JP2011067051A - Inverter, and electrical apparatus and solar power generator employing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inverter having a small switching loss and being at low cost. <P>SOLUTION: In the inverter, each arm A contains normally-on elements P and N-channel MOS transistors Q connected in series, built-in diodes D for the N-channel MOS transistors Q are used as free wheel diodes and the breakdown voltage of each N-channel MOS transistor Q is 10 to 50 V. Consequently, since the N-channel MOS transistors Q of low breakdown voltage are used, the reverse recovery currents of the built-in diodes D can be decreased, and the switching loss can be reduced. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an inverter, an electric device and a solar power generation device using the inverter, and more particularly to an inverter for converting DC power into AC power, and an electric device and a solar power generation device using the inverter.

  A junction field effect transistor and a static induction transistor that constitute a power semiconductor device are power semiconductor switching elements capable of realizing high-speed operation in a high voltage and high power region. This power semiconductor switching element is a normally-on element in which a drain current flows when the gate voltage is 0V. In a normally-on device, when a drain voltage is applied in a state where a negative voltage is not sufficiently applied to the gate electrode, a large drain current flows and the device is destroyed.

  For this reason, handling of normally-on elements is relatively difficult compared to normally-off elements such as bipolar transistors, insulated gate bipolar transistors, and MOS transistors. Therefore, a power semiconductor device using a serially connected body of normally-on elements and MOS transistors which are normally-off elements has been developed (see, for example, Patent Document 1).

  There is also an inverter in which each arm is configured by a serial connection body of normally-on elements and a plurality of MOS transistors and a high-speed diode connected in antiparallel to the serial connection body (see, for example, Patent Document 2).

JP 2001-251846 A JP 2006-158185 A

  However, when each arm of the inverter is configured by the serially connected body of the normally-on element and the MOS transistor of Patent Document 1 described above, there are the following problems. That is, when one of the upper and lower arms is turned on and then turned off, the built-in diode (parasitic diode) of the MOS transistor on the other arm is turned on. At this time, N-type and P-type minority carriers are accumulated in the P layer and N layer near the PN junction of the built-in diode, respectively.

  Next, when the arm on one side is turned on again, minority carriers accumulated in the built-in diode of the other arm flow to the built-in diode as reverse recovery current until a depletion layer is formed at the junction, causing reverse recovery loss. To do. The reverse recovery loss is a recovery loss of the built-in diode and occurs every recovery operation. Also, the reverse recovery current causes a through current to flow between the power supply and the ground via the normally-on element and the MOS transistor in the conduction transient state, thereby causing an increase in switching loss.

  In the inverter disclosed in Patent Document 2, since the ON voltage of the plurality of built-in diodes of the plurality of MOS transistors connected in series is higher than the ON voltage of the high-speed diode, the high-speed diode is turned on and the built-in diode is not turned on. Therefore, the switching loss due to the reverse recovery current of the built-in diode flowing into the normally-on element and the MOS transistor in the conduction transient state can be reduced. However, since this inverter uses an external high-speed recovery diode, there is a problem that the device price increases.

  Therefore, a main object of the present invention is to provide an inexpensive inverter with low switching loss, and an electric device and a solar power generation device using the inverter.

  An inverter according to the present invention is an inverter that converts DC power into N-phase AC power (where N is an integer of 2 or more), a first input terminal that receives the first DC voltage, A second input terminal that receives a second DC voltage that is lower than the first DC voltage, an N number of output terminals for outputting N-phase AC power, and a first input terminal corresponding to each output terminal, The first normally-on element and the first MOS transistor connected in series between the input terminal and the corresponding output terminal, and the corresponding output terminal and the second input are provided corresponding to each output terminal. A second normally-on element and a second MOS transistor connected in series with the terminal are provided. The gate of the first normally-on element is connected to the corresponding output terminal, and the gate of the second normally-on element is connected to the second input terminal. Each of the first and second MOS transistors is on / off controlled. The built-in diode of each of the first and second MOS transistors is used as a free wheel diode. The withstand voltage of the first and second MOS transistors is 10 to 50V.

  Preferably, each of the first and second normally-on elements is formed of a nitride semiconductor.

  An electric apparatus according to the present invention includes the inverter and a motor driven by AC power generated by the inverter.

  Moreover, the solar power generation device according to the present invention includes the inverter and a solar battery that supplies DC power to the inverter.

  In the inverter according to the present invention, the upper arm includes a first normally-on element and a first MOS transistor connected in series, and the lower arm includes a second normally-on element and a second MOS connected in series. A built-in diode of each of the first and second MOS transistors including a transistor is used as a freewheel diode, and the first and second MOS transistors have a withstand voltage of 10 to 50V. Therefore, since the diode built in the MOS transistor is used as a free wheel diode, the cost of the device can be reduced as compared with the conventional case where a high speed diode is separately provided. In addition, since the breakdown voltage of the MOS transistor is set as low as 10 to 50 V, the reverse recovery current of the built-in diode can be reduced, and the switching loss can be reduced.

1 is a circuit block diagram showing a configuration of an inverter according to an embodiment of the present invention and a method for using the inverter. It is sectional drawing which shows the structure of the normally on element shown in FIG. FIG. 2 is a cross-sectional view showing a configuration of an N-channel MOS transistor shown in FIG. FIG. 2 is a diagram showing the relationship between the breakdown voltage of the N-channel MOS transistor shown in FIG. 1 and the reverse recovery charge amount of a built-in diode. It is a figure for demonstrating the effect of this invention. FIG. 2 is a diagram showing the relationship between the breakdown voltage of the N-channel MOS transistor shown in FIG. 1 and inverter loss. It is a figure which shows the structure of the power module provided with the normally-on element and N channel MOS transistor shown in FIG.

  As shown in FIG. 1, the inverter according to the present embodiment includes input terminals T1 and T2, arms A1 to A6, output terminals TO1 to TO3, and a control unit 1. The positive terminal of the DC power source 2 is connected to the input terminal T1, and the negative electrode of the DC power source 2 is connected to the input terminal T2. The input terminal T2 is grounded.

  Arms A1 to A6 include normally-on elements P1 to P6, respectively. The drains of normally-on elements P1 to P3 are all connected to input terminal T1, and their gates are connected to output terminals TO1 to TO3, respectively. The drains of normally-on elements P4 to P6 are connected to output terminals TO1 to TO3, respectively, and their gates are all connected to input terminal T2.

  Arms A1 to A6 include N channel MOS transistors Q1 to Q6, respectively. The drains of N channel MOS transistors Q1-Q3 are connected to the sources of normally-on elements P1-P3, respectively, their sources are connected to output terminals TO1-TO3, respectively, and their gates are both connected to control unit 1. . The drains of N channel MOS transistors Q4 to Q6 are connected to the sources of normally on elements P4 to P6, respectively, their sources are both connected to input terminal T2, and their gates are both connected to control unit 1. The breakdown voltage of each of N channel MOS transistors Q1 to Q6 is set to 10 to 50V.

  For example, when the gate of N channel MOS transistor Q1 is set to “L” level by control unit 1 in arm A1, N channel MOS transistor Q1 is turned off. When N channel MOS transistor Q1 is turned off, the gate voltage of normally on element P1 becomes sufficiently lower than the source voltage, and normally on element P1 is turned off.

  When the gate of N channel MOS transistor Q1 is set to “H” level by control unit 1, N channel MOS transistor Q1 is turned on. When N-channel MOS transistor Q1 is turned on, the gate voltage of normally-on element P1 becomes substantially equal to the source voltage, and normally-on element P1 is turned on. That is, when the gate of N channel MOS transistor Q1 is set to “L” level, arm A1 is rendered non-conductive, and when the gate of N channel MOS transistor Q2 is set to “H” level, arm A1 is rendered conductive. The other arms A2 to A6 operate in the same manner as the arm A1.

  N-channel MOS transistors Q1 to Q6 incorporate diodes D1 to D6, respectively. Diodes D1-D6 are connected in antiparallel to N-channel MOS transistors Q1-Q6, respectively. Since the breakdown voltage of the N channel MOS transistors Q1 to Q6 is set to a low level of 10 to 60 V, the reverse recovery currents of the diodes D1 to D6 incorporated therein are also small. Each of the diodes D1 to D6 is used as a free wheel diode.

  For example, one terminals of a U-phase coil C1, a V-phase coil C2, and a W-phase coil C3 of the three-phase motor 3 are connected to the output terminals TO1 to TO3, respectively. The other terminals of the coils C1 to C3 are connected to each other. Control unit 1 performs on / off control of each of N-channel MOS transistors Q1 to Q6 at a predetermined timing, and converts DC power supplied from DC power supply 2 into three-phase AC power.

  For example, when the arm is shifted by 60 degrees in the order of A1, A6, A2, A4, A3, A5,... And turned into a conductive state by 180 degrees, the three-phase alternating current is transferred from the inverter to the coils C1 to C3 of the three-phase motor 3. A current flows, a rotating magnetic field is generated, and a rotor (not shown) of the motor 3 is rotationally driven.

  FIG. 2 is a cross-sectional view showing a configuration of a GaN field effect transistor that constitutes a normally-on element P. In FIG. 2, the GaN field effect transistor includes a silicon substrate 11. A source terminal 10 is formed on the back surface of the silicon substrate 11. On the surface of the silicon substrate 11, a buffer layer 12, a GaN layer 13, and an AlGaN layer 14 are sequentially stacked. The buffer layer 12 is made of, for example, AlGaN.

  A gate electrode 15 is formed on the surface of the AlGaN layer 14, and a gate terminal 16 is stacked on the surface of the gate electrode 15. On the surface of the AlGaN layer 14, a source electrode 17 is formed on one side of the gate electrode 15, and the source electrode 17 is sourced by a silicon substrate 11, a buffer layer 12, a GaN layer 13, and a through electrode 18 that penetrates the AlGaN layer 14. It is connected to the terminal 10.

  A drain electrode 19 is formed on the other side of the gate electrode 15 on the surface of the AlGaN layer 14. Portions other than the surface of the gate terminal 16 are covered with the polyimide resin layer 20. A drain terminal 21 is formed on the surface of the polyimide resin layer 20, and the drain terminal 21 is connected to the drain electrode 19 by a through electrode 22 that penetrates the polyimide resin layer 20.

  In this GaN field effect transistor, a high-concentration two-dimensional electron gas is formed in the vicinity of the heterojunction between the AlGaN layer 14 and the GaN layer 13, and high electron mobility is obtained. This GaN field effect transistor normally has a negative threshold voltage and is turned on when the gate voltage is 0V. Therefore, the GaN field effect transistor is a normally-on element.

FIG. 3 is a cross-sectional view showing the configuration of the N-channel MOS transistor Q. In FIG. 3, N channel MOS transistor Q includes an N ⁺ type silicon substrate 30. A drain electrode 31 is formed on the back surface of the N ⁺ -type silicon substrate 30, and the drain electrode 31 is connected to the drain terminal 32. An N-type drain layer 33 is formed on the surface of the N ⁺ -type silicon substrate 30, and a gate oxide film 34 and a gate electrode 35 are stacked on the surface of the N-type drain layer 33. The gate electrode 35 is connected to the gate terminal 36. A P-type region 37 is formed on each side of the gate electrode 35 on the surface of the N-type drain layer 33, and an N-type source region 38 is formed on the surface of the P-type region 37. P-type region 37 and N-type source region 38 are connected to source terminal 39.

  In this N channel MOS transistor Q, a diode D is formed by the P type region 37 and the N type drain region 33. N channel MOS transistor Q has a positive threshold voltage. When a voltage higher than the threshold voltage is applied between the gate terminal 36 and the source terminal 39, the drain terminal 32 and the source terminal 39 become conductive. When a voltage lower than the threshold voltage (for example, 0 V) is applied between the gate terminal 36 and the source terminal 39, the drain terminal 32 and the source terminal 39 become non-conductive. Therefore, N channel MOS transistor Q is a normally-off element.

The breakdown voltage of the N channel MOS transistor Q is determined by the distance L between the N ⁺ type silicon substrate 30 and the P type region 37. Increasing the distance L to increase the breakdown voltage of the transistor Q increases the on-resistance of the transistor Q. On the other hand, if the impurity concentration is decreased to increase the width of the depletion layer in order to increase the breakdown voltage of the transistor Q, the on-resistance of the transistor Q increases. Further, if the distance L is increased to lower the impurity concentration, the amount of minority carriers accumulated increases and the recovery characteristics deteriorate.

  In general, when MOS transistors having different breakdown voltages are produced while maintaining the on-resistance of the MOS transistor at a constant value, the chip area of the MOS transistor increases in proportion to the square of the breakdown voltage. Even in a recent super junction type high withstand voltage MOS transistor, the chip area increases in proportion to the withstand voltage.

  When a forward current flows through the built-in diode D of the N-channel MOS transistor Q, carriers are accumulated in the depletion layer of the diode D, and the accumulated carriers flow when the diode D is reverse-biased to become a reverse recovery current. . Therefore, reverse recovery current increases in N channel MOS transistor Q in which carriers are easily stored. The low breakdown voltage N-channel MOS transistor Q has a smaller area and a narrow depletion layer width than the high breakdown voltage N-channel MOS transistor having the same on-resistance, so that the number of carriers accumulated in the depletion layer is reduced and reverse recovery is achieved. The current becomes smaller.

  FIG. 4 is a diagram showing the relationship between the on-resistance (mΩ) and the reverse recovery charge amount (nC) in the MOS transistor. As the MOS transistor, a high breakdown voltage MOS transistor having a breakdown voltage of 500V and a low breakdown voltage MOS transistor having a breakdown voltage of 20V were used. In FIG. 4, the reverse recovery charge amount decreases in proportion to the on-resistance. The reverse recovery charge amount of the high voltage MOS transistor is 10000 nC. Therefore, when this high voltage MOS transistor is used for an inverter, a large reverse recovery current flows and a large reverse recovery loss occurs.

  On the other hand, if the on-resistance of the low breakdown voltage MOS transistor is 10 mΩ, the reverse recovery current is 60 nC, which is 1/100 or less of the reverse recovery current of the high breakdown voltage MOS transistor. Therefore, in the present invention, the low breakdown voltage N-channel MOS transistors Q1 to Q6 are used, so that the reverse recovery current of the built-in diodes D1 to D6 can be sufficiently reduced, and the switching loss in the inverter can be reduced.

  FIG. 5 (a) is a diagram showing waveforms of voltage V and current I of normally-on element P1 when arm A1 is changed from a non-conductive state to a conductive state in the inverter of the present invention. FIG. 5B is a diagram showing waveforms of voltage V and current I of the positive high-breakdown-voltage N-channel MOS transistor in a conventional normal inverter composed of six high-breakdown-voltage N-channel MOS transistors. . In each of FIGS. 5A and 5B, the peak of the current I is surrounded by a dotted circle. As can be seen from FIGS. 5A and 5B, the reverse recovery current in the inverter of the present invention is clearly smaller than the reverse recovery current in the conventional inverter.

  FIG. 6 is a diagram showing the relationship between the breakdown voltage (V) of N channel MOS transistor Q and the loss (W) of the inverter. In FIG. 6, when the breakdown voltage of the N channel MOS transistor Q is increased, the loss increases exponentially. In particular, when the breakdown voltage of the N channel MOS transistor Q exceeds 50V, the loss increases rapidly. Therefore, the upper limit of the breakdown voltage of N channel MOS transistor Q is about 50V. On the other hand, when the breakdown voltage of N channel MOS transistor Q is smaller than the absolute value | Vth | (for example, 5 V) of the threshold voltage of normally-on element P, normally-on element P does not turn off. An overdrive voltage of about 5V is also required. Therefore, it is optimal to set the breakdown voltage of N channel MOS transistor Q to a value between 10V and 50V.

  FIG. 7 is a diagram showing a main part of a power module including normally-on element P and N-channel MOS transistor Q. In FIG. 7, the normally-on element P chip and the N-channel MOS transistor Q chip are mounted on the surface of the substrate 40. The source terminal (not shown) of the normally-on element and the drain terminal (not shown) of the N-channel MOS transistor Q are connected to each other via an electrode formed on the surface of the substrate 40.

  The gate terminal 41 of the N channel MOS transistor Q is connected to the lead frame F1 by a bonding wire W1. The source terminal 42 of the N channel MOS transistor Q is connected to the lead frame F3 by a bonding wire W2. The gate terminal 43 of the normally-on element P is connected to the lead frame F3 by a bonding wire W3. The drain terminal 44 of the normally-on element P is connected to the lead frame F2 by a bonding wire W4. Portions other than the tip portions of the lead frames F1 to F3 are sealed and fixed with resin. This power module constitutes one arm A shown in FIG.

  In this embodiment, each arm A of the inverter is constituted by a normally-on element P and an N-channel MOS transistor Q connected in series, and the built-in diode D of the N-channel MOS transistor Q is used as a freewheel diode. That is, when one of the upper and lower arms becomes conductive and becomes non-conductive, the internal diode D of the N-channel MOS transistor Q of the other arm becomes forward biased, and the internal diode D becomes conductive. Since the forward voltage of the built-in diode D is lower than the threshold voltage of the normally-on element P, the normally-on element P becomes conductive, so-called from the built-in diode D of the N-channel MOS transistor Q via the normally-on element P. Regenerative current flows. Therefore, the built-in diode D operates as a freewheel diode. The breakdown voltage of the N channel MOS transistor Q is set to 10 to 50V. Therefore, it is possible to reduce the cost of the device as compared with the conventional case where a high-speed diode is separately provided as a freewheel diode. Further, since the low breakdown voltage N-channel MOS transistor Q is used, the reverse recovery current of the built-in diode D can be reduced, and the switching loss can be reduced.

  Further, when the regenerative current flows, a nitride semiconductor, for example, a FET using GaN is used as the normally-on element P, so that a high mutual conductance gm of the GaN FET and a built-in diode of the low breakdown voltage N-channel MOS transistor Q A combination of forward voltages with a low D can realize a low forward voltage and reduce loss. In particular, when the regenerative operation is performed, a surge voltage is generated unless the high breakdown voltage normally-on element P is conducted at high speed. However, FETs using GaN are excellent in high speed and can suppress the occurrence of surge. it can. Furthermore, since GaNFET does not accumulate minority carriers, it turns off at high speed when reverse recovery operation is performed after regenerative operation. For this reason, the loss resulting from reverse recovery can be reduced.

  In this embodiment, the case where the present invention is applied to a three-phase inverter has been described. Needless to say, the present invention is also applicable to a two-phase inverter. The two-phase inverter is obtained by removing the arms A3 and A6 and the output terminal TO3 from the three-phase inverter of FIG. In the two-phase inverter, arms A1 and A5 and arms A2 and A4 are alternately turned on by 180 degrees.

  In addition, the inverter of the present invention can be used for any electric equipment, and low power consumption of the electric equipment can be realized. Specifically, it can be used as an AC power source for a compressor motor such as a refrigerator or an air conditioner, or an AC power source for a motor that rotates a drum of a washing machine.

  The inverter of the present invention is also effective when converting direct current power generated by a solar cell into alternating current power in a photovoltaic power generation system. Also in this case, the power loss in the inverter can be reduced.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

A arm, P normally on element, Q N-channel MOS transistor, D diode, T input terminal, TO output terminal, C coil, 1 control unit, 2 DC power supply, 3 motor, 10, 39, 42 source terminal, 11 silicon Substrate, 12 Buffer layer, 13 GaN layer, 14 AlGaN layer, 15 Gate electrode, 16, 36, 41, 43 Gate terminal, 17 Source electrode, 18, 22 Through electrode, 19 Drain electrode, 20 Polyimide resin layer, 21, 32 , 44 Drain terminal, 30 N ⁺ type silicon substrate, 31 Drain electrode, 33 N type drain region, 34 Gate oxide film, 35 Gate electrode, 37 P type region, 38 N type source region, 40 substrate, W bonding wire, F Lead frame.

Claims (4)

An inverter that converts DC power into AC power of N-phase (where N is an integer of 2 or more),
A first input terminal receiving a first DC voltage;
A second input terminal for receiving a second DC voltage lower than the first DC voltage;
N output terminals for outputting the N-phase AC power;
A first normally-on element and a first MOS transistor provided corresponding to each output terminal and connected in series between the first input terminal and the corresponding output terminal;
A second normally-on element and a second MOS transistor provided corresponding to each output terminal and connected in series between the corresponding output terminal and the second input terminal;
A gate of the first normally-on element is connected to a corresponding output terminal; a gate of the second normally-on element is connected to the second input terminal;
Each of the first and second MOS transistors is on / off controlled,
The built-in diode of each of the first and second MOS transistors is used as a freewheel diode,
An inverter having a withstand voltage of 10 to 50 V of the first and second MOS transistors.   The inverter according to claim 1, wherein each of the first and second normally-on elements is formed of a nitride semiconductor. An inverter according to claim 1 or claim 2,
An electric device comprising: a motor driven by AC power generated by the inverter. An inverter according to claim 1 or claim 2,
A solar power generation apparatus comprising: a solar battery that supplies DC power to the inverter.

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