CN102308383B - 半导体管芯封装件及其制造方法 - Google Patents

半导体管芯封装件及其制造方法 Download PDF

Info

Publication number
CN102308383B
CN102308383B CN201080007032.4A CN201080007032A CN102308383B CN 102308383 B CN102308383 B CN 102308383B CN 201080007032 A CN201080007032 A CN 201080007032A CN 102308383 B CN102308383 B CN 102308383B
Authority
CN
China
Prior art keywords
clamp structure
lead frame
semiconductor die
semiconductor element
molded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201080007032.4A
Other languages
English (en)
Other versions
CN102308383A (zh
Inventor
A·V·C·杰瑞扎
P·A·卡罗
E·V·R·克鲁兹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fairchild Semiconductor Corp
Original Assignee
Fairchild Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fairchild Semiconductor Corp filed Critical Fairchild Semiconductor Corp
Priority to CN201410583922.XA priority Critical patent/CN104485321B/zh
Publication of CN102308383A publication Critical patent/CN102308383A/zh
Application granted granted Critical
Publication of CN102308383B publication Critical patent/CN102308383B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49524—Additional leads the additional leads being a tape carrier or flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/38—Structure, shape, material or disposition of the strap connectors prior to the connecting process of a plurality of strap connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/40247—Connecting the strap to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73263—Layer and strap connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/84801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/8485—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Die Bonding (AREA)

Abstract

一种半导体管芯封装件。该半导体管芯封装件包括预模制夹具结构组件，该预模制夹具结构组件具有夹具结构、附连于夹具结构的半导体管芯以及覆盖夹具结构和半导体管芯的至少一部分的第一模制材料。半导体管芯封装件还包括具有管芯附连焊盘的引线框结构，其中该引线框结构附连于预模制夹具结构组件。

Description

半导体管芯封装件及其制造方法
关联申请的交叉引用
不适用
背景技术
半导体管芯封装件是半导体业内公知的，但可以改进。例如，诸如无线电话等电子设备正变得越来越小。要求制造出更小的半导体管芯封装件，以使它们能包含在这些电子设备中。然而，更小的封装件经常要求更小的半导体管芯。这可能影响性能并增大接触电阻。也要求改善传统半导体管芯封装件的散热性能。包含例如功率晶体管的半导体管芯封装件产生大量热量。也要求向这些半导体管芯封装件的最终使用者提供健全的互连选择。
一些半导体管芯封装件具有预模制夹具结构。该预模制夹具结构可包括模制材料和夹具结构。诸如此类的预模制夹具结构可使用第一焊料材料附连于半导体管芯，而半导体管芯可使用第二焊料材料附连于引线框结构。当第一和第二焊料材料在半导体管芯封装件的制造过程中回流时，它们可能相对于彼此移位。这可能如图8(a)所示地不合需地使预模制夹具结构60相对于引线框结构和/或半导体管芯62转动。另外，如图8(b)所示，在用于形成具有预模制夹具结构的半导体管芯封装件的现有技术方法中，当将焊料施加于小栅极焊盘上时，焊膏的体积也是难以控制的，由此造成栅极焊料溢出至半导体管芯的角落处。图8(b)示出溢出半导体管芯62边缘的焊料80。焊料80接触预模制夹具结构60中的栅极夹具结构60(g)的一部分。如图8(b)所示，示出引线框结构61并且引线框结构61支承半导体管芯62。
本发明的诸实施例单独或全体地解决了这些和其它问题。
发明内容
本发明的实施例针对半导体管芯封装件及其制造方法。
本发明的一个实施例针对一半导体管芯封装件，该半导体管芯封装件包括：预模制夹具结构组件，该预模制夹具结构组件具有夹具结构、附连于夹具结构的半导体管芯以及覆盖夹具结构和半导体管芯的至少一部分的第一模制材料。该半导体管芯封装件还包括具有管芯附连焊盘的引线框结构，其中引线框结构附连于预模制夹具结构组件。
本发明的另一实施例针对一种方法，包括：获得引线框结构；并使预模制夹具结构组件附连至引线框结构，该预模制夹具结构组件包括夹具结构、附连于夹具结构的半导体管芯以及覆盖夹具结构和半导体管芯的至少一部分的第一模制材料。
本发明的另一实施例针对一种半导体管芯封装件，包括：包含引线框结构表面的引线框结构；附连于引线框结构的半导体管芯，其中半导体管芯包括含有输入区的第一表面以及含有输出区的第二表面；覆盖半导体管芯和引线框结构的至少一部分的模制材料，其中模制材料露出半导体管芯的第二表面并还露出引线框结构表面；金属外壳结构，其包括主部和从主部伸出的第一脚以及从主部伸出并与第一脚相对的第二脚，其中金属外壳在半导体管芯的第二表面处电气和机械地耦合于输出区；以及导电粘合剂，该导电粘合剂耦合金属外壳结构的主部和半导体管芯的第二表面。
本发明的另一实施例针对一种方法，包括：将半导体管芯附连于引线框结构，该引线框结构包括引线框结构表面，其中半导体管芯包括具有输入区的第一表面以及具有输出区的第二表面；将模制材料模制在半导体管芯和引线框结构的至少一部分周围，其中模制材料露出半导体管芯的第二表面并还露出引线框结构表面；并将金属外壳结构附连于半导体管芯，该金属外壳结构包括主部和从主部伸出的第一脚以及从主部伸出并与第一脚相对的第二脚，其中第二表面处的输出区电气和机械地耦合于金属外壳结构。
本发明的其它实施例针对能容纳根据本发明诸实施例的半导体管芯封装件的电气组件和系统。
本发明的这些和其它实施例参照附图在说明书中有详细描述。在附图中，相同的附图标记可表示相同的要素并且不再对一些要素作重复说明。另外，在附图中，一些要素可能不按照比例绘出。
附图说明
图1示出根据本发明一个实施例的半导体管芯封装件的横截面侧视图。
图2示出根据本发明一实施例的预模制夹具结构组件的横截面侧视图。
图3示出根据本发明另一实施例的半导体管芯封装件的横截面侧视图。
图4示出根据本发明另一实施例的预模制夹具结构组件的横截面侧视图。
图5示出根据本发明另一实施例的半导体管芯封装件的横截面侧视图。
图6示出根据本发明另一实施例的预模制夹具结构组件的横截面侧视图。
图7(a)-7(g)示出根据本发明一个实施例的在半导体管芯封装件成形过程中形成的多个前身结构。
图7(h)示出根据本发明一个实施例的半导体管芯封装件的立体图。
图8(a)和8(b)示出预模制夹具使用传统工艺安装在半导体管芯上时的照片。
图9示出根据本发明一个实施例的半导体管芯封装件的横截面侧视图。
图10(a)-10(b)各自示出另一半导体管芯封装件实施例的顶视立体图和底视立体图。
图11示出图10(a)和图10(b)所示的半导体管芯封装件实施例的底视立体图。模制材料的部分被移去。
图12(a)-12(e)示出半导体管芯封装件成形过程中形成的诸个前身结构，以及半导体管芯封装件的例子。
图12(f)示出根据本发明一个实施例的半导体管芯封装件的例子。
图13(a)-13(e)示出根据本发明另一实施例在半导体管芯封装件成形过程中形成的前身结构。
图13(f)示出根据本发明另一实施例的半导体管芯封装件的例子。
图14(a)示出具有两个金属外壳结构的半导体管芯封装件的底视立体图。
图14(b)示出具有两个金属外壳结构的半导体管芯封装件的顶视立体图。
图15示出根据本发明的实施例可用于半导体管芯封装件的垂直式功率MOSFET的横截面图。
在附图中，相同的附图标记表示相同要素并且不再对一些相似要素作重复说明。关于本发明诸实施例的其它细节参照附图在具体实施方式中给出。
具体实施方式
I.包括预模制夹具组件的半导体管芯封装件
图1示出根据本发明一个实施例的半导体管芯封装件100的横截面侧视图。图2示出根据本发明一个实施例的预模制夹具结构组件的横截面侧视图。
半导体管芯封装件100包括：预模制夹具结构组件160，该预模制夹具结构组件160包括夹具结构160(a)；以及使用第一导电粘合剂180(a)附连于夹具结构160(a)的半导体管芯150。半导体管芯150包括第一主表面150-1以及与第一主表面150-1相对的第二主表面150-2。第一导电粘合剂180(a)与半导体管芯150的第二表面150-2接触。第一表面150-1可包括例如漏极区的输出区，而第二主表面150-2可包括例如源极区和栅极区的输入区。
第一模制材料160(b)，例如环氧树脂模制材料，覆盖夹具结构160(a)和半导体管芯150的至少一部分。如图2所示，第一模制材料160(b)具有第一表面160(b)-1，该第一表面160(b)-1基本与半导体管芯150的第一表面150-1共面。第一模制材料160(b)的第二表面160(b)-2也可基本与夹具结构160(a)的顶表面160(a)-1共面。夹具结构160(a)的顶表面160(a)-1和第一模制材料160(b)的第二表面160(b)-2可形成预模制夹具结构组件160的第一表面160-1。预模制夹具结构组件160的第二表面160-2与第一表面160-1相对。预模制夹具结构组件160的第二表面160-2包括至少第一模制材料表面160(b)-1以及半导体管芯150的第一表面150-1。
参见图1，半导体管芯封装件100还包括引线框结构190，该引线框结构190包括管芯附连焊盘。引线框结构190使用第二导电粘合剂180(b)和第三导电粘合剂180(c)附连于预模制夹具结构组件160。
引线框结构190可包括数个不同部分，这些部分包括漏极引线结构190(d)，该漏极引线结构190(d)可包括管芯附连焊盘以及从管芯附连焊盘伸出的数根引线。它也可包括源极引线结构190(s)以及与源极引线结构190(s)电气隔绝的栅极引线结构(图1未示出)。
如前所述的第一、第二和第三导电粘合剂180(a)、180(b)、180(c)可包括任何适宜的导电粘合材料。示例包括导电环氧树脂以及焊料(例如基于铅的焊料或无铅焊料)。在一些实施例中，由于预模制夹具结构组件160是在附连于引线框结构190之前形成的，因此第一导电粘合剂180(a)可具有比第二和第三导电粘合剂180(b)、180(c)更高的熔化温度。
由虚线表示的第二模制材料170(例如环氧树脂模制材料)覆盖预模制夹具结构组件160的至少一部分以及引线框结构190的一部分。如图1所示，第二模制材料170的底部外表面基本与包含源极引线结构表面190(s)-1和漏极引线结构表面190(d)-1的引线框结构190的外表面共面。当被安装于底层电路板(未示出)等时，源极引线结构表面190(s)-1和漏极引线结构表面190(d)-1可与又一导电粘合剂接触。
第二模制材料170可与第一模制材料160(b)相同或不同。由于它们是在不同时间形成的，因此在半导体管芯封装件100中的第一和第二模制材料160(b)、170之间存在一界面。
在本申请描述的这个和其它实施例中的半导体管芯150可包括任何适宜的半导体器件(例如p沟道MOSFET管芯和n沟道MOSFET管芯)，并可以是垂直式器件。垂直式器件至少在管芯的一侧具有一输入而在管芯的另一侧具有一输出，以使电流可垂直地流过管芯。
在某些实现中，一些垂直式器件的示例包括垂直式功率MOSFET、垂直二极管、VDMOS晶体管、垂直双极晶体管等。适宜的半导体包括硅、砷化镓以及其它所谓的“Ⅲ-Ⅴ”和“Ⅱ-Ⅵ”半导体材料。VDMOS晶体管是具有通过扩散形成的两个或更多个半导体区域的MOSFET。它具有源极区、漏极区以及栅极。器件是垂直的，因为源极区和漏极区处于半导体管芯相对的两个表面上。栅极可以是带沟槽的栅极结构或平面栅极结构，并形成在与源极相同的表面上。带沟槽的栅极结构可以更窄并占据比平面栅极结构更少的空间。在工作中，VDMOS器件中从源极区域流至漏极区域的电流基本垂直于管芯表面。垂直式功率MOSFET的一个示例示出于图15。
图3示出根据本发明另一实施例的半导体管芯封装件100的横截面侧视图。图4示出根据本发明另一实施例的预模制夹具结构组件的横截面侧视图。
图3中的半导体管芯封装件类似于图1所示的半导体管芯封装件。另外，图4中的预模制夹具结构组件160类似于图2所示的夹具结构组件。然而，在图3-4所示的实施例中，第一模制材料160(b)覆盖夹具结构160(a)的表面160(a)-1。
图5示出根据本发明另一实施例的另一半导体管芯封装件100的横截面侧视图。图6示出根据本发明另一实施例的预模制夹具组件结构的横截面侧视图。
图5所示的半导体管芯封装件类似于图1所示的半导体管芯封装件。另外，图6中的预模制夹具结构组件160类似于图2所示的预模制夹具结构组件。然而，在图5-6所示实施例中，预模制夹具结构组件160包括附连于第一半导体管芯150的第一夹具结构160(a)以及附连于第二半导体管芯151的第二夹具结构160(d)。因此，半导体管芯封装件100和预模制夹具结构组件160各自包括两个半导体管芯和两个夹具结构。尽管它们包括四个半导体管芯和两个夹具结构，然而本发明的实施例可包括具有更多或更少半导体管芯和夹具结构的封装件和组件。
在半导体管芯封装件100中，模制材料区160(b)-1将半导体管芯封装件100中的第一夹具结构160(a)和第二夹具结构160(d)分开。另外，模制材料160(b)的底表面可基本与半导体管芯表面150-1、151-1共面。
本发明的其它实施例针对形成半导体管芯封装件的方法。在本发明的一个实施例中，该方法包括：获得引线框结构，并将预模制夹具结构组件附连于引线框结构。预模制夹具结构组件包括夹具结构、附连于夹具结构的半导体管芯以及覆盖夹具结构和半导体管芯的至少一部分的第一模制材料。根据本发明诸实施例的形成半导体管芯封装件的示例性方法可参照图7(a)-7(h)予以描述。
本发明的实施例可包括形成预模制夹具结构组件。用于形成预模制夹具结构组件的过程可包括：获得夹具结构；使用导电粘合剂将半导体管芯附连于夹具结构；并将第一模制材料模制在夹具结构和半导体管芯的至少一部分周围。
在预模制夹具结构组件的成形中，可首先获得夹具结构，例如图7(a)所示的夹具结构160(a)。在图7(a)中，示出两个夹具结构160(a)、161并且它们与框架192耦合在一起。两个夹具结构160(a)、161可用来形成半导体管芯封装件，该半导体管芯封装件包括两个夹具结构160(a)、161以及安装在每个夹具结构160(a)、161上的两个半导体管芯。
夹具结构160(a)、161可具有任何适宜的结构或厚度(例如1mm或更小)。在该例中，夹具结构160(a)包括主部160(s)，该主部160(s)可以是包含狭槽160(s)-1的源极部分，该狭槽160(s)-1可用作模具锁紧特征。栅极部分160(g)也出现在夹具结构160(a)中并在制成的半导体管芯封装件中可与主部160(s)电气隔绝。夹具结构161还包括主部161(s)，该主部161(s)包括狭槽161(s)-1(它也充当源极端子)。栅极部分161(g)也出现在夹具结构161中并在制成的半导体管芯封装件中与主部161(s)电气隔绝。另外，夹具结构160(a)、161也可具有脚部(例如160(f)、161(f)、160(h)、161(h))，这些脚部相对于主部160(s)、161(s)和栅极部分160(g)、161(g)中的每一个是隆起的。
夹具结构160(a)、161可包括任何适宜的材料。例如，诸如铜、铝和贵金属(及其合金)的导电材料可用于夹具结构160(a)、161中。该夹具结构160(a)、161也可镀有可焊接层，如果需要的话。
夹具结构160(a)、161也可以任意方式形成，包括蚀刻、压印等。
如图7(b)所示，在获得夹具结构160(a)、161后，例如焊料的第一导电粘合剂180(a)可沉积在夹具结构160(a)、161的主部160(s)、161(s)以及栅极部分160(g)、161(g)的诸部分上，同时使夹具结构160(a)、161的隆起的脚部160(f)、161(f)、160(h)、161(h)保持裸露。可使用任何适宜的焊料沉积工艺。
如图7(c)所示，第一和第二半导体管芯150、151被安装在第一夹具结构160(a)上，同时第三和第四半导体管芯152、153被安装在第二夹具结构161上。在该实施例中，半导体管芯150、151、152、153可各自包括垂直式功率MOSFET。
如图7(d)所示，在半导体管芯150、151、152、153被安装在夹具结构160(a)、161上之后，使第一模制材料160(b)形成在夹具结构160(a)、161以及半导体管芯150、151、152、153的至少诸个部分周围以形成预模制夹具结构组件160。如图所示，半导体管芯150、151、152、153的第一表面150-1、151-1、152-1、153-1通过第一模制材料160(b)露出并且它们基本与第二模制材料160(b)的外表面共面。
可使用任何适宜的模制工艺。适宜的模制工艺可包括带协助模制工艺或注塑模制工艺。适宜的工艺因素可由本领域内普通技术人员确定。
在模制后，可执行单体化工艺。图7(e)示出不具有前述框架192的预模制夹具结构组件160。
参见图7(f)，在形成预模制夹具结构组件160之前或之后，获得引线框结构190。该引线框结构可通过任何适宜的方式获得。例如，引线框结构190可使用传统工艺被压印、蚀刻和/或图案化以形成引线或引线框结构的其它部分。例如，引线框结构190可通过蚀刻连续导电薄板以形成预定图案来形成。如果使用压印，则引线框结构可以是在通过连杆相连的引线框结构阵列中的许多引线框结构中的一个。也可切割引线框结构阵列以使一些引线框结构与其它引线框结构分离。引线框结构190可以是连续的金属结构或不连续的金属结构。
术语“引线框结构”可指从引线框衍生出或与引线框相同的结构。每个引线框结构可包括具有引线表面和管芯附连区域的一个或多个引线。引线可横向地从管芯附连区域伸出。
引线框结构190可包括任何适宜的材料并可具有任何适宜的特性。示例性引线框结构材料包括金属，例如铜、铝、金等及其合金。引线框结构也可包括镀层，例如金、铬、银、钯、镍等镀层。引线框结构也可具有本领域内技术人员公知的任何适宜厚度。引线框结构190也可具有任何适宜的厚度，包括小于约1mm的厚度(例如小于约0.5mm)。
在图7(f)中，引线框结构190包括数个栅极引线结构190(g)、源极引线结构190(s)以及漏极引线结构190(d)。它们能电气耦合于所形成的半导体管芯封装件中的一个或多个半导体管芯内的栅极区、源极区和漏极区。如图7(f)所示，第二导电粘合剂180(b)沉积在漏极引线结构190(d)上，而第三导电粘合剂180(c)沉积在源极引线结构190(s)上。
如图7(g)所示，在引线框结构190涂覆以焊料后，之前形成的预模制夹具结构组件160随后翻转并安装在引线框结构190上并使用至少第二和第三导电粘合剂180(b)、180(c)电气耦合于引线框结构190。
参见图7(h)，第二模制材料170随后形成在预模制夹具结构组件160和引线框结构190周围以形成半导体管芯封装件100。可使用任何适宜的模制和后继的单体化工艺。
尽管图7(a)-7(h)中示出一个半导体管芯封装件的成形，然而要理解，在本发明的实施例中可同时形成半导体管芯封装件的阵列。
可使用本发明的实施例来形成PQFN(功率四方扁平无引线)、MLP(微引线框封装件)以及其它类型的封装件。
本发明的实施例提供许多优势。例如，由于预模制夹具结构组件包括半导体管芯，在半导体管芯安装于引线框结构前该半导体管芯与夹具结构对准。预模制夹具结构组件可随后在附连时相对于引线框结构对准。由于将半导体管芯连接于夹具结构的焊料材料以及将引线框结构连接于半导体管芯的焊料材料不同时回流，因此图8(a)和8(b)所示的夹具旋转和焊料悬伸问题不大可能发生。另外，由于半导体管芯封装件的最终组装不大可能具有缺陷，因此返工的半导体管芯封装件的数量减少。另外，所形成的半导体管芯封装件是紧凑的并具有良好的散热特性。
Ⅱ包含金属外壳的半导体管芯封装件
本发明的其它实施例针对具有改进的散热能力的半导体管芯封装件。本发明的实施例可与普通半导体封装件的普通版面图案一起使用并具有良好的顶部和底部冷却特性，同时提供对半导体管芯的良好保护。
本发明的一个实施例针对具有例如硅管芯的半导体管芯的半导体管芯封装件。该半导体管芯封装件附连于具有栅极和源极部分引线框结构。使半导体管芯附连于引线框结构是由焊料提供的，该焊料在引线框结构的栅极和源极部分。硅管芯和引线框结构被模制，且引线框结构的栅极和源极部分的表面通过模制材料露出。半导体管芯的背侧也通过模制材料露出。经模制的引线框结构和硅管芯随后附连于例如铜外壳的金属外壳。将铜外壳附连于经模制的引线框结构和硅管芯是由露出的硅背侧上的焊料提供的。铜外壳为半导体管芯封装件提供漏极连接并允许封装件通过半导体管芯封装件顶部的冷却。
图9示出半导体管芯封装件10，该半导体管芯封装件10包括：引线框结构9，该引线框结构9包括引线框结构表面9-1；以及附连于引线框结构9的半导体管芯16。半导体管芯16包括构成输入区(例如源极区)的第一表面16-1以及构成输出区(例如漏极区)的第二表面16-2。模制材料14覆盖半导体管芯16和引线框结构9的至少一部分。模制材料14使半导体管芯16的第二表面16-2露出并还使引线框结构表面9-1露出。模制材料14的外表面14-1可基本与半导体管芯16的第二表面16-2共面。
半导体管芯封装件10还包括金属外壳结构11，该金属外壳结构11包括主部11(a)以及从主部11(a)伸出的第一脚11(b)和从主部11(a)伸出的第二脚11(c)。第一和第二脚11(b)、11(c)可处于主部11(a)的相对侧。如图9所示，模制材料14的底表面14-2、引线框结构9的底表面9-1以及脚11(b)、11(c)的底表面可以是基本共面的。
金属外壳11电气和机械地耦合于半导体管芯16的第二表面16-2处的输出区。第一导电粘合剂15耦合金属外壳结构11的主部11(a)和半导体管芯16的第二表面16-2。第二和第三导电粘合剂17、18将半导体管芯16的第一表面16-1处的栅极区和源极区电耦合于引线框结构9的源极结构13和栅极结构12。引线框结构9的源极结构13和栅极结构12可各自具有源极引线结构表面13-1和栅极引线结构表面12-1，它们由部分蚀刻工艺界定。
每个脚11(a)、11(b)包括侧壁(它可以是实心的并至少延伸直至模制材料14的侧部)以及垂直于侧壁的底部，该底部耦合于电路基板4的导电焊接区4(d)。栅极结构表面12-1和源极结构表面13-1可相应地安装在焊盘4(s)和4(g)上。半导体管芯封装件10和电路基板4可一起形成电组件。
尽管金属外壳结构包括两个脚，然而它在本发明其它实施例中也可包括三个或甚至四个脚。另外，金属外壳结构可包括任何适宜的厚度(例如小于大约1mm)。
如图9所示，模制材料14-1的侧壁与作为脚11(b)和脚11(c)的一部分的壁间隔开，由此提供具有更大散热表面积的脚11(b)、11(c)。
图10(a)-10(b)分别示出另一半导体管芯封装件实施例的顶部和底视立体图。
图11示出图10(a)和图10(b)所示的半导体管芯封装件实施例的底视立体图。模制材料部分被移去。如图11所示，源极结构12包括细长部分12-1和垂直部分12(b)，该垂直部分12(b)具有处于与栅极结构表面12-1略微不同平面内的表面。该垂直部分12(b)覆盖有模制材料14。该漏极结构也具有通过部分蚀刻界定的表面13-1。图11还示出在源极结构13中的细长孔18。该孔18可作为模具锁紧特征并作为焊料溢出的空间。
图12(a)-12(e)示出在半导体管芯封装件成形期间形成的前身结构。
图12(a)示出在已通过晶片锯锯切后的引线框结构9。尽管示出了一个引线框结构9，然而在其它实施例中，引线框结构9在加工过程中可以处于引线框结构的一个阵列中。
在获得引线框结构9后，导电粘合剂沉积在引线框结构9上。图12(b)示出在将第二和第三导电粘合剂17、18沉积在引线框结构9上之后的引线框结构9。
在将导电粘合剂沉积在引线框结构9上之后，如图12(c)所示，半导体管芯16使用拾取和放置工艺、倒装芯片管芯附连工艺等安装在引线框结构9上。此时也可执行传统的焊料回流工艺。
在将半导体管芯16放置到引线框结构9上之后，如图12(d)所示，模制材料14形成在引线框结构9和半导体管芯16的诸部分周围。模制材料14露出半导体管芯16的表面16-1。可采用例如带协助模制工艺的模制工艺来对模制材料进行模制。如果需要的话，可随后执行封装件锯切工艺。
如图12(e)所示，在对模制材料14进行模制后，将第一导电粘合剂15沉积在半导体管芯16的露出表面16-1上。第一导电粘合剂15可具有比第二和第三导电粘合剂17、18更低的回流温度。在将第一导电粘合剂沉积在露出的表面16-1之后，可执行回流工艺。
如图12(f)所示，在将第一导电粘合剂15沉积到管芯表面16-1上之后，金属外壳结构11被放置在第一导电粘合剂15上以使其固定于半导体管芯16。也可执行冲裁单体化工艺。
图13(a)-(e)示出在半导体管芯封装件成形过程中形成的前身结构。
图13(a)示出在已用晶片锯锯切后的金属外壳结构11。
图13(b)示出通过第一导电粘合剂15安装在金属外壳结构11上的半导体管芯16。
图13(c)示出在已锯切后的引线框结构9。如前所述，引线框结构9在加工过程中可替代地处于阵列中。
图13(d)示出形成在引线框结构9周围的模制材料14。如图所示，模制材料14的表面14-1和栅极结构的表面12-1以及源极结构的表面13-1是基本共面的。在模制后，之后形成预模制的衬底。
图13(e)示出沉积在半导体管芯16上的第二和第三导电粘合剂17、18。
参见图13(f)，在导电粘合剂17、18沉积到半导体管芯16上之后，将预模制的衬底放置在半导体管芯16上以形成半导体管芯封装件2。半导体管芯封装件2与图12(f)所示的半导体管芯封装件10不同。在图13(f)中的半导体管芯封装件2中，模制材料14不围住半导体管芯16的边缘，而在图12(f)中的半导体管芯封装件10中则围住。
图14(a)示出具有两个金属外壳的半导体管芯封装件6的底视立体图。
图14(b)示出具有两个金属外壳的半导体管芯封装件6的顶视立体图。
包含该金属外壳结构的实施例具有许多优势。例如，它们具有良好的顶部和底部冷却特性并还能满足在电路衬底上的标准工业焊接区布图。该半导体管芯还通过模制材料的使用而受到保护而免受环境影响。
任何前述的半导体管芯封装件可用于包含其上安装有封装件的电路板的电气组件。这些电气组件可用于例如电话、计算机等的系统中。
对“一”、“一个”和“该”的任何引述旨在表示一个或多个，除非特别声明表示相反情况。
已在本文中使用的术语和表达用作描述性而非限定性术语，并且不打算使用这些术语和表达来排除图示和描述的特征的等效物，要理解在要求的发明范围内可具有多种修正。
此外，本发明的一个或多个实施例的一个或多个特征可与本发明的其它实施例的一个或多个特征组合而不脱离本发明的范围。例如，关于引线框结构、导电粘合剂以及与前述包含预模制夹具结构组件的半导体管芯封装件关联的加工条件的具体细节也可用于包含金属外壳结构的半导体管芯封装件。
尽管已结合所示实施例具体描述了本发明，然而要理解可基于本公开作出多种替代、修改、适应和等效配置，并且这些替代、修改、适应和等效配置均落在本发明和所附权利要求书的范围内。

Claims (10)

1.一种半导体管芯封装件，包括：
预模制夹具结构组件，所述预模制夹具结构组件包含夹具结构、附连于所述夹具结构的半导体管芯以及覆盖所述夹具结构的至少一部分和所述半导体管芯的至少一部分的第一模制材料；
包含管芯附连焊盘的引线框结构，其中所述引线框结构附连于预模制夹具结构组件；以及
覆盖所述引线框结构的至少一部分和预模制夹具结构组件的至少一部分的第二模制材料，其中所述第一模制材料与所述第二模制材料接触，在所述第一模制材料和所述第二模制材料之间存在界面。
2.如权利要求1所述的半导体管芯封装件，其特征在于，还包括在所述引线框结构和所述预模制夹具结构组件之间的导电粘合剂。
3.如权利要求2所述的半导体管芯封装件，其特征在于，所述导电粘合剂是第一导电粘合剂并且所述预模制夹具结构组件包括在所述夹具结构和半导体管芯之间的第二导电粘合剂。
4.如权利要求3所述的半导体管芯封装件，其特征在于，所述半导体管芯包括功率半导体管芯，所述功率半导体管芯包括功率MOSFET。
5.如权利要求1所述的半导体管芯封装件，其特征在于，所述预模制夹具结构组件包括第一表面和与所述第一表面相对的第二表面，其中所述第一表面包括第一模制材料表面和半导体管芯的表面。
6.一种用于制造半导体管芯封装件的方法，包括：
获得引线框结构；
将预模制夹具结构组件附连于所述引线框结构，所述预模制夹具结构组件包括夹具结构、附连于所述夹具结构的半导体管芯以及覆盖所述夹具结构和所述半导体管芯的至少一部分的第一模制材料；以及
施加第二模制材料以覆盖所述引线框结构的至少一部分和所述预模制夹具结构组件的至少一部分；其中所述第一模制材料与所述第二模制材料接触，在所述第一模制材料和所述第二模制材料之间存在界面。
7.如权利要求6所述的方法，其特征在于，还包括形成预模制夹具结构组件，其中形成预模制夹具结构组件包括：
获得夹具结构；
使用导电粘合剂将半导体管芯附连于夹具结构；以及
在所述夹具结构和所述半导体管芯的至少一部分周围模制第一模制材料。
8.如权利要求6所述的方法，其特征在于，所述半导体管芯包括功率MOSFET。
9.如权利要求6所述的方法，其特征在于，所述引线框结构包括铜。
10.如权利要求6所述的方法，其特征在于，将所述预模制夹具结构组件附连于所述引线框结构包括使用焊料将所述预模制夹具结构组件附连于所述引线框结构。
CN201080007032.4A 2009-02-05 2010-01-20 半导体管芯封装件及其制造方法 Expired - Fee Related CN102308383B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201410583922.XA CN104485321B (zh) 2009-02-05 2010-01-20 半导体管芯封装件及其制造方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/366,039 US8222718B2 (en) 2009-02-05 2009-02-05 Semiconductor die package and method for making the same
US12/366,039 2009-02-05
PCT/US2010/021462 WO2010090827A2 (en) 2009-02-05 2010-01-20 Semiconductor die package and method for making the same

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CN201410583922.XA Division CN104485321B (zh) 2009-02-05 2010-01-20 半导体管芯封装件及其制造方法

Publications (2)

Publication Number Publication Date
CN102308383A CN102308383A (zh) 2012-01-04
CN102308383B true CN102308383B (zh) 2014-12-03

Family

ID=42397003

Family Applications (2)

Application Number Title Priority Date Filing Date
CN201410583922.XA Expired - Fee Related CN104485321B (zh) 2009-02-05 2010-01-20 半导体管芯封装件及其制造方法
CN201080007032.4A Expired - Fee Related CN102308383B (zh) 2009-02-05 2010-01-20 半导体管芯封装件及其制造方法

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN201410583922.XA Expired - Fee Related CN104485321B (zh) 2009-02-05 2010-01-20 半导体管芯封装件及其制造方法

Country Status (5)

Country Link
US (2) US8222718B2 (zh)
KR (1) KR101561684B1 (zh)
CN (2) CN104485321B (zh)
TW (1) TWI495055B (zh)
WO (1) WO2010090827A2 (zh)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7768105B2 (en) * 2007-01-24 2010-08-03 Fairchild Semiconductor Corporation Pre-molded clip structure
US9275976B2 (en) * 2012-02-24 2016-03-01 Broadcom Corporation System-in-package with integrated socket
US20140167237A1 (en) * 2012-12-14 2014-06-19 Samsung Electro-Mechanics Co., Ltd. Power module package
US9536800B2 (en) 2013-12-07 2017-01-03 Fairchild Semiconductor Corporation Packaged semiconductor devices and methods of manufacturing
JP6287341B2 (ja) * 2014-03-03 2018-03-07 セイコーエプソン株式会社 液体吐出装置および液体吐出装置の制御方法
CN104900623B (zh) 2014-03-06 2018-11-30 恩智浦美国有限公司 露出管芯的功率半导体装置
JP6303623B2 (ja) 2014-03-07 2018-04-04 富士電機株式会社 半導体装置、半導体装置の製造方法、位置決め治具
JP6384080B2 (ja) 2014-03-25 2018-09-05 セイコーエプソン株式会社 液体吐出装置および液体吐出装置の制御方法
KR20160033870A (ko) * 2014-09-18 2016-03-29 제엠제코(주) 클립 구조체를 이용한 반도체 패키지
DE102014114933B4 (de) 2014-10-15 2021-08-12 Infineon Technologies Austria Ag Halbleiterbauelement
WO2017078377A2 (ko) * 2015-11-05 2017-05-11 한국기계연구원 오염된 산화촉매의 재생 수단을 포함하는 공정 배출가스 오염물질 제거장치
KR102050130B1 (ko) * 2016-11-30 2019-11-29 매그나칩 반도체 유한회사 반도체 패키지 및 그 제조 방법
WO2018211685A1 (ja) 2017-05-19 2018-11-22 新電元工業株式会社 電子モジュール
WO2018211680A1 (ja) * 2017-05-19 2018-11-22 新電元工業株式会社 電子モジュール
JP6511584B2 (ja) * 2017-05-19 2019-05-15 新電元工業株式会社 チップモジュールの製造方法
US10727151B2 (en) * 2017-05-25 2020-07-28 Infineon Technologies Ag Semiconductor chip package having a cooling surface and method of manufacturing a semiconductor package
US11088046B2 (en) 2018-06-25 2021-08-10 Semiconductor Components Industries, Llc Semiconductor device package with clip interconnect and dual side cooling
US11621203B2 (en) * 2018-09-20 2023-04-04 Semiconductor Components Industries, Llc SiC MOSFET semiconductor packages and related methods
JP7180385B2 (ja) * 2019-01-08 2022-11-30 株式会社デンソー 半導体装置
EP3761359A1 (en) * 2019-07-03 2021-01-06 Nexperia B.V. A lead frame assembly for a semiconductor device
TWI716075B (zh) * 2019-08-19 2021-01-11 尼克森微電子股份有限公司 功率模組
US11600498B2 (en) * 2019-12-31 2023-03-07 Texas Instruments Incorporated Semiconductor package with flip chip solder joint capsules
TWI727861B (zh) * 2020-07-23 2021-05-11 朋程科技股份有限公司 晶片封裝結構及其製造方法
CN112701094A (zh) * 2020-12-15 2021-04-23 杰群电子科技（东莞）有限公司 一种功率器件封装结构及电力电子设备
CN112701095B (zh) * 2020-12-15 2022-10-14 杰群电子科技（东莞）有限公司 一种功率芯片堆叠封装结构
US20240145355A1 (en) * 2022-11-02 2024-05-02 Stmicroelectronics S.R.L. Method of manufacturing semiconductor devices, corresponding component, semiconductor device and method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005277168A (ja) * 2004-03-25 2005-10-06 Nec Electronics Corp 半導体装置、その組立方法及び半導体装置用導電性接着剤

Family Cites Families (54)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60217649A (ja) 1984-04-12 1985-10-31 Nec Corp 集積回路装置
US5327325A (en) * 1993-02-08 1994-07-05 Fairchild Space And Defense Corporation Three-dimensional integrated circuit package
US5646446A (en) * 1995-12-22 1997-07-08 Fairchild Space And Defense Corporation Three-dimensional flexible assembly of integrated circuits
US6460245B1 (en) * 1996-03-07 2002-10-08 Tessera, Inc. Method of fabricating semiconductor chip assemblies
US6133634A (en) * 1998-08-05 2000-10-17 Fairchild Semiconductor Corporation High performance flip chip package
KR100335480B1 (ko) * 1999-08-24 2002-05-04 김덕중 칩 패드가 방열 통로로 사용되는 리드프레임 및 이를 포함하는반도체 패키지
KR100335481B1 (ko) * 1999-09-13 2002-05-04 김덕중 멀티 칩 패키지 구조의 전력소자
US6720642B1 (en) * 1999-12-16 2004-04-13 Fairchild Semiconductor Corporation Flip chip in leaded molded package and method of manufacture thereof
US6989588B2 (en) * 2000-04-13 2006-01-24 Fairchild Semiconductor Corporation Semiconductor device including molded wireless exposed drain packaging
US6556750B2 (en) * 2000-05-26 2003-04-29 Fairchild Semiconductor Corporation Bi-directional optical coupler
KR100370231B1 (ko) * 2000-06-13 2003-01-29 페어차일드코리아반도체 주식회사 리드프레임의 배면에 직접 부착되는 절연방열판을구비하는 전력 모듈 패키지
KR100403608B1 (ko) * 2000-11-10 2003-11-01 페어차일드코리아반도체 주식회사 스택구조의 인텔리젠트 파워 모듈 패키지 및 그 제조방법
KR100374629B1 (ko) * 2000-12-19 2003-03-04 페어차일드코리아반도체 주식회사 얇고 작은 크기의 전력용 반도체 패키지
US6469384B2 (en) * 2001-02-01 2002-10-22 Fairchild Semiconductor Corporation Unmolded package for a semiconductor device
US6930397B2 (en) * 2001-03-28 2005-08-16 International Rectifier Corporation Surface mounted package with die bottom spaced from support board
US6891257B2 (en) * 2001-03-30 2005-05-10 Fairchild Semiconductor Corporation Packaging system for die-up connection of a die-down oriented integrated circuit
US6645791B2 (en) * 2001-04-23 2003-11-11 Fairchild Semiconductor Semiconductor die package including carrier with mask
US6893901B2 (en) * 2001-05-14 2005-05-17 Fairchild Semiconductor Corporation Carrier with metal bumps for semiconductor die packages
US6646329B2 (en) * 2001-05-15 2003-11-11 Fairchild Semiconductor, Inc. Power chip scale package
US7061080B2 (en) * 2001-06-11 2006-06-13 Fairchild Korea Semiconductor Ltd. Power module package having improved heat dissipating capability
US6683375B2 (en) * 2001-06-15 2004-01-27 Fairchild Semiconductor Corporation Semiconductor die including conductive columns
US6774465B2 (en) * 2001-10-05 2004-08-10 Fairchild Korea Semiconductor, Ltd. Semiconductor power package module
US6891256B2 (en) * 2001-10-22 2005-05-10 Fairchild Semiconductor Corporation Thin, thermally enhanced flip chip in a leaded molded package
US6674157B2 (en) * 2001-11-02 2004-01-06 Fairchild Semiconductor Corporation Semiconductor package comprising vertical power transistor
US6566749B1 (en) * 2002-01-15 2003-05-20 Fairchild Semiconductor Corporation Semiconductor die package with improved thermal and electrical performance
US6867489B1 (en) * 2002-01-22 2005-03-15 Fairchild Semiconductor Corporation Semiconductor die package processable at the wafer level
US6830959B2 (en) * 2002-01-22 2004-12-14 Fairchild Semiconductor Corporation Semiconductor die package with semiconductor die having side electrical connection
DE10392377T5 (de) * 2002-03-12 2005-05-12 FAIRCHILD SEMICONDUCTOR CORP. (n.d.Ges.d. Staates Delaware) Auf Waferniveau beschichtete stiftartige Kontakthöcker aus Kupfer
US7122884B2 (en) * 2002-04-16 2006-10-17 Fairchild Semiconductor Corporation Robust leaded molded packages and methods for forming the same
US6836023B2 (en) * 2002-04-17 2004-12-28 Fairchild Semiconductor Corporation Structure of integrated trace of chip package
KR100460063B1 (ko) * 2002-05-03 2004-12-04 주식회사 하이닉스반도체 센터 패드 칩 적층 볼 그리드 어레이 패키지 및 그 제조방법
KR100843737B1 (ko) * 2002-05-10 2008-07-04 페어차일드코리아반도체 주식회사 솔더 조인트의 신뢰성이 개선된 반도체 패키지
US7061077B2 (en) * 2002-08-30 2006-06-13 Fairchild Semiconductor Corporation Substrate based unmolded package including lead frame structure and semiconductor die
US6777800B2 (en) * 2002-09-30 2004-08-17 Fairchild Semiconductor Corporation Semiconductor die package including drain clip
US6943434B2 (en) * 2002-10-03 2005-09-13 Fairchild Semiconductor Corporation Method for maintaining solder thickness in flipchip attach packaging processes
US6806580B2 (en) * 2002-12-26 2004-10-19 Fairchild Semiconductor Corporation Multichip module including substrate with an array of interconnect structures
KR100958422B1 (ko) * 2003-01-21 2010-05-18 페어차일드코리아반도체 주식회사 고전압 응용에 적합한 구조를 갖는 반도체 패키지
US7217594B2 (en) * 2003-02-11 2007-05-15 Fairchild Semiconductor Corporation Alternative flip chip in leaded molded package design and method for manufacture
US7271497B2 (en) * 2003-03-10 2007-09-18 Fairchild Semiconductor Corporation Dual metal stud bumping for flip chip applications
US6867481B2 (en) * 2003-04-11 2005-03-15 Fairchild Semiconductor Corporation Lead frame structure with aperture or groove for flip chip in a leaded molded package
US7315077B2 (en) * 2003-11-13 2008-01-01 Fairchild Korea Semiconductor, Ltd. Molded leadless package having a partially exposed lead frame pad
TWI242850B (en) * 2003-12-31 2005-11-01 Advanced Semiconductor Eng Chip package structure
US7196313B2 (en) * 2004-04-02 2007-03-27 Fairchild Semiconductor Corporation Surface mount multi-channel optocoupler
US7242076B2 (en) * 2004-05-18 2007-07-10 Fairchild Semiconductor Corporation Packaged integrated circuit with MLP leadframe and method of making same
US7501702B2 (en) * 2004-06-24 2009-03-10 Fairchild Semiconductor Corporation Integrated transistor module and method of fabricating same
US7256479B2 (en) * 2005-01-13 2007-08-14 Fairchild Semiconductor Corporation Method to manufacture a universal footprint for a package with exposed chip
US7230333B2 (en) * 2005-04-21 2007-06-12 International Rectifier Corporation Semiconductor package
CN101807533B (zh) * 2005-06-30 2016-03-09 费查尔德半导体有限公司 半导体管芯封装及其制作方法
US7285849B2 (en) * 2005-11-18 2007-10-23 Fairchild Semiconductor Corporation Semiconductor die package using leadframe and clip and method of manufacturing
US7371616B2 (en) * 2006-01-05 2008-05-13 Fairchild Semiconductor Corporation Clipless and wireless semiconductor die package and method for making the same
TWI315565B (en) * 2006-07-13 2009-10-01 Powertech Technology Inc Map type semiconductor package
US20090057869A1 (en) * 2007-08-31 2009-03-05 Alpha & Omega Semiconductor, Ltd. Co-packaged high-side and low-side nmosfets for efficient dc-dc power conversion
US7800208B2 (en) * 2007-10-26 2010-09-21 Infineon Technologies Ag Device with a plurality of semiconductor chips
US8049312B2 (en) * 2009-01-12 2011-11-01 Texas Instruments Incorporated Semiconductor device package and method of assembly thereof

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005277168A (ja) * 2004-03-25 2005-10-06 Nec Electronics Corp 半導体装置、その組立方法及び半導体装置用導電性接着剤

Also Published As

Publication number Publication date
US20120329214A1 (en) 2012-12-27
TW201036119A (en) 2010-10-01
KR101561684B1 (ko) 2015-10-20
WO2010090827A2 (en) 2010-08-12
CN104485321B (zh) 2017-12-26
US20100193921A1 (en) 2010-08-05
CN102308383A (zh) 2012-01-04
WO2010090827A3 (en) 2010-09-30
KR20110117211A (ko) 2011-10-26
TWI495055B (zh) 2015-08-01
US8497164B2 (en) 2013-07-30
CN104485321A (zh) 2015-04-01
US8222718B2 (en) 2012-07-17

Similar Documents

Publication Publication Date Title
CN102308383B (zh) 半导体管芯封装件及其制造方法
CN101796637B (zh) 热增强的薄半导体封装件
US8008759B2 (en) Pre-molded clip structure
CN100444371C (zh) 功率半导体封装
US7504733B2 (en) Semiconductor die package
US7495323B2 (en) Semiconductor package structure having multiple heat dissipation paths and method of manufacture
US6469384B2 (en) Unmolded package for a semiconductor device
US7663212B2 (en) Electronic component having exposed surfaces
US8314489B2 (en) Semiconductor module and method for production thereof
KR20170086828A (ko) 메탈범프를 이용한 클립 본딩 반도체 칩 패키지
KR20080070068A (ko) 리드프레임과 클립을 이용하는 반도체 다이 패키지 및 그제조방법
WO2007027790A2 (en) Reversible-multiple footprint package and method of manufacturing
US20150243641A1 (en) Integrated circuit package
JP2010034350A (ja) 半導体装置
US20170194296A1 (en) Semiconductor module
KR101644913B1 (ko) 초음파 용접을 이용한 반도체 패키지 및 제조 방법
JP2008294219A (ja) 半導体装置及びその製造方法
CN111354703A (zh) 一种封装电子元件及其制造方法
JP2009218279A (ja) 半導体装置およびその製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20141203

Termination date: 20220120