TWI727861B - 晶片封裝結構及其製造方法 - Google Patents

晶片封裝結構及其製造方法 Download PDF

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TWI727861B
TWI727861B TW109124927A TW109124927A TWI727861B TW I727861 B TWI727861 B TW I727861B TW 109124927 A TW109124927 A TW 109124927A TW 109124927 A TW109124927 A TW 109124927A TW I727861 B TWI727861 B TW I727861B
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Taiwan
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chips
substrate
heat dissipation
chip
thermally conductive
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TW109124927A
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TW202205570A (zh
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蔡欣昌
劉敬文
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朋程科技股份有限公司
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Priority to TW109124927A priority Critical patent/TWI727861B/zh
Priority to US17/019,333 priority patent/US11177188B1/en
Priority to JP2020190687A priority patent/JP7145190B2/ja
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Publication of TWI727861B publication Critical patent/TWI727861B/zh
Publication of TW202205570A publication Critical patent/TW202205570A/zh

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Abstract

一種晶片封裝結構，包括散熱基板、預封裝晶片組、內連導線以及第二密封體。預封裝晶片組位於散熱基板上。內連導線位於封裝結構內，電性連接散熱基板與預封裝晶片組。第二密封體包覆部份散熱基板、所述內連導線與預封裝晶片組。預封裝晶片組包括導熱基板、至少二晶片、圖案化線路以及第一密封體。至少二晶片位於導熱基板上並與導熱基板熱耦接。圖案化線路位於預封裝晶片組內。至少二晶片之間藉由圖案化線路電性連接。第一密封體包覆至少二晶片與部份或全部圖案化線路。另提供一種晶片封裝結構的製造方法。

Description

晶片封裝結構及其製造方法
本發明是有關於一種封裝結構及其製造方法，且特別是有關於一種晶片封裝結構及其製造方法。
一般而言，具有高發熱密度的晶片所衍生的散熱挑戰在於具有熱點(hot spot)存在，故擴散熱阻(spreading resistance)將強烈影響整體晶片的性能與使用壽命。具體而言，當熱點存在擴散熱阻高時會造成晶片效能降低與使用壽命縮短，因此，如何解決晶片所面臨的熱點問題降低擴散熱阻有效地改善散熱能力，提升晶片效能與增加使用壽命已成為挑戰。
本發明提供一種晶片封裝結構及其製造方法，其可以在提升晶片效能與增加使用壽命的同時降低整體晶片封裝結構的製造成本。
本發明的一種晶片封裝結構，包括散熱基板、預封裝晶片組、內連導線以及第二密封體。預封裝晶片組位於散熱基板上。第二密封體包覆部份散熱基板、內連導線與預封裝晶片組。預封裝晶片組包括導熱基板、至少二晶片、圖案化線路以及第一密封體。至少二晶片位於導熱基板上並與導熱基板熱耦接。圖案化線路位於預封裝晶片組內。至少二晶片之間藉由圖案化線路電性連接。第一密封體密封至少二晶片與部份或全部圖案化線路。
本發明的一種晶片封裝結構的製造方法，包括以下步驟。配置預封裝晶片組於散熱基板上。形成第二密封體以密封部份散熱基板與預封裝晶片組。預封裝晶片組的形成步驟包括以下步驟。提供導熱基板。配置至少二晶片於導熱基板上，其中至少二晶片與導熱基板熱耦接。形成圖案化線路於至少二晶片上，以使至少二晶片之間藉由圖案化線路電性連接。形成第一密封體以密封至少二晶片與部份或全部圖案化線路。形成內連導線，電性連接散熱基板與預封裝晶片組。形成第二密封體以包覆部份散熱基板，部份或全部內連導線與預封裝晶片組。
基於上述，本發明的晶片封裝結構透過將至少二晶片預先組合在一起形成的晶片組熱耦接至導熱基板上，再把導熱基板與晶片組藉由密封體封裝成預封裝晶片組，並將預封裝晶片組配置於散熱基板上，如此一來，可以解決單一晶片所面臨的熱集中問題，以降低擴散熱阻。並且有效地改善封裝結構散熱能力並進一步縮減晶片成本，因此可以在提升晶片效能與增加使用壽命的同時，降低整體晶片封裝結構的製造成本。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
以下將參考圖式來全面地描述本發明的例示性實施例，但本發明還可按照多種不同形式來實施，且不應解釋為限於本文所述的實施例。在圖式中，為了清楚起見，各區域、部位及層的大小與厚度可不按實際比例繪製。為了方便理解，下述說明中相同的元件將以相同之符號標示來說明。
除非另有明確說明，否則本文所述任何方法絕不意欲被解釋為要求按特定順序執行其步驟。
圖1是依照本發明的一實施例的一種晶片封裝結構的剖面示意圖。圖2A至圖2H是依照本發明的一實施例的晶片封裝結構在不同階段的製造過程中的立體示意圖。圖3A是依照本發明的一實施例的一種晶片封裝結構的至少二晶片電性連接方式的剖面示意圖。
請參照圖1，在本實施例中，晶片封裝結構100包括散熱基板110、預封裝晶片組120以及密封體130、內連導線140。進一步而言，本發明不限制散熱基板110的材料，散熱基板110可以由任何適宜的散熱材料所製成，例如銅、鋁或碳纖維。在一些實施例中，散熱基板110可以是金屬導線架、金屬絕緣基板、陶瓷絕緣基板。此外，預封裝晶片組120位於散熱基板110上，內連導線140位於晶片封裝結構100內，密封體130包覆部份散熱基板110、部分或全部內連導線140與預封裝晶片組120、內連導線140。於本實施例中，內連導線140例如為一銅夾片，於其他實施例中，內連導線140例如可為打線結構或其他金屬夾片，以電性連接預封裝晶片組120和散熱基板110。
在一些實施例中，密封體130可以是藉由模塑製程(molding process)所形成的模塑化合物(molding compound)或是藉由灌模製程(potting process)所形成的矽化合物凝膠(Silicone Gel)。在一實施例中，密封體130例如可以由環氧樹脂或其他適宜的樹脂等絕緣材料所形成的，但本發明不限於此。
在本實施例中，預封裝晶片組120的製造方法可以包括以下步驟。
請參照圖2A，首先，提供導熱基板1210。在一些實施例中，為了具有較佳的導熱效果，導熱基板1210的材料的熱導率可以是大於50W/m-k。舉例而言，導熱基板1210的材料例如是銅、鋁或碳纖維。然而，本發明不限制導熱基板1210的材料，導熱基板1210可以是由任何適宜的導熱材料所製成。在一些實施例中，導熱基板1210例如可以是金屬基板、金屬導線架、金屬絕緣基板、陶瓷絕緣基板。
請參照圖2B，於導熱基板1210上配置至少二晶片1220(圖2B示意地繪示出四個)，其中至少二晶片1220與導熱基板1210熱耦接。在此，熱耦接可以定義為至少二晶片1220將熱量傳遞至導熱基板1210。在一些實施例中，至少二晶片1220與導熱基板1210間還包含一黏接層(未繪示)，用以黏接至少二晶片1220與導熱基板1210。
在上述實施例中，至少二晶片1220為相同的晶片。進一步而言，由於單一晶片的尺寸越大所需的晶片成本越高，因此，在本實施例中，將複數個尺寸較小的相同晶片1220組合成一個晶片組，可以在維持與一個大尺寸晶片同等電氣特性的同時避免溫度過度集中及縮減晶片成本，進而可以降低整體晶片封裝結構的擴散熱阻及製造成本。
在一些實施例中，晶片1220可以是三端點晶片、二端點晶片或其組合，其中三端點晶片可以是包括閘極(gate)、源極(source)與汲極(drain)，而二端點晶片可以是包括P型端與N型端。舉例而言，晶片1220可以包括功率金氧半場效電晶體(Metal-Oxide Semiconductor Field Effect Transistor, MOSFET)、快速恢復二極體(Fast Recovery Diode, FRD)、絕緣閘極雙極電晶體(Insulated-Gate Bipolar Transistor, IGBT)或其組合，且預封裝晶片組120中的每一晶片1220可以是彼此相同或彼此不同的晶片。然而，本發明不限於此，晶片1220依實際設計上的需求可以是任何適宜的晶片種類。
應說明的是，儘管圖2B中繪示出四個三端點晶片的組合，然而，本發明不限制晶片1220的組合態樣，可視實際設計上的需求而定。舉例而言，在一些實施例中，至少二晶片1220可以皆是三端點晶片，在另一些實施例中，至少二晶片1220可以皆是二端點晶片，在又一些實施例中，至少二晶片1220可以由三端點晶片及二端點晶片所組成。
在一些實施例中，晶片1220可以為碳化矽(SiC)或氮化鎵(GaN)的寬能隙半導體，由於寬能隙半導體單晶片的尺寸越大良率會越低，進而會導致寬能隙單晶片相較於其他大尺寸晶片具有成本更昂貴的劣勢，因此，藉由前述晶片組的配置可以更有效地降低包括寬能隙晶片的晶片封裝結構的製造成本，但本發明不限於此。
在本實施例中，晶片1220是以三端點晶片為例，即，本實施例的晶片1220具有閘極1222、源極1224與汲極(未繪示)，如圖2B所示。進一步而言，至少二晶片1220的閘極1222與源極1224可以是位於晶片1220的正面1220a上，而汲極可以是位於相對於閘極1222與源極1224的背面上。換句話說，晶片1220可以是以閘極1222與源極1224所在的正面1220a朝上的方式配置於導熱基板1210上，即相較於晶片1220的閘極1222與源極1224，晶片1220的汲極較靠近導熱基板1210，但本發明不限於此，晶片1220的配置方式可以視實際需求進行調整。也就是說，晶片1220以正面黏晶的方式配置於導熱基板1210上，也可以覆晶的方式配置於導熱基板1210上。
請同時參照圖2C至圖2F及圖3A，於至少二晶片1220上形成圖案化線路1230，以使至少二晶片1220之間藉由圖案化線路1230電性連接。在本實施例中，如圖3A所示，至少二晶片1220之間可以是以並聯的方式藉由圖案化線路1230電性連接。然而，本發明不限於此，在其他實施例中，至少二晶片1220之間可以是以其他方式藉由圖案化線路電性連接，例如以串聯方式電性連接。
進一步而言，圖案化線路1230可以是藉由以下步驟所形成。首先，如圖2C所示，於晶片1220上形成導體層1232，以形成電極。進一步而言，可以是於晶片1220的閘極1222與源極1224的上形成電極，以用於後續閘極1222與源極1224的電性連接。接著，如圖2D所示，於導體層1232上形成介電層1234，以使電極之間電性隔離，其中介電層1234可以暴露出閘極1222與源極1224電極的頂部。
然後，如圖2E所示，於介電層1234上形成導體層1236，以使至少二晶片1220的閘極1222之間形成電性連接路徑(routing)同時增厚源極1224上方的電極結構。之後，如圖2F所示，於導體層1236上形成導體層1238，以後續用於閘極1222、源極1224和外露焊墊1250(請參考圖2H)間的電性連接。據此，導體層1232、介電層1234、導體層1236以及導體層1238可以構成圖案化線路1230。
導體層1232、導體層1236與導體層1238的材料例如是藉由電鍍方式所形成的銅層，介電層1234例如是藉由模塑製程所形成環氧樹脂(epoxy)層。然而，本發明不限於此，導體層1232、導體層1236、導體層1238與介電層1234可以藉由任何適宜的材料與方法所形成。
應說明的是，本發明的圖案化線路1230中導體層與介電層的連接方式與層數可以視實際設計上的需求進行調整，不限於本實施例中的連接方式與層數。
請參照圖2G，形成密封體1240以包覆至少二晶片1220與部份或全部圖案化線路1230。在一些實施例中，密封體1240可以是藉由模塑製程或灌模製程所形成的模塑化合物或矽化合物凝膠。在一實施例中，密封體1240例如可以由環氧樹脂或其他適宜的樹脂等絕緣材料所形成的，但本發明不限於此。
在本實施例中，密封體1240與密封體130可以是在不同步驟中形成，舉例而言，可以先進行第一次封裝，以用密封體1240來形成預封裝晶片組120，接著，進行第二次封裝，將預封裝晶片組120配置於散熱基板110上再形成密封體130，以密封預封裝晶片組120與散熱基板110。
在一些實施例中，密封體1240與密封體130的材料可以不同。在另一些實施例中，密封體1240與密封體130的材料可以實質上相同。應說明的是，由於密封體1240與密封體130是在不同步驟中形成，因此即便封體1240與密封體130的材料實質上相同，在其鄰接處還是會具有一介面，此外，前述密封體1240可以是第一密封體，而前述密封體130可以是第二密封體。
請參照圖2H，在本實施例中，還可以於密封體1240上形成外露焊墊1250，以使後續至少二晶片1220可以藉由外露焊墊1250透過內連導線140與散熱基板110電性連接，或是外露焊墊1250直接與散熱基板110電性連接；請再次參照圖1，當預封裝晶片組120以外露焊墊1250向上且導熱基板1210向下的方式配置於散熱基板110上時，預封裝晶片組120的外露焊墊1250透過內連導線140與散熱基板110電性連接，且預封裝晶片組120的導熱基板1210直接與散熱基板110電性連接；當預封裝晶片組120以導熱基板1210向上且外露焊墊1250向下的方式配置於散熱基板110上時，預封裝晶片組120的外露焊墊1250直接與散熱基板110電性連接，導熱基板1210則透過內連導線140與散熱基板110電性連接。外露焊墊1250例如是藉由電鍍方式所形成的銅層，但本發明不限於此。
在本實施例中，晶片封裝結構100包括散熱基板110、預封裝晶片組120、第二密封體130以及內連導線140。預封裝晶片組120位於散熱基板110上，內連導線140電性連接散熱基板110與預封裝晶片組120。預封裝晶片組120包括導熱基板1210、至少二晶片1220、圖案化線路1230以及密封體1240。至少二晶片1220位於導熱基板1210上並與導熱基板1210熱耦接。圖案化線路1230位於預封裝晶片組120內，其中至少二晶片1220之間藉由圖案化線路1230電性連接。密封體1240包覆至少二晶片1220與部份圖案化線路1230。
於上述實施例中，所述預封裝晶片組120與所述內連導線140間，以及所述預封裝晶片組120與所述散熱基板110間，還可分別包含一黏接層(未繪示)，以黏接所述預封裝晶片組120與所述散熱基板110和所述內連導線140。
因此，本實施例的晶片封裝結構100透過將至少二晶片1220預先組合在一起形成的晶片組熱耦接至導熱基板1210上，再把導熱基板1210與晶片組藉由密封體1240封裝成預封裝晶片組120，並將預封裝晶片組120配置於散熱基板110上，如此一來，可以解決晶片1220所面臨的熱集中問題，以降低擴散熱阻。並且有效地改善散熱能力並縮減晶片1220成本，因此可以在提升晶片1220效能與增加使用壽命的同時，降低整體晶片封裝結構100的製造成本。
具體而言，晶片1220所產生的熱可以透過預封裝晶片組120的導熱基板1210引導出來，再經由散熱基板110進行散熱使溫度不會過度集中於局部區域，因此可以解決晶片1220所面臨的熱集中問題，降低擴散熱阻並且有效地改善散熱能力，以提升晶片1220效能與增加使用壽命。此外，由於單一晶片的尺寸越大所需的晶片成本越高，因此將複數個尺寸較小的相同晶片1220組合成一個晶片組，可以在維持與一個大尺寸晶片同樣電氣特性的同時縮減晶片1220成本，以降低整體晶片封裝結構100的製造成本。
在一些實施例中，晶片封裝結構100的結構熱阻可以從1.208(℃/W)降至0.707(℃/W)，換句話說，晶片封裝結構100可以有效降低結構擴散熱阻進而降低結構整體熱阻約40%，但本發明不限於此。
在一些實施例中，晶片封裝結構100例如是功率晶片封裝結構，但本發明不限於此。
在此必須說明的是，以下實施例沿用上述實施例的元件標號與部分內容，其中採用相同或近似的標號來表示相同或近似的元件，並且省略了相同技術內容的說明，關於省略部分的說明可參考前述實施例，下述實施例不再重複贅述。
圖3B是依照本發明的另一實施例的一種晶片封裝結構的至少二晶片電性連接方式的剖面示意圖。請參照圖3B，圖3B的實施例類似於圖3A的實施例，差異在於圖3B的實施例中至少二晶片1220之間可以是以串聯的方式藉由圖案化線路1230電性連接，以提升預封裝晶片組120中電性連接方式的彈性。
綜上所述，本發明的晶片封裝結構的晶片所產生的熱可以透過預封裝晶片組的導熱基板引導出來，再經由散熱基板進行散熱使溫度不會過度集中於局部區域，因此可以有效地改善散熱能力，解決晶片所面臨的熱集中問題降低結構熱阻，以提升晶片效能與增加使用壽命。此外，由於單一晶片的尺寸越大所需的晶片成本越高，因此將複數個尺寸較小的相同晶片組合成一個晶片組，可以在維持與一個大尺寸晶片同等電氣特性的同時縮減晶片成本，以降低整體晶片封裝結構的製造成本。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
100:晶片封裝結構 110:散熱基板 120:預封裝晶片組 1210:導熱基板 1220:晶片 1220a:正面 1222:閘極 1224:源極 1230:圖案化線路 1232、1236、1238:導體層 1234:介電層 1250:外露焊墊 1240、130:密封體 140：內連導線
圖1是依照本發明的一實施例的一種晶片封裝結構的剖面示意圖。 圖2A至圖2H是依照本發明的一實施例的晶片封裝結構在不同階段的製造過程中的立體示意圖。 圖3A是依照本發明的一實施例的一種晶片封裝結構的至少二晶片電性連接方式的剖面示意圖。 圖3B是依照本發明的另一實施例的一種晶片封裝結構的至少二晶片電性連接方式的剖面示意圖。
100:晶片封裝結構
110:散熱基板
120:預封裝晶片組
130:密封體
140:內連導線

Claims (12)

  1. 一種晶片封裝結構，包括： 散熱基板； 預封裝晶片組，位於所述散熱基板上，其中所述預封裝晶片組包括： 導熱基板； 至少二晶片，位於所述導熱基板上並與所述導熱基板熱耦接； 圖案化線路，位於所述預封裝晶片組中，其中所述至少二晶片之間藉由所述圖案化線路電性連接；以及 第一密封體，包覆所述至少二晶片與部份或全部所述圖案化線路； 內連導線，位於所述晶片封裝結構內，電性連接所述散熱基板與所述預封裝晶片組；以及 第二密封體，包覆部份所述散熱基板、所述內連導線與所述預封裝晶片組。
  2. 如請求項1所述的晶片封裝結構，其中所述至少二晶片之間以串聯或並聯的方式藉由所述圖案化線路電性連接。
  3. 如請求項1所述的晶片封裝結構，其中所述至少二晶片包括功率金氧半場效電晶體、快速恢復二極體、絕緣閘極雙極電晶體、碳化矽寬能隙半導體電晶體、氮化鎵寬能隙半導體電晶體或其組合。
  4. 如請求項1所述的晶片封裝結構，其中所述散熱基板為金屬導線架、金屬絕緣基板或陶瓷絕緣基板，且所述導熱基板為金屬基板、金屬導線架、金屬絕緣基板或陶瓷絕緣基板。
  5. 如請求項1所述的晶片封裝結構，其中所述預封裝晶片組包括外露焊墊，位於所述第一密封體上，其中所述至少二晶片藉由所述外露焊墊透過所述內連導線與所述散熱基板電性連接，且所述預封裝晶片組的所述導熱基板直接與所述散熱基板電性連接。
  6. 如請求項1所述的晶片封裝結構，其中所述預封裝晶片組包括外露焊墊，位於所述第一密封體上，其中所述至少二晶片藉由所述外露焊墊直接與所述散熱基板電性連接，且所述預封裝晶片組的所述導熱基板透過所述內連導線與所述散熱基板電性連接。
  7. 如請求項1所述的晶片封裝結構，其中所述至少二晶片為相同的晶片。
  8. 如請求項1所述的晶片封裝結構，其中所述至少二晶片與所述導熱基板間還包含一黏接層，用以黏接所述至少二晶片與所述導熱基板。
  9. 如請求項1所述的晶片封裝結構，其中所述預封裝晶片組與所述內連導線間，以及所述預封裝晶片組與所述散熱基板間，分別包含一黏接層，以黏接所述預封裝晶片組與所述散熱基板和所述內連導線。
  10. 一種晶片封裝結構的製造方法，包括： 配置預封裝晶片組於散熱基板上，其中所述預封裝晶片組的形成步驟包括： 提供導熱基板； 配置至少二晶片於所述導熱基板上，其中所述至少二晶片與所述導熱基板熱耦接； 形成圖案化線路於所述至少二晶片上，以使所述至少二晶片之間藉由所述圖案化線路電性連接； 形成第一密封體以密封所述至少二晶片與部份或全部所述圖案化線路； 形成內連導線，電性連接所述散熱基板與所述預封裝晶片組；以及 形成第二密封體以包覆部份所述散熱基板，部份或全部內連導線與所述預封裝晶片組。
  11. 如請求項10所述的晶片封裝結構的製造方法，其中形成所述預封裝晶片組之後，再將所述預封裝晶片組配置於所述散熱基板上，且其中所述第一密封體與所述第二密封體是在不同步驟中所形成。
  12. 如請求項10所述的晶片封裝結構的製造方法，其中所述配置至少二晶片於所述導熱基板上的步驟包括以正面黏晶的方式配置於所述導熱基板上，或以覆晶的方式配置於所述導熱基板上。
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