JP5478789B2 - Ｓｏｉ基板の作製方法 - Google Patents

Ｓｏｉ基板の作製方法 Download PDF

Info

Publication number
JP5478789B2
JP5478789B2 JP2008160232A JP2008160232A JP5478789B2 JP 5478789 B2 JP5478789 B2 JP 5478789B2 JP 2008160232 A JP2008160232 A JP 2008160232A JP 2008160232 A JP2008160232 A JP 2008160232A JP 5478789 B2 JP5478789 B2 JP 5478789B2
Authority
JP
Japan
Prior art keywords
layer
semiconductor layer
substrate
semiconductor
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2008160232A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009033123A5 (enExample
JP2009033123A (ja
Inventor
明久 下村
秀和 宮入
由里香 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP2008160232A priority Critical patent/JP5478789B2/ja
Publication of JP2009033123A publication Critical patent/JP2009033123A/ja
Publication of JP2009033123A5 publication Critical patent/JP2009033123A5/ja
Application granted granted Critical
Publication of JP5478789B2 publication Critical patent/JP5478789B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0214—Manufacture or treatment of multiple TFTs using temporary substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)
JP2008160232A 2007-06-27 2008-06-19 Ｓｏｉ基板の作製方法 Expired - Fee Related JP5478789B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008160232A JP5478789B2 (ja) 2007-06-27 2008-06-19 Ｓｏｉ基板の作製方法

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP2007168960 2007-06-27
JP2007168960 2007-06-27
JP2007168666 2007-06-27
JP2007168666 2007-06-27
JP2008160232A JP5478789B2 (ja) 2007-06-27 2008-06-19 Ｓｏｉ基板の作製方法

Publications (3)

Publication Number Publication Date
JP2009033123A JP2009033123A (ja) 2009-02-12
JP2009033123A5 JP2009033123A5 (enExample) 2011-07-07
JP5478789B2 true JP5478789B2 (ja) 2014-04-23

Family

ID=40161086

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008160232A Expired - Fee Related JP5478789B2 (ja) 2007-06-27 2008-06-19 Ｓｏｉ基板の作製方法

Country Status (3)

Country Link
US (1) US7795111B2 (enExample)
JP (1) JP5478789B2 (enExample)
KR (1) KR101478812B1 (enExample)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5315596B2 (ja) * 2006-07-24 2013-10-16 株式会社Ｓｕｍｃｏ 貼合せｓｏｉウェーハの製造方法
WO2008132904A1 (en) * 2007-04-13 2008-11-06 Semiconductor Energy Laboratory Co., Ltd. Photovoltaic device and method for manufacturing the same
WO2009001836A1 (en) * 2007-06-28 2008-12-31 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of semiconductor device
US8431451B2 (en) 2007-06-29 2013-04-30 Semicondutor Energy Laboratory Co., Ltd. Display device and method for manufacturing the same
JP5507063B2 (ja) 2007-07-09 2014-05-28 株式会社半導体エネルギー研究所 半導体装置の作製方法
US8236668B2 (en) * 2007-10-10 2012-08-07 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
JP2009135453A (ja) * 2007-10-30 2009-06-18 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法、半導体装置及び電子機器
JP5688203B2 (ja) * 2007-11-01 2015-03-25 株式会社半導体エネルギー研究所 半導体基板の作製方法
US7943414B2 (en) * 2008-08-01 2011-05-17 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
SG161151A1 (en) * 2008-10-22 2010-05-27 Semiconductor Energy Lab Soi substrate and method for manufacturing the same
SG182208A1 (en) * 2008-12-15 2012-07-30 Semiconductor Energy Lab Manufacturing method of soi substrate and manufacturing method of semiconductor device
JP2010239123A (ja) * 2009-03-12 2010-10-21 Semiconductor Energy Lab Co Ltd 半導体装置及びその作製方法
TWI398961B (zh) * 2010-01-04 2013-06-11 Tainergy Tech Co Ltd 包含至少二次去除有害雜質步驟之太陽能電池的製造方法
FR2963982B1 (fr) 2010-08-20 2012-09-28 Soitec Silicon On Insulator Procede de collage a basse temperature
US8946820B2 (en) * 2011-06-30 2015-02-03 Sharp Kabushiki Kaisha Method for manufacturing semiconductor substrate, substrate for forming semiconductor substrate, stacked substrate, semiconductor substrate, and electronic device
JP5926527B2 (ja) * 2011-10-17 2016-05-25 信越化学工業株式会社 透明ｓｏｉウェーハの製造方法
JP2013093489A (ja) * 2011-10-27 2013-05-16 Mitsubishi Electric Corp 半導体装置の製造方法
US9281233B2 (en) * 2012-12-28 2016-03-08 Sunedison Semiconductor Limited Method for low temperature layer transfer in the preparation of multilayer semiconductor devices
JP6442818B2 (ja) * 2013-09-04 2018-12-26 株式会社Sumco シリコンウェーハおよびその製造方法
WO2017116905A1 (en) * 2015-12-30 2017-07-06 Mattson Technology, Inc. Gas flow control for millisecond anneal system
US9966301B2 (en) * 2016-06-27 2018-05-08 New Fab, LLC Reduced substrate effects in monolithically integrated RF circuits
US10593818B2 (en) * 2016-12-09 2020-03-17 The Boeing Company Multijunction solar cell having patterned emitter and method of making the solar cell
JP6855124B2 (ja) * 2017-05-08 2021-04-07 株式会社ディスコ ゲッタリング層形成方法
JP7581098B2 (ja) 2021-03-19 2024-11-12 キオクシア株式会社 半導体装置の製造方法

Family Cites Families (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02267950A (ja) 1989-04-07 1990-11-01 Sony Corp 半導体基板
JP2564935B2 (ja) 1989-04-20 1996-12-18 三菱電機株式会社 半導体装置
JP3293736B2 (ja) * 1996-02-28 2002-06-17 キヤノン株式会社 半導体基板の作製方法および貼り合わせ基体
JP4103968B2 (ja) * 1996-09-18 2008-06-18 株式会社半導体エネルギー研究所 絶縁ゲイト型半導体装置
US5753560A (en) * 1996-10-31 1998-05-19 Motorola, Inc. Method for fabricating a semiconductor device using lateral gettering
US6027988A (en) * 1997-05-28 2000-02-22 The Regents Of The University Of California Method of separating films from bulk substrates by plasma immersion ion implantation
US6548382B1 (en) * 1997-07-18 2003-04-15 Silicon Genesis Corporation Gettering technique for wafers made using a controlled cleaving process
US6388652B1 (en) * 1997-08-20 2002-05-14 Semiconductor Energy Laboratory Co., Ltd. Electrooptical device
US6686623B2 (en) * 1997-11-18 2004-02-03 Semiconductor Energy Laboratory Co., Ltd. Nonvolatile memory and electronic apparatus
JPH11163363A (ja) 1997-11-22 1999-06-18 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
JP3358550B2 (ja) * 1998-07-07 2002-12-24 信越半導体株式会社 Ｓｏｉウエーハの製造方法ならびにこの方法で製造されるｓｏｉウエーハ
US6271101B1 (en) * 1998-07-29 2001-08-07 Semiconductor Energy Laboratory Co., Ltd. Process for production of SOI substrate and process for production of semiconductor device
JP2000077287A (ja) * 1998-08-26 2000-03-14 Nissin Electric Co Ltd 結晶薄膜基板の製造方法
JP4476390B2 (ja) * 1998-09-04 2010-06-09 株式会社半導体エネルギー研究所 半導体装置の作製方法
US6380007B1 (en) * 1998-12-28 2002-04-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method of the same
JP4066574B2 (ja) * 1999-03-04 2008-03-26 富士電機デバイステクノロジー株式会社 半導体装置の製造方法
JP2000349266A (ja) * 1999-03-26 2000-12-15 Canon Inc 半導体部材の製造方法、半導体基体の利用方法、半導体部材の製造システム、半導体部材の生産管理方法及び堆積膜形成装置の利用方法
JP4379943B2 (ja) * 1999-04-07 2009-12-09 株式会社デンソー 半導体基板の製造方法および半導体基板製造装置
US7232742B1 (en) * 1999-11-26 2007-06-19 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device that includes forming a material with a high tensile stress in contact with a semiconductor film to getter impurities from the semiconductor film
JP2002033399A (ja) * 2000-07-13 2002-01-31 Toshiba Corp 半導体集積回路及びその製造方法
US7045444B2 (en) * 2000-12-19 2006-05-16 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing semiconductor device that includes selectively adding a noble gas element
JP4316132B2 (ja) * 2000-12-19 2009-08-19 株式会社半導体エネルギー研究所 半導体装置の作製方法
TWI221645B (en) * 2001-01-19 2004-10-01 Semiconductor Energy Lab Method of manufacturing a semiconductor device
US7115453B2 (en) * 2001-01-29 2006-10-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method of the same
US7141822B2 (en) * 2001-02-09 2006-11-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
JP5088993B2 (ja) * 2001-02-16 2012-12-05 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP4993810B2 (ja) * 2001-02-16 2012-08-08 株式会社半導体エネルギー研究所 半導体装置の作製方法
US7052943B2 (en) * 2001-03-16 2006-05-30 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device
JP2002343799A (ja) 2001-05-17 2002-11-29 Nec Corp Ｓｏｉ基板及び半導体装置の製造方法
US6743700B2 (en) * 2001-06-01 2004-06-01 Semiconductor Energy Laboratory Co., Ltd. Semiconductor film, semiconductor device and method of their production
TW541584B (en) * 2001-06-01 2003-07-11 Semiconductor Energy Lab Semiconductor film, semiconductor device and method for manufacturing same
US6566158B2 (en) * 2001-08-17 2003-05-20 Rosemount Aerospace Inc. Method of preparing a semiconductor using ion implantation in a SiC layer
US7119365B2 (en) * 2002-03-26 2006-10-10 Sharp Kabushiki Kaisha Semiconductor device and manufacturing method thereof, SOI substrate and display device using the same, and manufacturing method of the SOI substrate
JP4772258B2 (ja) 2002-08-23 2011-09-14 シャープ株式会社 Ｓｏｉ基板の製造方法
JP4693411B2 (ja) * 2002-10-30 2011-06-01 株式会社半導体エネルギー研究所 半導体装置の作製方法
WO2005024917A1 (ja) * 2003-09-08 2005-03-17 Sumco Corporation 貼り合わせウェーハの製造方法
JP5110772B2 (ja) 2004-02-03 2012-12-26 株式会社半導体エネルギー研究所 半導体薄膜層を有する基板の製造方法
JP2005311199A (ja) * 2004-04-23 2005-11-04 Canon Inc 基板の製造方法
WO2006032948A1 (en) * 2004-09-21 2006-03-30 S.O.I.Tec Silicon On Insulator Technologies Method for obtaining a thin layer by implementing co-implantation and subsequent implantation
US7148124B1 (en) * 2004-11-18 2006-12-12 Alexander Yuri Usenko Method for forming a fragile layer inside of a single crystalline substrate preferably for making silicon-on-insulator wafers
US20070281440A1 (en) * 2006-05-31 2007-12-06 Jeffrey Scott Cites Producing SOI structure using ion shower
US8153513B2 (en) * 2006-07-25 2012-04-10 Silicon Genesis Corporation Method and system for continuous large-area scanning implantation process
CN101281912B (zh) * 2007-04-03 2013-01-23 株式会社半导体能源研究所 Soi衬底及其制造方法以及半导体装置
CN101681843B (zh) * 2007-06-20 2012-05-09 株式会社半导体能源研究所 半导体装置的制造方法
JP5325404B2 (ja) * 2007-09-21 2013-10-23 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法

Also Published As

Publication number Publication date
KR20080114525A (ko) 2008-12-31
US7795111B2 (en) 2010-09-14
US20090004821A1 (en) 2009-01-01
JP2009033123A (ja) 2009-02-12
KR101478812B1 (ko) 2015-01-02

Similar Documents

Publication Publication Date Title
JP5478789B2 (ja) Ｓｏｉ基板の作製方法
JP5383098B2 (ja) 半導体装置の作製方法
CN101393920B (zh) 半导体装置以及其制造方法
US8247307B2 (en) Manufacturing method of substrate provided with semiconductor films
JP5849077B2 (ja) Ｓｏｉ基板の作製方法
KR101561855B1 (ko) Ｓｏｉ기판의 제작방법
JP5542256B2 (ja) Ｓｏｉ基板の作製方法
KR101574138B1 (ko) Ｓｏｉ 기판의 제조방법
US8822305B2 (en) Substrate provided with semiconductor films and manufacturing method thereof
JP5500833B2 (ja) Ｓｏｉ基板の作製方法
JP2011077504A (ja) 半導体装置の作製方法
JP2010109353A (ja) Ｓｏｉ基板の作製方法
JP2010114431A (ja) Ｓｏｉ基板の作製方法
JP2010177662A (ja) Ｓｏｉ基板の作製方法及び半導体装置の作製方法
JP5580010B2 (ja) 半導体装置の作製方法
JP2010147313A (ja) Ｓｏｉ基板の作製方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110519

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20110519

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130529

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20130530

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20140204

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20140211

R150 Certificate of patent or registration of utility model

Ref document number: 5478789

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees