JP2010109353A - Soi基板の作製方法 - Google Patents
Soi基板の作製方法 Download PDFInfo
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- JP2010109353A JP2010109353A JP2009228249A JP2009228249A JP2010109353A JP 2010109353 A JP2010109353 A JP 2010109353A JP 2009228249 A JP2009228249 A JP 2009228249A JP 2009228249 A JP2009228249 A JP 2009228249A JP 2010109353 A JP2010109353 A JP 2010109353A
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- 239000002210 silicon-based material Substances 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 1
- 229960000909 sulfur hexafluoride Drugs 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- QQQSFSZALRVCSZ-UHFFFAOYSA-N triethoxysilane Chemical compound CCO[SiH](OCC)OCC QQQSFSZALRVCSZ-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
Abstract
【解決手段】SOI基板の作製において、ボンド基板中に脆化層を形成する際の水素イオンドーズ量を、ボンド基板の分離下限となる水素イオンドーズ量より増加して脆化層を形成し、ベース基板に貼り合わせたボンド基板を分離して、ベース基板上に単結晶半導体膜が形成されたSOI基板を形成し、該単結晶半導体膜の表面にレーザ光を照射して作製する。
【選択図】図8
Description
本実施の形態に係るSOI基板の作製方法では、ボンド基板である半導体基板から分離させた半導体膜をベース基板に貼り合わせてSOI基板を作製する。以下、図1〜図3を参照して、本形態に係るSOI基板の作製方法の一つについて説明する。
O2+hν(λ1nm)→O(3P)+O(3P) (1)
O(3P)+O2→O3 (2)
O3+hν(λ2nm)→O(1D)+O2 (3)
O2+hν(λ3nm)→O(1D)+O(3P) (4)
O(3P)+O2→O3 (5)
O3+hν(λ3nm)→O(1D)+O2 (6)
本実施の形態では、実施の形態1で作製したSOI基板を用いて半導体装置を作製する。図4乃至図6の図面を参照して、nチャネル型薄膜トランジスタ、およびpチャネル型薄膜トランジスタを作製する方法を説明する。複数の薄膜トランジスタ(TFT)を組み合わせることで、各種の半導体装置を形成することができる。
本実施の形態では、実施の形態2とは異なり、サイドウォールを形成することによって、半導体膜中に高濃度不純物領域、低濃度不純物及びチャネル形成領域を形成する半導体装置の製造方法について図7を参照して説明する。
本実施の形態では、本発明の一態様を適用して作製した半導体装置の具体的な態様について、図9及び図10を参照しながら、説明する。
本実施の形態では上記実施の形態で示した半導体装置を適用して作製した表示装置について、図11及び図12を参照しながら、説明する。
本実施の形態では、上記実施の形態で示した半導体装置を適用して作製した電子機器について、図13及び図14を参照しながら、説明する。
102 絶縁膜
104 脆化層
106 絶縁膜
107 レーザ光
108 ベース基板
109 微小ボイド
110 分離後のボンド基板
111a 分離面
111b 分離面
112 半導体膜
114 レーザ光
116 半導体膜
118 半導体膜
120 ゲート絶縁膜
122 第1の導電膜
124 第2の導電膜
125 積層導電膜
126 レジストマスク
128 レジストマスク
130 第1の導電膜
132 第1の導電膜
134 第2の導電膜
136 第2の導電膜
138 第2の導電膜
140 第2の導電膜
142 ゲート電極
144 ゲート電極
146 レジストマスク
148 p型不純物元素
150 高濃度不純物領域
152 低濃度不純物領域
154 チャネル形成領域
156 レジストマスク
158 n型不純物元素
160 高濃度不純物領域
162 低濃度不純物領域
164 チャネル形成領域
166 絶縁膜
168 第1の層間絶縁膜
170 第2の層間絶縁膜
172 配線
174 配線
200 第1の導電膜
202 第1の導電膜
204 第2の導電膜
206 第2の導電膜
208 ゲート電極
210 ゲート電極
212 低濃度不純物領域
214 チャネル形成領域
216 低濃度不純物領域
218 チャネル形成領域
220 サイドウォール
222 サイドウォール
224 高濃度不純物領域
226 低濃度不純物領域
228 チャネル形成領域
230 高濃度不純物領域
232 低濃度不純物領域
234 チャネル形成領域
302 単結晶半導体膜
320 単結晶半導体膜
322 走査線
323 信号線
324 画素電極
325 TFT
327 層間絶縁膜
328 電極
329 柱状スペーサ
330 配向膜
332 対向基板
333 対向電極
334 配向膜
335 液晶層
340 チャネル形成領域
341 高濃度不純物領域
401 選択用トランジスタ
402 表示制御用トランジスタ
403 半導体膜
404 半導体膜
405 走査線
406 信号線
407 電流供給線
408 画素電極
410 電極
411 電極
412 ゲート電極
413 電極
427 層間絶縁膜
428 隔壁層
429 EL層
430 対向電極
431 対向基板
432 樹脂層
451 チャネル形成領域
452 高濃度不純物領域
500 マイクロプロセッサ
501 演算回路
502 演算回路制御部
503 命令解析部
504 制御部
505 タイミング制御部
506 レジスタ
507 レジスタ制御部
508 バスインターフェース
509 専用メモリ
510 メモリインターフェース
511 RFCPU
512 アナログ回路部
513 デジタル回路部
514 共振回路
515 整流回路
516 定電圧回路
517 リセット回路
518 発振回路
519 復調回路
520 変調回路
521 RFインターフェース
522 制御レジスタ
523 クロックコントローラ
524 インターフェース
525 中央処理ユニット
526 ランダムアクセスメモリ
527 専用メモリ
528 アンテナ
529 容量部
530 電源管理回路
700 携帯電話
701 筐体
702 筐体
703 表示部
704 スピーカー
705 マイクロフォン
706 操作キー
707 ポインティングデバイス
708 表面カメラ用レンズ
709 外部接続端子ジャック
710 イヤホン端子
711 キーボード
712 外部メモリスロット
713 裏面カメラ
714 ライト
801 筐体
802 支持台
803 表示部
804 スピーカー部
805 ビデオ入力端子
812 筐体
813 表示部
814 キーボード
815 外部接続ポート
816 マウス
822 表示部
824 外部接続ポート
825 リモコン受信部
826 受像部
829 操作キー
1000 周辺部
1002 単結晶シリコン層
1004 熱酸化膜
1006 単結晶シリコン層
1008 熱酸化膜
1008 領域
1012 第1の領域
1014 第2の領域
1016 第3の領域
1018 第4の領域
1020 第5の領域
1022 第6の領域
Claims (15)
- ボンド基板上に絶縁膜を形成し、
前記絶縁膜を介して前記ボンド基板に水素イオンの照射を行うことにより、前記ボンド基板中に脆化層を形成し、
前記ボンド基板を、前記絶縁膜を介してベース基板と貼り合わせ、
熱処理によって前記ボンド基板を前記脆化層において分離し、
前記ベース基板上に前記絶縁膜を介して半導体膜を形成し、
前記半導体膜にレーザ光を照射し、
前記水素イオンの照射における水素イオンドーズ量は、前記熱処理により前記ボンド基板が分離する最小量となる水素イオンドーズ量の2.2倍以上とすることを特徴とするSOI基板の作製方法。 - 請求項1において、
前記水素イオンの照射における水素イオンドーズ量は、前記熱処理により前記ボンド基板が分離する最小量となる水素イオンドーズ量の2.2倍以上3.0倍以下とすることを特徴とするSOI基板の作製方法。 - ボンド基板上に絶縁膜を形成し、
前記絶縁膜を介して前記ボンド基板に水素イオンの照射を行うことにより、前記ボンド基板中に脆化層を形成し、
前記ボンド基板を、前記絶縁膜を介してベース基板と貼り合わせ、
前記ボンド基板を前記脆化層において分離し、
前記ベース基板上に前記絶縁膜を介して半導体膜を形成し、
前記半導体膜にレーザ光を照射し、
前記水素イオンの照射における水素イオンドーズ量は、2.2×1016ions/cm2以上とすることを特徴とするSOI基板の作製方法。 - 請求項3において、
前記水素イオンの照射における水素イオンドーズ量は、2.2×1016ions/cm2以上3.0×1016ions/cm2以下とすることを特徴とするSOI基板の作製方法。 - 請求項1乃至請求項4のいずれか一項において、
前記レーザ光を照射する前に、前記半導体膜の表面に形成されている自然酸化膜を除去することを特徴とするSOI基板の作製方法。 - 請求項5において、
前記自然酸化膜を、ドライエッチングを用いて除去することを特徴とするSOI基板の作製方法。 - 請求項1乃至請求項6のいずれか一項において、
前記レーザ光の照射によって、前記半導体膜を部分溶融させることを特徴とするSOI基板の作製方法。 - 請求項1乃至請求項7のいずれか一項において、
前記絶縁膜は、酸化シリコン膜、窒化シリコン膜、酸化窒化シリコン膜若しくは窒化酸化シリコン膜から選ばれた単数の膜又は複数の膜の積層であることを特徴とするSOI基板の作製方法。 - 請求項1乃至請求項7のいずれか一項において、
前記絶縁膜は、前記酸化シリコン膜であり、有機シランガスを用いた化学気相成長法により形成されたものであることを特徴とするSOI基板の作製方法。 - 請求項1乃至請求項7のいずれか一項において、
前記絶縁膜は、前記酸化シリコン膜であり、前記ボンド基板を熱酸化して形成されたものであることを特徴とするSOI基板の作製方法。 - 請求項1乃至請求項10のいずれか一項において、
前記ベース基板上に接して第2の絶縁膜を形成することを特徴とするSOI基板の作製方法。 - 請求項11において、
前記第2の絶縁膜は、窒化シリコン膜又は窒化酸化シリコン膜であることを特徴とするSOI基板の作製方法。 - 請求項1乃至請求項12のいずれか一項において、
前記ボンド基板は、単結晶シリコン基板であることを特徴とするSOI基板の作製方法。 - 請求項1乃至請求項13のいずれか一項において、
前記ベース基板は、アルミノシリケートガラス、バリウムホウケイ酸ガラス、又はアルミノホウケイ酸ガラスであることを特徴とするSOI基板の作製方法。 - 請求項1乃至請求項14のいずれか一項において、
イオンドーピング装置を用いて前記水素イオンの照射を行うことを特徴とするSOI基板の作製方法。
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