KR101478812B1 - Ｓｏｉ 기판의 제조방법 및 반도체장치의 제조방법 - Google Patents

Ｓｏｉ 기판의 제조방법 및 반도체장치의 제조방법 Download PDF

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Publication number
KR101478812B1
KR101478812B1 KR20080057830A KR20080057830A KR101478812B1 KR 101478812 B1 KR101478812 B1 KR 101478812B1 KR 20080057830 A KR20080057830 A KR 20080057830A KR 20080057830 A KR20080057830 A KR 20080057830A KR 101478812 B1 KR101478812 B1 KR 101478812B1
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semiconductor
layer
substrate
semiconductor layer
gettering site
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Korean (ko)
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KR20080114525A (ko
Inventor
아키히사 시모무라
히데카즈 미야이리
유리카 사토
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가부시키가이샤 한도오따이 에네루기 켄큐쇼
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0214—Manufacture or treatment of multiple TFTs using temporary substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)
KR20080057830A 2007-06-27 2008-06-19 Ｓｏｉ 기판의 제조방법 및 반도체장치의 제조방법 Expired - Fee Related KR101478812B1 (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JPJP-P-2007-00168666 2007-06-27
JP2007168666 2007-06-27
JP2007168960 2007-06-27
JPJP-P-2007-00168960 2007-06-27

Publications (2)

Publication Number Publication Date
KR20080114525A KR20080114525A (ko) 2008-12-31
KR101478812B1 true KR101478812B1 (ko) 2015-01-02

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US (1) US7795111B2 (enExample)
JP (1) JP5478789B2 (enExample)
KR (1) KR101478812B1 (enExample)

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JP5315596B2 (ja) * 2006-07-24 2013-10-16 株式会社Ｓｕｍｃｏ 貼合せｓｏｉウェーハの製造方法
WO2008132904A1 (en) * 2007-04-13 2008-11-06 Semiconductor Energy Laboratory Co., Ltd. Photovoltaic device and method for manufacturing the same
CN101743616B (zh) * 2007-06-28 2012-02-22 株式会社半导体能源研究所 半导体装置的制造方法
US8431451B2 (en) 2007-06-29 2013-04-30 Semicondutor Energy Laboratory Co., Ltd. Display device and method for manufacturing the same
JP5507063B2 (ja) 2007-07-09 2014-05-28 株式会社半導体エネルギー研究所 半導体装置の作製方法
US8236668B2 (en) * 2007-10-10 2012-08-07 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
JP2009135453A (ja) * 2007-10-30 2009-06-18 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法、半導体装置及び電子機器
JP5688203B2 (ja) * 2007-11-01 2015-03-25 株式会社半導体エネルギー研究所 半導体基板の作製方法
JP5552276B2 (ja) * 2008-08-01 2014-07-16 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
SG161151A1 (en) * 2008-10-22 2010-05-27 Semiconductor Energy Lab Soi substrate and method for manufacturing the same
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JP2010239123A (ja) * 2009-03-12 2010-10-21 Semiconductor Energy Lab Co Ltd 半導体装置及びその作製方法
TWI398961B (zh) * 2010-01-04 2013-06-11 Tainergy Tech Co Ltd 包含至少二次去除有害雜質步驟之太陽能電池的製造方法
FR2963982B1 (fr) 2010-08-20 2012-09-28 Soitec Silicon On Insulator Procede de collage a basse temperature
WO2013002227A1 (ja) * 2011-06-30 2013-01-03 シャープ株式会社 半導体基板の製造方法、半導体基板作成用基板、積層基板、半導体基板、及び電子デバイス
JP5926527B2 (ja) * 2011-10-17 2016-05-25 信越化学工業株式会社 透明ｓｏｉウェーハの製造方法
JP2013093489A (ja) * 2011-10-27 2013-05-16 Mitsubishi Electric Corp 半導体装置の製造方法
US9281233B2 (en) * 2012-12-28 2016-03-08 Sunedison Semiconductor Limited Method for low temperature layer transfer in the preparation of multilayer semiconductor devices
JP6442818B2 (ja) * 2013-09-04 2018-12-26 株式会社Sumco シリコンウェーハおよびその製造方法
CN108028214B (zh) * 2015-12-30 2022-04-08 玛特森技术公司 用于毫秒退火系统的气体流动控制
US9966301B2 (en) * 2016-06-27 2018-05-08 New Fab, LLC Reduced substrate effects in monolithically integrated RF circuits
US10593818B2 (en) * 2016-12-09 2020-03-17 The Boeing Company Multijunction solar cell having patterned emitter and method of making the solar cell
JP6855124B2 (ja) * 2017-05-08 2021-04-07 株式会社ディスコ ゲッタリング層形成方法
JP7581098B2 (ja) 2021-03-19 2024-11-12 キオクシア株式会社 半導体装置の製造方法

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KR20080114525A (ko) 2008-12-31
US20090004821A1 (en) 2009-01-01
US7795111B2 (en) 2010-09-14
JP5478789B2 (ja) 2014-04-23
JP2009033123A (ja) 2009-02-12

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