KR20000011406A - Soi웨이퍼의제조방법및이방법으로제조된soi웨이퍼 - Google Patents
Soi웨이퍼의제조방법및이방법으로제조된soi웨이퍼 Download PDFInfo
- Publication number
- KR20000011406A KR20000011406A KR1019990026311A KR19990026311A KR20000011406A KR 20000011406 A KR20000011406 A KR 20000011406A KR 1019990026311 A KR1019990026311 A KR 1019990026311A KR 19990026311 A KR19990026311 A KR 19990026311A KR 20000011406 A KR20000011406 A KR 20000011406A
- Authority
- KR
- South Korea
- Prior art keywords
- wafer
- soi
- layer
- soi wafer
- thickness
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 100
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 235000012431 wafers Nutrition 0.000 claims abstract description 171
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 33
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 33
- 239000010703 silicon Substances 0.000 claims abstract description 33
- 238000010438 heat treatment Methods 0.000 claims abstract description 26
- 239000007789 gas Substances 0.000 claims abstract description 10
- 239000010408 film Substances 0.000 claims description 47
- 239000001257 hydrogen Substances 0.000 claims description 19
- 229910052739 hydrogen Inorganic materials 0.000 claims description 19
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 12
- 150000002500 ions Chemical class 0.000 claims description 12
- 239000006227 byproduct Substances 0.000 claims description 11
- 238000005468 ion implantation Methods 0.000 claims description 11
- -1 hydrogen ions Chemical class 0.000 claims description 8
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims description 3
- 229910000041 hydrogen chloride Inorganic materials 0.000 claims description 3
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 claims description 3
- 238000012958 reprocessing Methods 0.000 claims description 3
- 239000010409 thin film Substances 0.000 claims description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 2
- 230000008569 process Effects 0.000 abstract description 33
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 abstract description 16
- 238000003475 lamination Methods 0.000 abstract description 2
- 230000003647 oxidation Effects 0.000 abstract 1
- 238000007254 oxidation reaction Methods 0.000 abstract 1
- 230000007547 defect Effects 0.000 description 13
- 238000005530 etching Methods 0.000 description 12
- 230000003746 surface roughness Effects 0.000 description 11
- 238000005498 polishing Methods 0.000 description 8
- 230000001133 acceleration Effects 0.000 description 7
- 239000013078 crystal Substances 0.000 description 7
- 238000004299 exfoliation Methods 0.000 description 5
- 238000002347 injection Methods 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- 230000032798 delamination Effects 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 4
- 238000005247 gettering Methods 0.000 description 4
- 229910001385 heavy metal Inorganic materials 0.000 description 4
- 238000004064 recycling Methods 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 239000007864 aqueous solution Substances 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- SLLGVCUQYRMELA-UHFFFAOYSA-N chlorosilicon Chemical compound Cl[Si] SLLGVCUQYRMELA-UHFFFAOYSA-N 0.000 description 2
- 238000011109 contamination Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 239000012808 vapor phase Substances 0.000 description 2
- 229910003902 SiCl 4 Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000003776 cleavage reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000002440 industrial waste Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 230000007017 scission Effects 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 230000003595 spectral effect Effects 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S156/00—Adhesive bonding and miscellaneous chemical manufacture
- Y10S156/934—Apparatus having delaminating means adapted for delaminating a specified article
- Y10S156/941—Means for delaminating semiconductive product
- Y10S156/942—Means for delaminating semiconductive product with reorientation means
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/977—Thinning or removal of substrate
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
- Y10T156/19—Delaminating means
- Y10T156/1978—Delaminating bending means
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
Claims (19)
- 2매의 단결정 실리콘 웨이퍼중 적어도 하나에 산화막을 형성하고; 2매의 웨이퍼중 한 웨이퍼의 상면에 수소이온 또는 희가스(rare gas) 이온을 주입하여 이온주입층(ion implanted layer)을 형성시키고; 상기 이온-주입된 면과 다른 실리콘 웨이퍼의 표면을 산화막을 사이에 두어 밀착시키고; 상기 이온주입층을 벽개면으로 하여 실리콘 웨이퍼를 박막상으로 분리하도록 열처리를 가함에 의해, SOI층을 갖는 SOI웨이퍼를 제조한 다음; 상기 SOI층상에 에피텍셜층을 성장시켜 후막 SOI층을 형성시키는 것을 특징으로 하는 SOI웨이퍼의 제조방법.
- 제1항에 있어서, 에피텍셜층 성장전의 상기 SOI웨이퍼에, 수소를 포함하는 환원성분위기 또는 염화수소가스를 포함하는 분위기하에서 열처리를 행하는 것을 특징으로 하는 SOI웨이퍼의 제조방법.
- 제1항에 있어서, 에피텍셜층 성장전 상기 SOI웨이퍼의 SOI층 두께가 0.2㎛ 이상인 것을 특징으로 하는 SOI웨이퍼의 제조방법.
- 제2항에 있어서, 에피텍셜층 성장전 상기 SOI웨이퍼의 SOI층 두께가 0.2㎛ 이상인 것을 특징으로 하는 SOI웨이퍼의 제조방법.
- 제1항에 있어서, 에피텍셜 성장후 상기 후막SOI층의 두께가 2㎛ 이상인 것을 특징으로 하는 SOI웨이퍼의 제조방법.
- 제2항에 있어서, 에피텍셜 성장후 상기 후막SOI층의 두께가 2㎛ 이상인 것을 특징으로 하는 SOI웨이퍼의 제조방법.
- 제3항에 있어서, 에피텍셜 성장후 상기 후막SOI층의 두께가 2㎛ 이상인 것을 특징으로 하는 SOI웨이퍼의 제조방법.
- 제1항의 방법으로 제조된 SOI웨이퍼.
- 제2항의 방법으로 제조된 SOI웨이퍼.
- 제3항의 방법으로 제조된 SOI웨이퍼.
- 제4항의 방법으로 제조된 SOI웨이퍼.
- 제5항의 방법으로 제조된 SOI웨이퍼.
- 제6항의 방법으로 제조된 SOI웨이퍼.
- 제7항의 방법으로 제조된 SOI웨이퍼.
- 제1항의 방법에서 부산물로 생긴 박리 웨이퍼를 재처리한 후, 실리콘 웨이퍼로 재이용하는 방법.
- 제2항의 방법에서 부산물로 생긴 박리 웨이퍼를 재처리한 후, 실리콘 웨이퍼로 재이용하는 방법.
- 제3항의 방법에서 부산물로 생긴 박리 웨이퍼를 재처리한 후, 실리콘 웨이퍼로 재이용하는 방법.
- 제5항의 방법에서 부산물로 생긴 박리 웨이퍼를 재처리한 후, 실리콘 웨이퍼로 재이용하는 방법.
- SOI층상에 에피텍셜층을 성장시킨 후막 SOI웨이퍼에 있어서, 상기 에피텍셜층 하부의 SOI층중에 데미지층이 존재하는 것을 특징으로 하는 후막 SOI웨이퍼.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20871098A JP3358550B2 (ja) | 1998-07-07 | 1998-07-07 | Soiウエーハの製造方法ならびにこの方法で製造されるsoiウエーハ |
JP10-208710 | 1998-07-07 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20000011406A true KR20000011406A (ko) | 2000-02-25 |
KR100668160B1 KR100668160B1 (ko) | 2007-01-11 |
Family
ID=16560808
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019990026311A KR100668160B1 (ko) | 1998-07-07 | 1999-07-01 | Soi웨이퍼의 제조방법 및 이 방법으로 제조된 soi웨이퍼 |
Country Status (4)
Country | Link |
---|---|
US (2) | US6284629B1 (ko) |
EP (1) | EP0971395A1 (ko) |
JP (1) | JP3358550B2 (ko) |
KR (1) | KR100668160B1 (ko) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100434914B1 (ko) * | 2001-10-19 | 2004-06-09 | 주식회사 실트론 | 고품질 웨이퍼 및 그의 제조방법 |
KR100549257B1 (ko) * | 1999-12-08 | 2006-02-03 | 주식회사 실트론 | 에스오아이 웨이퍼의 표면 정밀 가공 방법 |
KR100753754B1 (ko) * | 2005-04-07 | 2007-08-31 | 가부시키가이샤 섬코 | 에스 오 아이 기판의 제조 방법 및 제조시 층 이송된웨이퍼의 재생 방법 |
KR101478812B1 (ko) * | 2007-06-27 | 2015-01-02 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Soi 기판의 제조방법 및 반도체장치의 제조방법 |
KR20150132383A (ko) * | 2013-03-14 | 2015-11-25 | 썬에디슨 세미컨덕터 리미티드 | 광점 결함들 및 표면 거칠기를 감소시키기 위한 반도체-온-인슐레이터 웨이퍼 제조 방법 |
Families Citing this family (92)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070122997A1 (en) | 1998-02-19 | 2007-05-31 | Silicon Genesis Corporation | Controlled process and resulting device |
US6159825A (en) | 1997-05-12 | 2000-12-12 | Silicon Genesis Corporation | Controlled cleavage thin film separation process using a reusable substrate |
JP3324469B2 (ja) * | 1997-09-26 | 2002-09-17 | 信越半導体株式会社 | Soiウエーハの製造方法ならびにこの方法で製造されるsoiウエーハ |
US6287941B1 (en) | 1999-04-21 | 2001-09-11 | Silicon Genesis Corporation | Surface finishing of SOI substrates using an EPI process |
FR2797714B1 (fr) * | 1999-08-20 | 2001-10-26 | Soitec Silicon On Insulator | Procede de traitement de substrats pour la microelectronique et substrats obtenus par ce procede |
JP2001144275A (ja) * | 1999-08-27 | 2001-05-25 | Shin Etsu Handotai Co Ltd | 貼り合わせsoiウエーハの製造方法および貼り合わせsoiウエーハ |
US6489241B1 (en) * | 1999-09-17 | 2002-12-03 | Applied Materials, Inc. | Apparatus and method for surface finishing a silicon film |
EP1158581B1 (en) * | 1999-10-14 | 2016-04-27 | Shin-Etsu Handotai Co., Ltd. | Method for producing soi wafer |
JP4450126B2 (ja) | 2000-01-21 | 2010-04-14 | 日新電機株式会社 | シリコン系結晶薄膜の形成方法 |
FR2811807B1 (fr) * | 2000-07-12 | 2003-07-04 | Commissariat Energie Atomique | Procede de decoupage d'un bloc de materiau et de formation d'un film mince |
US6420243B1 (en) * | 2000-12-04 | 2002-07-16 | Motorola, Inc. | Method for producing SOI wafers by delamination |
US6670259B1 (en) * | 2001-02-21 | 2003-12-30 | Advanced Micro Devices, Inc. | Inert atom implantation method for SOI gettering |
JP4304879B2 (ja) * | 2001-04-06 | 2009-07-29 | 信越半導体株式会社 | 水素イオンまたは希ガスイオンの注入量の決定方法 |
JP3785067B2 (ja) * | 2001-08-22 | 2006-06-14 | 株式会社東芝 | 半導体素子の製造方法 |
US6656761B2 (en) | 2001-11-21 | 2003-12-02 | Motorola, Inc. | Method for forming a semiconductor device for detecting light |
JPWO2003046993A1 (ja) * | 2001-11-29 | 2005-04-14 | 信越半導体株式会社 | Soiウェーハの製造方法 |
CN100403543C (zh) * | 2001-12-04 | 2008-07-16 | 信越半导体株式会社 | 贴合晶片及贴合晶片的制造方法 |
US6794227B2 (en) | 2002-06-28 | 2004-09-21 | Seh America, Inc. | Method of producing an SOI wafer |
FR2842349B1 (fr) * | 2002-07-09 | 2005-02-18 | Transfert d'une couche mince a partir d'une plaquette comprenant une couche tampon | |
JP2004063730A (ja) * | 2002-07-29 | 2004-02-26 | Shin Etsu Handotai Co Ltd | Soiウェーハの製造方法 |
KR100511656B1 (ko) * | 2002-08-10 | 2005-09-07 | 주식회사 실트론 | 나노 에스오아이 웨이퍼의 제조방법 및 그에 따라 제조된나노 에스오아이 웨이퍼 |
JP2004265904A (ja) * | 2003-01-23 | 2004-09-24 | Shin Etsu Handotai Co Ltd | Soiウエーハ及びその製造方法 |
TW200428637A (en) | 2003-01-23 | 2004-12-16 | Shinetsu Handotai Kk | SOI wafer and production method thereof |
JP2004259970A (ja) * | 2003-02-26 | 2004-09-16 | Shin Etsu Handotai Co Ltd | Soiウエーハの製造方法及びsoiウエーハ |
US20040187769A1 (en) * | 2003-03-27 | 2004-09-30 | Yoshirou Aoki | Method of producing SOI wafer |
CA2520972C (en) * | 2003-04-21 | 2010-01-26 | Sioptical, Inc. | Cmos-compatible integration of silicon-based optical devices with electronic devices |
DE60336543D1 (de) | 2003-05-27 | 2011-05-12 | Soitec Silicon On Insulator | Verfahren zur Herstellung einer heteroepitaktischen Mikrostruktur |
FR2855909B1 (fr) * | 2003-06-06 | 2005-08-26 | Soitec Silicon On Insulator | Procede d'obtention concomitante d'au moins une paire de structures comprenant au moins une couche utile reportee sur un substrat |
US7538010B2 (en) * | 2003-07-24 | 2009-05-26 | S.O.I.Tec Silicon On Insulator Technologies | Method of fabricating an epitaxially grown layer |
FR2857983B1 (fr) * | 2003-07-24 | 2005-09-02 | Soitec Silicon On Insulator | Procede de fabrication d'une couche epitaxiee |
FR2858461B1 (fr) * | 2003-07-30 | 2005-11-04 | Soitec Silicon On Insulator | Realisation d'une structure comprenant une couche protegeant contre des traitements chimiques |
FR2867310B1 (fr) | 2004-03-05 | 2006-05-26 | Soitec Silicon On Insulator | Technique d'amelioration de la qualite d'une couche mince prelevee |
FR2867307B1 (fr) | 2004-03-05 | 2006-05-26 | Soitec Silicon On Insulator | Traitement thermique apres detachement smart-cut |
US7282449B2 (en) | 2004-03-05 | 2007-10-16 | S.O.I.Tec Silicon On Insulator Technologies | Thermal treatment of a semiconductor layer |
US20050236619A1 (en) * | 2004-04-21 | 2005-10-27 | Vipulkumar Patel | CMOS-compatible integration of silicon-based optical devices with electronic devices |
JP4617820B2 (ja) * | 2004-10-20 | 2011-01-26 | 信越半導体株式会社 | 半導体ウェーハの製造方法 |
EP1667223B1 (en) | 2004-11-09 | 2009-01-07 | S.O.I. Tec Silicon on Insulator Technologies S.A. | Method for manufacturing compound material wafers |
US7402520B2 (en) | 2004-11-26 | 2008-07-22 | Applied Materials, Inc. | Edge removal of silicon-on-insulator transfer wafer |
DE102004062356A1 (de) * | 2004-12-23 | 2006-07-13 | Siltronic Ag | Halbleiterscheibe mit einer Halbleiterschicht und einer darunter liegenden elektrisch isolierenden Schicht sowie Verfahren zu deren Herstellung |
US20080315349A1 (en) * | 2005-02-28 | 2008-12-25 | Shin-Etsu Handotai Co., Ltd. | Method for Manufacturing Bonded Wafer and Bonded Wafer |
FR2883659B1 (fr) * | 2005-03-24 | 2007-06-22 | Soitec Silicon On Insulator | Procede de fabrication d'une hetero-structure comportant au moins une couche epaisse de materiau semi-conducteur |
TW200733244A (en) * | 2005-10-06 | 2007-09-01 | Nxp Bv | Semiconductor device |
JP5168788B2 (ja) * | 2006-01-23 | 2013-03-27 | 信越半導体株式会社 | Soiウエーハの製造方法 |
JP5124973B2 (ja) * | 2006-04-18 | 2013-01-23 | 信越半導体株式会社 | Soiウェーハの製造方法 |
US9362439B2 (en) | 2008-05-07 | 2016-06-07 | Silicon Genesis Corporation | Layer transfer of films utilizing controlled shear region |
US7811900B2 (en) | 2006-09-08 | 2010-10-12 | Silicon Genesis Corporation | Method and structure for fabricating solar cells using a thick layer transfer process |
US8993410B2 (en) | 2006-09-08 | 2015-03-31 | Silicon Genesis Corporation | Substrate cleaving under controlled stress conditions |
US8293619B2 (en) | 2008-08-28 | 2012-10-23 | Silicon Genesis Corporation | Layer transfer of films utilizing controlled propagation |
EP1926130A1 (en) * | 2006-11-27 | 2008-05-28 | S.O.I.TEC. Silicon on Insulator Technologies S.A. | Method of improving the surface of a semiconductor substrate |
EP2095415B1 (en) * | 2006-12-26 | 2010-10-27 | S.O.I.Tec Silicon on Insulator Technologies | Method for producing a semiconductor-on-insulator structure |
EP1950803B1 (en) * | 2007-01-24 | 2011-07-27 | S.O.I.TEC Silicon on Insulator Technologies S.A. | Method for manufacturing silicon on Insulator wafers and corresponding wafer |
JP5350655B2 (ja) | 2007-04-27 | 2013-11-27 | 株式会社半導体エネルギー研究所 | 半導体装置 |
JP5280015B2 (ja) * | 2007-05-07 | 2013-09-04 | 信越半導体株式会社 | Soi基板の製造方法 |
JP5272329B2 (ja) * | 2007-05-22 | 2013-08-28 | 信越半導体株式会社 | Soiウエーハの製造方法 |
KR101478813B1 (ko) * | 2007-06-20 | 2015-01-02 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치의 제조 방법 |
JP5245380B2 (ja) | 2007-06-21 | 2013-07-24 | 信越半導体株式会社 | Soiウェーハの製造方法 |
US7989305B2 (en) * | 2007-10-10 | 2011-08-02 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing SOI substrate using cluster ion |
US7696058B2 (en) * | 2007-10-31 | 2010-04-13 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing SOI substrate |
US20090117708A1 (en) * | 2007-11-01 | 2009-05-07 | Sumco Corporation | Method for manufacturing soi substrate |
JP5459900B2 (ja) * | 2007-12-25 | 2014-04-02 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
EP2105957A3 (en) * | 2008-03-26 | 2011-01-19 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing soi substrate and method for manufacturing semiconductor device |
JP5654206B2 (ja) * | 2008-03-26 | 2015-01-14 | 株式会社半導体エネルギー研究所 | Soi基板の作製方法及び該soi基板を用いた半導体装置 |
JP4636110B2 (ja) * | 2008-04-10 | 2011-02-23 | 信越半導体株式会社 | Soi基板の製造方法 |
JP5496540B2 (ja) | 2008-04-24 | 2014-05-21 | 株式会社半導体エネルギー研究所 | 半導体基板の作製方法 |
US7947523B2 (en) * | 2008-04-25 | 2011-05-24 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing photoelectric conversion device |
US7951656B2 (en) * | 2008-06-06 | 2011-05-31 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
US7776624B2 (en) * | 2008-07-08 | 2010-08-17 | International Business Machines Corporation | Method for improving semiconductor surfaces |
US8330126B2 (en) | 2008-08-25 | 2012-12-11 | Silicon Genesis Corporation | Race track configuration and method for wafering silicon solar substrates |
JP5625239B2 (ja) * | 2008-12-25 | 2014-11-19 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
US8329557B2 (en) | 2009-05-13 | 2012-12-11 | Silicon Genesis Corporation | Techniques for forming thin films by implantation with reduced channeling |
JP2011029594A (ja) * | 2009-06-22 | 2011-02-10 | Shin Etsu Handotai Co Ltd | Soiウェーハの製造方法及びsoiウェーハ |
SG176602A1 (en) * | 2009-06-24 | 2012-01-30 | Semiconductor Energy Lab | Method for reprocessing semiconductor substrate and method for manufacturing soi substrate |
US8278187B2 (en) * | 2009-06-24 | 2012-10-02 | Semiconductor Energy Laboratory Co., Ltd. | Method for reprocessing semiconductor substrate by stepwise etching with at least two etching treatments |
KR101752901B1 (ko) * | 2009-08-25 | 2017-06-30 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 기판의 재생 방법, 재생 반도체 기판의 제작 방법, 및 soi 기판의 제작 방법 |
US8318588B2 (en) * | 2009-08-25 | 2012-11-27 | Semiconductor Energy Laboratory Co., Ltd. | Method for reprocessing semiconductor substrate, method for manufacturing reprocessed semiconductor substrate, and method for manufacturing SOI substrate |
EP2474995B1 (en) | 2009-09-04 | 2014-04-30 | Shin-Etsu Handotai Co., Ltd. | Method for manufacturing soi wafer |
SG178179A1 (en) | 2009-10-09 | 2012-03-29 | Semiconductor Energy Lab | Reprocessing method of semiconductor substrate, manufacturing method of reprocessed semiconductor substrate, and manufacturing method of soi substrate |
JP5706670B2 (ja) | 2009-11-24 | 2015-04-22 | 株式会社半導体エネルギー研究所 | Soi基板の作製方法 |
US8080464B2 (en) * | 2009-12-29 | 2011-12-20 | MEMC Electronics Materials, Inc, | Methods for processing silicon on insulator wafers |
JP5521561B2 (ja) | 2010-01-12 | 2014-06-18 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
US7935612B1 (en) * | 2010-02-05 | 2011-05-03 | International Business Machines Corporation | Layer transfer using boron-doped SiGe layer |
JP2011253906A (ja) * | 2010-06-01 | 2011-12-15 | Shin Etsu Handotai Co Ltd | 貼り合わせウェーハの製造方法 |
JP2012064802A (ja) * | 2010-09-16 | 2012-03-29 | Shin Etsu Handotai Co Ltd | 貼り合わせウェーハの製造方法 |
US8404562B2 (en) * | 2010-09-30 | 2013-03-26 | Infineon Technologies Ag | Method for manufacturing a composite wafer having a graphite core, and composite wafer having a graphite core |
JP5541136B2 (ja) * | 2010-12-15 | 2014-07-09 | 信越半導体株式会社 | 貼り合わせsoiウエーハの製造方法 |
JP5477277B2 (ja) | 2010-12-20 | 2014-04-23 | 信越半導体株式会社 | Soiウェーハの製造方法 |
US9123529B2 (en) | 2011-06-21 | 2015-09-01 | Semiconductor Energy Laboratory Co., Ltd. | Method for reprocessing semiconductor substrate, method for manufacturing reprocessed semiconductor substrate, and method for manufacturing SOI substrate |
JP5418564B2 (ja) | 2011-09-29 | 2014-02-19 | 信越半導体株式会社 | 貼り合わせsoiウェーハの反りを算出する方法、及び貼り合わせsoiウェーハの製造方法 |
JP6186984B2 (ja) * | 2013-07-25 | 2017-08-30 | 三菱電機株式会社 | 半導体装置の製造方法 |
CN103794467A (zh) * | 2014-02-21 | 2014-05-14 | 上海超硅半导体有限公司 | 一种薄硅片的重新利用方法 |
CN104925748B (zh) * | 2014-03-19 | 2017-06-13 | 中芯国际集成电路制造(上海)有限公司 | 一种提高晶圆间键合强度的方法 |
CN108878349A (zh) * | 2018-06-27 | 2018-11-23 | 北京工业大学 | 一种新型soi衬底的结构及其制备方法 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
NL8501773A (nl) * | 1985-06-20 | 1987-01-16 | Philips Nv | Werkwijze voor het vervaardigen van halfgeleiderinrichtingen. |
US5254830A (en) | 1991-05-07 | 1993-10-19 | Hughes Aircraft Company | System for removing material from semiconductor wafers using a contained plasma |
TW211621B (ko) * | 1991-07-31 | 1993-08-21 | Canon Kk | |
FR2681472B1 (fr) | 1991-09-18 | 1993-10-29 | Commissariat Energie Atomique | Procede de fabrication de films minces de materiau semiconducteur. |
EP1251556B1 (en) * | 1992-01-30 | 2010-03-24 | Canon Kabushiki Kaisha | Process for producing semiconductor substrate |
US5659192A (en) * | 1993-06-30 | 1997-08-19 | Honeywell Inc. | SOI substrate fabrication |
JP3352340B2 (ja) * | 1995-10-06 | 2002-12-03 | キヤノン株式会社 | 半導体基体とその製造方法 |
US5989981A (en) * | 1996-07-05 | 1999-11-23 | Nippon Telegraph And Telephone Corporation | Method of manufacturing SOI substrate |
SG65697A1 (en) * | 1996-11-15 | 1999-06-22 | Canon Kk | Process for producing semiconductor article |
JPH10223497A (ja) * | 1997-01-31 | 1998-08-21 | Shin Etsu Handotai Co Ltd | 貼り合わせ基板の作製方法 |
JPH10275905A (ja) * | 1997-03-31 | 1998-10-13 | Mitsubishi Electric Corp | シリコンウェーハの製造方法およびシリコンウェーハ |
JP3864495B2 (ja) * | 1997-05-15 | 2006-12-27 | 株式会社デンソー | 半導体基板の製造方法 |
US6159825A (en) * | 1997-05-12 | 2000-12-12 | Silicon Genesis Corporation | Controlled cleavage thin film separation process using a reusable substrate |
US6204151B1 (en) * | 1999-04-21 | 2001-03-20 | Silicon Genesis Corporation | Smoothing method for cleaved films made using thermal treatment |
-
1998
- 1998-07-07 JP JP20871098A patent/JP3358550B2/ja not_active Expired - Lifetime
-
1999
- 1999-06-29 US US09/343,074 patent/US6284629B1/en not_active Expired - Lifetime
- 1999-06-29 EP EP99305120A patent/EP0971395A1/en not_active Withdrawn
- 1999-07-01 KR KR1019990026311A patent/KR100668160B1/ko not_active IP Right Cessation
-
2001
- 2001-07-16 US US09/906,873 patent/US20010046746A1/en not_active Abandoned
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100549257B1 (ko) * | 1999-12-08 | 2006-02-03 | 주식회사 실트론 | 에스오아이 웨이퍼의 표면 정밀 가공 방법 |
KR100434914B1 (ko) * | 2001-10-19 | 2004-06-09 | 주식회사 실트론 | 고품질 웨이퍼 및 그의 제조방법 |
KR100753754B1 (ko) * | 2005-04-07 | 2007-08-31 | 가부시키가이샤 섬코 | 에스 오 아이 기판의 제조 방법 및 제조시 층 이송된웨이퍼의 재생 방법 |
US7790573B2 (en) | 2005-04-07 | 2010-09-07 | Sumco Corporation | Process for producing SOI substrate and process for regeneration of layer transferred wafer in the production |
KR101478812B1 (ko) * | 2007-06-27 | 2015-01-02 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Soi 기판의 제조방법 및 반도체장치의 제조방법 |
KR20150132383A (ko) * | 2013-03-14 | 2015-11-25 | 썬에디슨 세미컨덕터 리미티드 | 광점 결함들 및 표면 거칠기를 감소시키기 위한 반도체-온-인슐레이터 웨이퍼 제조 방법 |
Also Published As
Publication number | Publication date |
---|---|
JP3358550B2 (ja) | 2002-12-24 |
US6284629B1 (en) | 2001-09-04 |
US20010046746A1 (en) | 2001-11-29 |
EP0971395A1 (en) | 2000-01-12 |
KR100668160B1 (ko) | 2007-01-11 |
JP2000030995A (ja) | 2000-01-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100668160B1 (ko) | Soi웨이퍼의 제조방법 및 이 방법으로 제조된 soi웨이퍼 | |
US6489654B2 (en) | Silicon-on-insulator (SOI) substrate | |
EP0843345B1 (en) | Method of manufacturing a semiconductor article | |
US6054363A (en) | Method of manufacturing semiconductor article | |
US5966620A (en) | Process for producing semiconductor article | |
US10475694B2 (en) | Handle substrate for use in manufacture of semiconductor-on-insulator structure and method of manufacturing thereof | |
CA2233096C (en) | Substrate and production method thereof | |
US6350702B2 (en) | Fabrication process of semiconductor substrate | |
EP0843346B1 (en) | Method of manufacturing a semiconductor article | |
US7186628B2 (en) | Method of manufacturing an SOI wafer where COP's are eliminated within the base wafer | |
WO2005024925A1 (ja) | Soiウェーハの作製方法 | |
KR101142138B1 (ko) | 적층기판의 세척방법, 기판의 접합방법 및 접합 웨이퍼의제조방법 | |
EP2053650B1 (en) | Method for producing semiconductor substrate | |
JPH10326883A (ja) | 基板及びその作製方法 | |
USRE41841E1 (en) | Method for making a silicon substrate comprising a buried thin silicon oxide film | |
JP3293767B2 (ja) | 半導体部材の製造方法 | |
EP3809448B1 (en) | Bonded soi wafer and method for manufacturing bonded soi wafer | |
EP3370249A1 (en) | Bonded soi wafer manufacturing method | |
JP3293766B2 (ja) | 半導体部材の製造方法 | |
JPH11195774A (ja) | 半導体基板の作成方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
E902 | Notification of reason for refusal | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20121227 Year of fee payment: 7 |
|
FPAY | Annual fee payment |
Payment date: 20131218 Year of fee payment: 8 |
|
FPAY | Annual fee payment |
Payment date: 20141230 Year of fee payment: 9 |
|
FPAY | Annual fee payment |
Payment date: 20151217 Year of fee payment: 10 |
|
FPAY | Annual fee payment |
Payment date: 20161221 Year of fee payment: 11 |
|
FPAY | Annual fee payment |
Payment date: 20171219 Year of fee payment: 12 |
|
LAPS | Lapse due to unpaid annual fee |