US20010046746A1 - Method of fabricating an SOI wafer and SOI wafer fabricated by the method - Google Patents

Method of fabricating an SOI wafer and SOI wafer fabricated by the method Download PDF

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US20010046746A1
US20010046746A1 US09906873 US90687301A US2001046746A1 US 20010046746 A1 US20010046746 A1 US 20010046746A1 US 09906873 US09906873 US 09906873 US 90687301 A US90687301 A US 90687301A US 2001046746 A1 US2001046746 A1 US 2001046746A1
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soi
wafer
layer
method
soi wafer
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Isao Yokokawa
Naoto Tate
Kiyoshi Mitani
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Shin-Etsu Handotai Co Ltd
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Shin-Etsu Handotai Co Ltd
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S156/00Adhesive bonding and miscellaneous chemical manufacture
    • Y10S156/934Apparatus having delaminating means adapted for delaminating a specified article
    • Y10S156/941Means for delaminating semiconductive product
    • Y10S156/942Means for delaminating semiconductive product with reorientation means
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/977Thinning or removal of substrate
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/19Delaminating means
    • Y10T156/1978Delaminating bending means

Abstract

There is disclosed a method of fabricating an SOI wafer wherein an oxide film is formed on at least one of two single crystal silicon wafers; hydrogen ions or rare gas ions are implanted into the upper surface of one of the two silicon wafers in order to form an ion implanted layer; the ion-implanted surface is brought into close contact with the surface of the other silicon wafer via the oxide film; heat treatment is performed to separate a thin film from the silicon wafer with using the ion implanted layer as a delaminating plane to fabricate the SOI wafer having an SOI layer; and then an epitaxial layer is grown on the SOI layer to form a thick SOI layer. There is provided an SOI wafer which has a thick SOI layer with good thickness uniformity and good crystallinity and which is useful for a bipolar device or a power device.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • The present invention relates to a method of increasing thickness of an SOI (silicon on insulator) layer in an SOI structure wafer obtained by a method wherein an ion-implanted wafer is bonded to another wafer and a portion of the ion-implanted wafer is delaminated to provide an SOI wafer (the technique called a hydrogen ion delamination method, or a smart-cut method), and an SOI wafer produced by the method. [0002]
  • 2. Description of the Related Art [0003]
  • One of typical method for producing an SOI wafer is a so-called wafer bonding method in which two mirror-polished silicon wafers are bonded together via an oxide film without use of adhesive, then subjected to a heat treatment (generally 1000° C. to 1200° C.) to increase a bonding strength, and one of the wafers is subsequently made thin. [0004]
  • In the wafer bonding method, thickness of one of the two wafers which are bonded to each other is made thin with grinding or etching to some extent, and then the surface thereof is subjected to a mechanochemical polishing to be finished to have an intended thickness of the SOI layer. [0005]
  • The SOI wafer fabricated according to the method has an advantage that crystallinity of the SOI layer and reliability of a buried oxide layer are as high as those of general silicon wafers. However, it has a disadvantage that thickness uniformity of the SOI layer achieved in the method is limited. Namely, only the uniformity in the surface of the intended thickness ±0.3 μm can be achieved even if a highly precise processing method is used. Furthermore, there exists a problem of high production cost, since only one SOI wafer can be obtained from two silicon wafers. [0006]
  • Recently, a new method of fabricating an SOI wafer in which an ion-implanted wafer is bonded to another wafer and the wafers are then subjected to a heat treatment to be delaminated at an ion implanted layer (the technique called a hydrogen ion delamination method, or a smart-cut method) has been proposed in Japanese Patent Application Laid-Open (kokai) No. 5-211128. In this method, an oxide film is formed on the surface of at least one of two silicon wafers; hydrogen ions or rare gas ions are implanted into one surface of one of the two silicon wafers in order to form a fine bubble layer (enclosed layer) within the wafer; the ion-implanted silicon wafer is superposed on the other silicon wafer such that the ion-implanted surface comes into close contact with the surface of the other silicon wafer via the oxide film; heat treatment at 500° C. or more is then performed to delaminate a portion of the ion-implanted wafer with using the fine bubble layer as a delaminating plane, so as to delaminate a thin film; and heat treatment at high temperature is further performed to firmly bond the wafers to each other, to thereby obtain an SOI wafer. According to the method, the SOI wafer having a thickness uniformity of ±0.01 μm or less can be fabricated relatively easily. [0007]
  • A so-called thick layer SOI wafer which has a SOI layer having a thickness of several microns to tens microns is very useful for a bipolar device or a power device, and further development thereof is greatly expected. [0008]
  • The thick layer SOI wafer has been conventionally fabricated by the above-mentioned wafer bonding method, namely, by bonding a wafer having an oxide film and a bare wafer to each other, subjecting them to a bonding heat treatment at 1100° C., and grinding and polishing them to provide a thick layer SOI wafer having a desired thickness. In the method, since the wafers are not bonded to each other in the peripheral part, it is necessary to perform an edge treatment step for removing the unbonded portion before polishing. Such a step makes the method complicate, and increases production cost. Furthermore, it is not possible to improve thickness uniformity of the SOI layer only by a polishing process, and therefore, a vapor phase etching treatment called PACE (Plasma Assisted Chemical Etching) disclosed in Japanese Patent Application Laid-Open (kokai) No. 5-160074 has been performed to make thickness uniform, and the mirror polishing has been performed to remove hazes or the like. When polishing is performed after the vapor phase etching as described above, thickness uniformity of the SOI layer may be rather deteriorated, latent flaws or a damage layer may be incorporated, and crystallinity may be lowered. Furthermore, processing cost is high also in that case. [0009]
  • On the other hand, the hydrogen ion delamination method are significantly advantageous in productivity and cost performance, since the edge treatment process which is essential in the above-mentioned wafer bonding method is not necessary. [0010]
  • However, only an SOI layer having a thickness of 2 μm at most can be produced by the method, since the thickness of the SOI layer depends on a depth of ion implantation, which depends on an acceleration voltage of an ion implanter, and only about 200 keV of acceleration voltage at most is possible in high current ion implanter generally used for mass-production, because of limitation in the apparatus. [0011]
  • Accordingly, in order to form a thicker SOI layer by the hydrogen ion delamination method, the high current ion implanter which can provide a higher acceleration voltage is necessary. However, when the apparatus which can provide high acceleration voltage more than 200 keV is used, it takes long time to achieve a certain amount of ion implantation and thus cost is increased, since it is difficult to obtain high current by such an apparatus. Therefore, such an apparatus has not been used in mass-production. Furthermore, as in a PACE method, there is also a problem that a process such as polishing or the like is necessary in order to improve a surface roughness on the surface of SOI after delamination. [0012]
  • SUMMARY OF THE INVENTION
  • The present invention has been accomplished to solve the above-mentioned problems, and a major object of the present invention is to provide a method of fabricating a thick layer SOI wafer having excellent thickness uniformity in high productivity and at low cost by forming a silicon film on an SOI wafer obtained by hydrogen ion delamination method. [0013]
  • To achieve the above mentioned object, the present invention provides a method of fabricating an SOI wafer characterized in that an oxide film is formed on at least one of two single crystal silicon wafers; hydrogen ions or rare gas ions are implanted into the upper surface of one of the two silicon wafers in order to form an ion implanted layer; the ion-implanted surface is brought into close contact with the surface of the other silicon wafer via the oxide film; heat treatment is performed to separate a thin film from the silicon wafer with using the ion implanted layer as a delaminating plane to fabricate the SOI wafer having an SOI layer; and then an epitaxial layer is grown on the SOI layer to form a thick SOI layer. [0014]
  • As described above, when the epitaxial layer is grown on the SOI layer without polishing delaminating plane of the SOI layer after the SOI wafer having the SOI layer is obtained by the hydrogen ion delamination method, the thick layer SOI wafer having a good thickness uniformity can be fabricated in good yield and in high productivity. Furthermore, since the SOI wafer is exposed to hydrogen atmosphere while the temperature is increased before epitaxial growth to thereby improve surface roughness of the surface of the SOI layer, surface roughness of the thick layer SOI wafer after growth of the epitaxial layer can also be improved. [0015]
  • In that case, since the epitaxial layer is formed on the delaminated surface of the SOI layer that still include a damage layer caused by ion implantation in some degree, the thick layer SOI wafer having the damage layer in the SOI layer under the epitaxial layer can be fabricated. In the wafer, the damage layer can be used as a gettering site for removing impurities such as heavy metal from the device active layer. [0016]
  • When the SOI wafer before epitaxial growth is subjected to a heat treatment in a reducing atmosphere including hydrogen or in an atmosphere including hydrogen chloride gas, a damage layer remaining on the delaminated surface of SOI layer can be removed, so that the epitaxial layer can be grown on the delaminated surface whose surface roughness has been improved. As a result, an SOI wafer that contains very few crystal defects and has a thick SOI layer with high quality such as good thickness uniformity and surface roughness can be fabricated. [0017]
  • When the SOI wafer is fabricated using the silicon wafer produced by Czochralski method (CZ method), void type defects having a size of 0.1 to 0.2 μm, called COP (Crystal Originated Particle), are present in the SOI layer. Accordingly, if the thickness of the SOI layer is thinner than the size of COP, hydrogen gas used in the epitaxial growth process passes through the COP, and etches the buried oxide layer, resulting in degradation of characteristics of SOI wafer. [0018]
  • Accordingly, the thickness of the SOI layer of the SOI wafer before growth of the epitaxial layer is preferably 0.2 μm or more, to surely prevent the buried oxide layer from being etched during the epitaxial growth process. [0019]
  • The thickness of the thick SOI layer after epitaxial growth is preferably more than 2 μm. [0020]
  • When the thick SOI layer is formed as described above, the thick SOI layer which is quite useful for a bipolar device or a power device and has good thickness uniformity can be fabricated in high productivity and with good cost performance. [0021]
  • The present invention also provides an SOI wafer fabricated by the method described above. [0022]
  • Such an SOI wafer is excellent in thickness uniformity and electric characteristics, and therefore is quite useful for a bipolar device or a power device. [0023]
  • The present invention also provides a method for reusing a delaminated wafer produced as a by-product in the methods described above as a silicon wafer by reprocessing it. [0024]
  • According to the method, a delaminated wafer produced as a by-product in the hydrogen ion delamination method of the present invention can also be reused as a silicon wafer after being reprocessed appropriately, and as a result, yield and productivity of the SOI wafer which has a thick SOI layer with good quality can be improved, and cost reduction can be achieved. [0025]
  • As described above, according to the present invention, an SOI wafer having a thick SOI layer excellent in thickness uniformity, crystallinity and electric characteristics, which is useful as a bipolar device or a power device, or an SOI wafer having a gettering site in the SOI layer and having a strong resistance to heavy metal contamination can be fabricated relatively easily at low cost. [0026]
  • Furthermore, in the method of the present invention, neither a process for making a film thin nor a polishing process for improving surface roughness is necessary, and therefore amounts of water to be used and industrial wastes such as polishing slurry are reduced, and thus, harmful influence on environment can be prevented. Furthermore, since a process for removing the unbonded part in the periphery of the wafer is not necessary, productivity and yield are further improved, enabling drastic cost reduction. Recycle of the delaminated wafer produced as a by product as a silicon wafer may further reduce the cost.[0027]
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a flowchart showing an example of an SOI-wafer fabricating process of the present invention.[0028]
  • DESCRIPTION OF THE INVENTION AND A PREFERRED EMBODIMENT
  • The present invention will be further described below in detail, referring a figure, but is not limited thereto. [0029]
  • FIG. 1 is a flowchart showing an example of an SOI wafer fabricating process including an epitaxial growth process, in which an ion-implanted wafer is bonded to another wafer and a portion of the ion-implanted wafer is delaminated to thereby fabricate an SOI wafer. [0030]
  • The hydrogen ion delamination method can be performed in two different ways, namely Method A and Method B which are different from each other in the sequence of process steps. First, a method of fabricating SOI wafer having thick film of the present invention according to Method A will be described. [0031]
  • In Step [0032] 1 of Method A as shown in FIG. 1 (1), two silicon mirror wafers 20, 21 which are suitable for device specifications are prepared.
  • In Step [0033] 2, at least one of the wafers (the wafer 20 in this case) is subjected to thermal oxidation so as to form on the surface thereof an oxide film 30 having a thickness of about 0.1 μm to 2.0 μm. In the figure, the oxide film is formed only on one surface. However, the oxide film may be formed all over the surface of the wafer 20.
  • In Step [0034] 3, hydrogen ions or rare gas ions are implanted into one surface of the other wafer 21, in order to form a fine bubble layer (enclosed layer) 40 which lies in parallel to the surface at a position corresponding to the mean depth of ion implantation. The implantation temperature is preferably 25-450° C.
  • Depth of implantation of ions depends on acceleration voltage of an ion implanter, and the thickness of SOI layer after delamination depends on the depth of implantation of ions. However, there is a limit to acceleration voltage of the ion implanter. The acceleration voltage of about 200 keV, which means thickness of about 2 μm, for example, in the case of hydrogen ion implantation, is upper limit at present. [0035]
  • In Step [0036] 4, the wafer 20 is superposed on the hydrogen ion-implanted surface of the hydrogen ion-implanted wafer 21 via the oxide film 30, and they are brought in close contact with each other. When the surfaces of the two wafers are brought into contact with each other at ambient temperature in a clean atmosphere, the wafers are bonded to each other without use of adhesive or the like.
  • In Step [0037] 5, there is performed a heat treatment for delamination in which the upper silicon (a delamination wafer) 28 is delaminated from the lower SOI wafer 10 (composed of the SOI layer 25, a buried oxide layer 26, and a base wafer 27) at the enclosed layer 40. The heat treatment is performed at a temperature of about 500° C. or higher in an inert gas atmosphere so as to cause crystal rearrangement and bubble cohesion, and thereby the delamination wafer 28 is delaminated (separated) from the lower SOI wafer. As described above, the delaminated wafer 28 is produced as a by-product in Step 5 in the present invention.
  • In Step [0038] 6, the wafers which have been bonded to each other in the above-mentioned Step 4, the bonding step, are subjected to heat treatment in order to improve bonding strength to a sufficient level, since the bonding strength imparted in Step 4 is too low for use in a device process. Preferably, this heat treatment is performed in an inert gas atmosphere or an oxidizing gas atmosphere at 1050-1200° C. for 30 minutes to 2 hours.
  • The heat treatment for delamination in Step [0039] 5 and the heat treatment for bonding in Step 6 as mentioned above may be successively performed. Alternatively, a single heat treatment serving as both of Steps 5 and 6 may be performed. The steps described above are the same as the steps of the method for fabricating an SOI wafer according to a general hydrogen ion delamination method.
  • In Step [0040] 7, the epitaxial layer is grown on the delaminated surface 50 which is a surface of the SOI layer 25 obtained by a hydrogen ion delamination method in order to increase a thickness of the SOI layer to a desired thickness which is more than 2 μm.
  • In Method A, since there is a region (non bonding portion) where an oxide film [0041] 30 (buried oxide layer 26) is exposed in the peripheral part of SOI wafer 10 after the delamination heat treatment, it is necessary to remove it in advance with an aqueous solution of hydrofluoric acid or the like before epitaxial growth. The SOI wafer 10 finally obtained after epitaxial layer growth consists of a thick SOI layer 60 having a total thickness of several microns to several tens microns, a buried oxide layer 26 and a base wafer 27.
  • Epitaxial growth may be performed according to CVD method as generally performed, for example, by reducing SiCl[0042] 4, SiHCl3, SiH2Cl2, SiH4 or the like with hydrogen at 1100-1200° C., to precipitate Si so that epitaxial growth may be obtained in the same crystal orientation as that of the used silicon wafer.
  • Alternatively, epitaxial growth can also be performed according to a molecular beam epitaxy method (MBE method) under super high vacuum (10[0043] −8 to 10−11 Torr), at low temperature as 600 to 900° C.
  • The sequence of the above-mentioned steps, namely the Steps [0044] 5-6-7 may be changed to the Steps 5-7-6.
  • The bonding heat treatment of Step [0045] 6 and epitaxial growth of Step 7 can also be performed successively, or the treatment serving as both of Step 6 and Step 7 can also be performed.
  • For example, a general epitaxial growing process comprises providing a reactant gas to deposit a epitaxial layer after increasing temperature to 1000 to 1200° C. in 100% hydrogen atmosphere. Even only the above-mentioned process can improve bonding strength with epitaxial growth. Alternatively, a damage layer on the surface of the SOI is etched by being kept in an atmosphere of hydrogen or a mixed atmosphere of hydrogen chloride gas and hydrogen for a predetermined period after increasing the temperature around a reaction temperature, and then the deposition of the epitaxial layer can be successively performed. In that case, bonding strength can also be improved as a result. [0046]
  • Step [0047] 6 and Step 7 can be performed successively or at the same time in the same epitaxial apparatus in the above method, and thus the method is very advantageous in productivity and cost performance.
  • As described above, when epitaxial growth of silicon is performed on the delaminated surface of the SOI layer obtained by the hydrogen ion delamination method, the thick SOI layer having a total thickness of several microns to several tens microns can be obtained relatively easily, and an SOI wafer having uniform thickness, containing almost no crystal defects, and excellent in electric characteristics, or an SOI wafer having a gettering site in the SOI layer and having a resistibility to heavy metal contamination can be fabricated. [0048]
  • Next will be described a method of fabricating SOI wafer according to Method B. In Step [0049] 1 of Method B, there are prepared two mirror silicon wafers 22 and 23 suitable for device specifications.
  • In Step [0050] 2, at least one of the wafers is subjected to thermal oxidation to form on the surface thereof an oxide film 31 having a thickness of about 0.1-2.0 μm.
  • In Step [0051] 3, hydrogen ions or rare gas ions are implanted into the oxide film 31 of the wafer 23 in order to form a fine bubble layer (enclosed layer) 41 which lies in parallel to the surface at a position corresponding to the mean depth of ion implantation. The implantation temperature is preferably 25-450° C.
  • In Step [0052] 4, the silicon wafer 22 is superposed on the surface of the oxide film 31, which is the surface to which hydrogen ions have been implanted, of the ion-implanted wafer 23. When the surface of the two wafers are brought into contact with each other at ambient temperature in a clean atmosphere, the wafers are bonded to each other without use of adhesive or the like.
  • Subsequently, in Steps [0053] 5 to 7, the same treatment processes as those in Method A are performed, to thereby obtain an SOI wafer which has a thick SOI layer having uniform thickness without crystal defects.
  • Step [0054] 8 in this method is a step for reusing a delaminated wafer. In this step, the delaminated wafer 28 produced as a by-product in the Step 5, which is a step of the heat treatment for delamination, is reused as a silicon wafer. The wafers produced as a by-product in either Method A or Method B can be reused.
  • The step for reusing is designed suitably depending on the quality of the delaminated wafer. For example, when a step due to an unbonded portion and an oxide film or a damage layer remains in the peripheral part of the delaminated wafer, the reusing step includes a polishing process for polishing the delaminated surface. [0055]
  • The heat treatment in a reducing atmosphere including hydrogen can also be performed to remove the damage layer on the surface and improve the surface roughness. [0056]
  • EXAMPLES
  • The following examples are being submitted to further explain the present invention. These examples are not intended to limit the scope of the present invention. [0057]
  • Example 1
  • Two CZ silicon mirror wafers of conductive type p having a resistivity of 10 Ω·cm, a diameter of 150 mm and crystal axis of <100> were prepared. These wafers were processed through Steps [0058] 1 to 8 of Method B shown in FIG. 1 to thereby obtain SOI wafers according to the hydrogen ion delamination method, which have an SOI layer having a thickness of 0.5 μm, and then an epitaxial layer is grown by CVD method to produce SOI wafers which have a thick SOI layer having a total thickness of 2.0 μm.
  • The major process conditions for fabricating SOI wafers were as follows. [0059]
  • a) Thickness of the oxide film in Step [0060] 2: 80 nm;
  • b) Condition of hydrogen implantation in Step [0061] 3: H+ ions, implantation energy: 67 keV, implantation dose: 8×1016/cm2;
  • c) Conditions of heat treatment for delamination in Step [0062] 5: in a N2 gas atmosphere, at 500° C. for 30 minutes;
  • d) Bonding heat treatment of Step [0063] 6: none (Step 7 serves also as it);
  • e) Conditions of epitaxial growth by CVD method in Step [0064] 7: H2 bake (H2 atmosphere, 1110° C., 60 seconds), epitaxial layer deposition (SiHCl3+H2, 1110° C., 60 seconds).
  • An SOI layer having a thickness of 0.5 μm was formed according to the hydrogen ion delamination method in Step [0065] 5, and a thick SOI layer having a total thickness of 2.0 μm was formed by performing epitaxial growth of 1.5 μm according to the CVD method in Step 7.
  • Thickness uniformity and surface roughness of the SOI layer of the SOI wafer just delaminated after the heat treatment for delamination of Step [0066] 5 was measured. Thickness was measured by the spectral reflectance measurement at several thousands points in 2 mm pitch on the surface area other than the area within 10 mm from the periphery of the SOI wafer, and the results were indicated in RMS value (root-mean-square value). According to the results, a sigma (standard deviation) of the thickness of the SOI layer after the delamination heat treatment was 0.6 nm, and therefore thickness uniformity (3 sigma) was ±1.8 nm. Surface roughness was measured by an atomic force microscope over a measuring area of 1 μm square, and it was expressed in the RMS value (root-mean-square roughness) as about 7.6 nm.
  • On the other hand, thickness distribution of the SOI layer after epitaxial growth in Step [0067] 7 was measured. A sigma (standard deviation) of the thickness was 18.4 nm, and therefore thickness uniformity (3 sigma) was ±55.4 nm. From the results, it is apparent that thickness uniformity was lowered little by the epitaxial growth, but was still quite excellent compared with the value, ±0.3 μm, of the wafer fabricated by a general wafer bonding method. Surface roughness was Rms value of about 0.29 nm and quite excellent.
  • The SOI wafer was divided into four pieces after the epitaxial growth, and a defect density in the depth direction of the SOI layer was measured. The four pieces of the wafer were etched with KOH aqueous solution at a etching removal of 1.5, 1.0, 0.5, 0 μm from the surface. The pieces were then subjected to the four step Secco etching method disclosed in H. Gassel et al. (J. Electrochem. Soc., 140, pp1713, 1993), and observed with a microscope to count a density of pits existing on the surface. [0068]
  • The defect density was 10[0069] 2/cm2 or less at any depth, which was equal to or less than that of a general bulk wafer, and was quite excellent.
  • Example 2
  • An SOI wafer having a total thickness of 7.0 μm was fabricated in the same manner as Example 1 except that thickness achieved by epitaxial growth was 6.5 μm and an epitaxial layer was deposited without H[0070] 2 bake (the heat treatment in approximately 100% hydrogen atmosphere). Surface roughness expressed in the RMS value was quite excellent as about 0.33 nm.
  • The SOI wafer was divided into four pieces. One of them was subjected to a general preferential etching (Secco etching) at an etching removal of 1 μm, and observed with a microscope to measure the defect density on the surface. No defect such as stacking fault was observed. [0071]
  • The other three of them were evaluated as for the defect density in the depth direction of the SOI layer in the same manner as Example 1 except that the etching removal with an aqueous solution of KOH was 5.0, 6.0 or 6.5 μm from the surface of each piece. [0072]
  • As for the two of them in which the etching removal was 5.0, 6.0 μm respectively, the defect density was 10[0073] 2/cm2 or less, as well as Example 1. As for the wafer in which the etching removal was 6.5 μm (etching to a position at which epitaxial layer had began to grow), the defect density was 7×103/cm2. The results showed that the SOI layer under the epitaxial layer still included a damage that was generated when hydrogen ion was implanted. The damage layer can be used as a gettering site for removing impurity such as heavy metals from the device active layer.
  • The present invention is not limited to the above-described embodiment. The above-described embodiment is a mere example, and those having substantially the same structure as that described in the appended claims and providing the similar action and effects are all included in the scope of the present invention. [0074]

Claims (19)

    What is claimed is:
  1. 1. A method of fabricating an SOI wafer wherein an oxide film is formed on at least one of two single crystal silicon wafers; hydrogen ions or rare gas ions are implanted into the upper surface of one of the two silicon wafers in order to form an ion implanted layer; the ion-implanted surface is brought into close contact with the surface of the other silicon wafer via the oxide film; heat treatment is performed to separate a thin film from the silicon wafer with using the ion implanted layer as a delaminating plane to fabricate the SOI wafer having an SOI layer; and then an epitaxial layer is grown on the SOI layer to form a thick SOI.
  2. 2. The method of fabricating an SOI wafer according to
    claim 1
    wherein the SOI wafer before the growth of the epitaxial layer is subjected to a heat treatment in a reducing atmosphere including hydrogen or in an atmosphere including hydrogen chloride gas.
  3. 3. The method of fabricating an SOI wafer according to
    claim 1
    wherein the thickness of the SOI layer of the SOI wafer before growth of the epitaxial layer is 0.2 μm or more.
  4. 4. The method of fabricating an SOI wafer according to
    claim 2
    wherein the thickness of the SOI layer of the SOI wafer before growth of the epitaxial layer is 0.2 μm or more.
  5. 5. The method of fabricating an SOI wafer according to
    claim 1
    wherein the thickness of the thick SOI layer after the epitaxial growth is 2 μm or more.
  6. 6. The method of fabricating an SOI wafer according to
    claim 2
    wherein the thickness of the thick SOI layer after the epitaxial growth is 2 μm or more.
  7. 7. The method of fabricating an SOI wafer according to
    claim 3
    wherein the thickness of the thick SOI layer after the epitaxial growth is 2 μm or more.
  8. 8. An SOI wafer fabricated by the method according to
    claim 1
    .
  9. 9. An SOI wafer fabricated by the method according to
    claim 2
    .
  10. 10. An SOI wafer fabricated by the method according to
    claim 3
    .
  11. 11. An SOI wafer fabricated by the method according to
    claim 4
    .
  12. 12. An SOI wafer fabricated by the method according to
    claim 5
    .
  13. 13. An SOI wafer fabricated by the method according to
    claim 6
    .
  14. 14. An SOI wafer fabricated by the method according to
    claim 7
    .
  15. 15. A method for reusing a delaminated wafer produced as a by-product in the method according to
    claim 1
    as a silicon wafer after reprocessing it.
  16. 16. A method for reusing a delaminated wafer produced as a by-product in the method according to
    claim 2
    as a silicon wafer after reprocessing it.
  17. 17. A method for reusing a delaminated wafer produced as a by-product in the method according to
    claim 3
    as a silicon wafer after reprocessing it.
  18. 18. A method for reusing a delaminated wafer produced as a by-product in the method according to
    claim 5
    as a silicon wafer after reprocessing it.
  19. 19. A thick layer SOI wafer fabricated by growing an epitaxial layer on an SOI layer wherein a damage layer is present in the SOI layer under the epitaxial layer.
US09906873 1998-07-07 2001-07-16 Method of fabricating an SOI wafer and SOI wafer fabricated by the method Abandoned US20010046746A1 (en)

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US09906873 US20010046746A1 (en) 1998-07-07 2001-07-16 Method of fabricating an SOI wafer and SOI wafer fabricated by the method

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