JP2004265904A - Soi wafer and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an SOI wafer in which the insulating property of an interlayer insulating oxide film is maintained at a high level even when the film is formed to have an extremely thin thickness of, for example, ≤100 nm and which is high in electrical reliability in a device manufacturing process. <P>SOLUTION: This SOI wafer on which an active silicon layer 27 is formed is manufactured by reducing the thickness of a bond wafer 21 composed of a single silicon crystal after the wafer 21 is stuck to a base wafer 22 also composed of a single silicon crystal through an oxide film 23. The single silicon crystal forming the base wafer 22 is grown by the Czochralski method, and the whole surface of the wafer 22 is in an N region on the outside of an OSF region and does not contain the defective region detected by the Cu deposition method. It is preferable that the base wafer 22 is formed by the ion-implanting peeling method, and the bond wafer 21 forming the active silicon layer 27 is also composed of a similar single silicon crystal. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an SOI wafer, and particularly to a high-quality SOI wafer having extremely high electrical reliability and a method for manufacturing the same.
[0002]
[Prior art]
Conventionally, as a device substrate, an SOI wafer having a silicon active layer (SOI layer) formed on a supporting substrate has been widely used. As a method for manufacturing such an SOI wafer, for example, a so-called bonding method in which two silicon wafers are bonded to each other with an oxide film interposed therebetween is known.
[0003]
In the ion implantation delamination method, which is one of the bonding methods, an oxide film (buried oxide film, interlayer) is formed as an insulating layer on the surface of a silicon wafer (bond wafer) serving as a silicon active layer or a silicon wafer (base wafer) serving as a support substrate. Then, ions such as hydrogen are ion-implanted from one surface of the bond wafer to form an ion-implanted layer (microbubble layer) inside the wafer. Further, the surface of the bond wafer on the side where the ions are implanted is bonded to the base wafer via an oxide film, and then separated by heat treatment with the ion implanted layer as a boundary. As a result, an SOI wafer having a thin silicon active layer formed on a base wafer via an oxide film can be obtained. After peeling, heat treatment (bonding heat treatment) for increasing the bonding force between the silicon active layer and the base wafer, or hydrofluoric acid cleaning for removing an oxide film on the surface may be performed.
[0004]
In general, a silicon single crystal grown by the Czochralski method (CZ method) can be used as a silicon wafer used for manufacturing such an SOI wafer. In recent years, however, a silicon active layer or a buried oxide film has been used. Demands for thinning of silicon wafers are increasing, and quality requirements for silicon wafers to be used are becoming stricter.
In particular, for a bond wafer to be a silicon active layer, it has been proposed to grow a silicon single crystal with few defects and use a high-quality silicon wafer obtained therefrom.
[0005]
Here, the relationship between the pulling speed when growing a silicon single crystal by the Czochralski method and defects in the grown silicon single crystal will be described.
When the growth rate V is changed from high to low in the crystal axis direction by a CZ puller using a furnace internal structure (hot zone: HZ) having a large temperature gradient G near the solid-liquid interface in a normal crystal, FIG. It is known that a defect distribution diagram as shown can be obtained.
[0006]
In FIG. 9, the V region is a region where there are many vacancies, that is, depressions and holes generated due to lack of silicon atoms, and the I region is an interstitial silicon which is an extra silicon atom. This is a region where there are many dislocations and excessive lump of silicon atoms caused by the existence. A neutral (neutral, hereinafter abbreviated as N) region exists in which there is no (small) lack or excess of atoms between the V region and the I region, and an OSF is located near the boundary of the V region. It has also been confirmed that a defect called (Oxidation-Induced Stacking Fault) is distributed in a ring shape (hereinafter sometimes referred to as an OSF ring) when viewed in a cross section perpendicular to the crystal growth axis. ing.
[0007]
When the growth rate is relatively high, grown-in defects such as FPDs, LSTDs, and COPs, which are attributed to voids in which vacancy-type point defects are aggregated, exist at high density throughout the crystal diameter direction. The region where the defect exists is the V region. Further, as the growth rate decreases, an OSF ring is generated from the periphery of the crystal, an N region is generated outside the ring (low-speed side), and when the growth rate is reduced, the OSF ring is located at the center of the wafer. It contracts and disappears, and the entire surface becomes an N region. If the speed is further reduced, defects (large dislocation clusters) of L / D (Large Dislocation: abbreviation of interstitial dislocation loop, LSEPD, LFPD, etc.), which are considered to be caused by dislocation loops in which interstitial silicon is gathered, exist at low density. However, an area where these defects exist is an I area (also referred to as an L / D area).
[0008]
The N region outside the OSF ring between the V region and the I region is a region where neither FPD, LSTD, or COP due to vacancies nor LSEPD or LFPD due to interstitial silicon exists. Recently, when the N region is further classified, as shown in FIG. 9, an Nv region (a region with many holes) adjacent to the outside of the OSF ring and a Ni region (interstitial silicon) adjacent to the I region It is known that in the Nv region, a large amount of oxygen precipitates when subjected to thermal oxidation treatment, and in the Ni region, there is almost no oxygen precipitation.
[0009]
Conventionally, such an N region was only partially present in the wafer plane, but it is necessary to control V / G, which is the ratio of the pulling speed (V) to the temperature gradient (G) in the crystal-solid interface axial direction. As shown in FIG. 9, it is possible to manufacture a crystal in which the N region spreads over the entire lateral side (entire wafer).
Therefore, in the production of SOI wafers, there has been proposed a method of using a silicon single crystal wafer which is an entire N region as a bond wafer. For example, when pulling a silicon single crystal by the Czochralski method, the ratio (V / G) between the pulling speed V and the temperature gradient G of the crystal solid-liquid interface in the pulling axis direction is controlled within a predetermined range to control the silicon single crystal. An SOI wafer has been proposed in which a crystal is pulled up and a silicon wafer in an N region is used as a bond wafer (for example, see Patent Documents 1 and 2).
[0010]
On the other hand, the base wafer is originally necessary to support the SOI layer via the insulating film, and the device is not directly formed on the surface thereof. Therefore, it has been proposed to use a dummy-grade silicon wafer whose resistance value or the like is out of the product standard as a base wafer (see Patent Document 3).
[0011]
Generally, the base wafer partially includes a V region grown at a high pulling speed, or an OSF region or an Nv region as shown in FIG. 9 in consideration of the improvement of quality and productivity, and the like. A silicon wafer obtained by growing a silicon single crystal of a certain degree and processing the silicon single crystal thus grown at a high speed into a mirror-like shape is widely used.
[0012]
[Patent Document 1]
JP 2001-146498 A (pages 5-8)
[Patent Document 2]
JP 2001-44398 A (pages 2-4, FIG. 1)
[Patent Document 3]
JP-A-11-40786
[Problems to be solved by the invention]
On the surface and in the bulk of the silicon wafer obtained from the silicon single crystal grown at high speed as described above, vacancy defects such as COPs in which vacancies are gathered are formed at a high density, and the surface has a size of 50 nm or more. There are many small pit defects. When an SOI wafer is manufactured using a silicon wafer having a large number of such minute pit defects as a base wafer, particularly when the thickness of an insulating oxide film required in recent years is formed to be thin, a high insulating property is obtained. If not maintained, the problem that electrical reliability is impaired has arisen.
[0014]
Accordingly, the present invention has been made in view of such a problem, and even when the thickness of an interlayer insulating oxide film is extremely thin as, for example, 100 nm or less, high insulation is maintained, and a device manufacturing process is performed. It is an object of the present invention to provide an SOI wafer having high electrical reliability in the above.
[0015]
[Means for Solving the Problems]
In order to achieve the above object, according to the present invention, a silicon active layer is formed by laminating a base wafer and a bond wafer each made of a silicon single crystal via an oxide film and then thinning the bond wafer. The formed SOI wafer, wherein the base wafer is a silicon single crystal grown by the Czochralski method, the entire surface of the wafer is an N region outside the OSF region, and is detected by the Cu deposition method. An SOI wafer is provided which does not include a defective region (claim 1).
[0016]
As described above, if the entire surface of the base wafer is the N region outside the OSF region, and the SOI wafer is made of a CZ silicon single crystal that does not include a defect region detected by the Cu deposition method, the surface of the base wafer has a very small size. Since there is no defect, even if the thickness of the insulating oxide film on the base wafer is as thin as, for example, less than 100 nm, the dielectric breakdown characteristics do not deteriorate due to the influence of the defect on the surface of the base wafer, and the SOI wafer with extremely high thermal reliability.
[0017]
In this case, it is preferable that the SOI wafer is formed by an ion implantation separation method in which ion implantation is performed on the bond wafer and the bond wafer is peeled off by the formed ion implantation layer to make the bond wafer thinner ( Claim 2).
As a bonding method, after bonding the bond wafer and the base wafer, the bond wafer may be thinned by grinding and polishing to obtain an SOI wafer, but in this case, the thickness of the SOI layer is relatively thick. . On the other hand, according to the ion implantation delamination method, the depth of the ion implantation layer, that is, the thickness of the SOI layer can be set to an extremely thin level required in recent years, and an extremely high quality SOI wafer can be obtained.
[0018]
The thickness of the oxide film may be in the range of 10 to 100 nm (claim 3).
In recent years, it has been required that the thickness of the interlayer insulating oxide film be, for example, about 50 nm. However, the SOI wafer of the present invention has deteriorated dielectric breakdown characteristics even if such an extremely thin oxide film is formed. And high insulation is maintained.
[0019]
Further, the silicon active layer is a single crystal of silicon grown by the Czochralski method, is an N region outside the OSF region over the entire surface, and does not include a defect region detected by the Cu deposition method. (Claim 4).
As described above, if the entire silicon active layer is the N region outside the OSF region and is made of CZ silicon single crystal that does not include the defect region detected by the Cu deposition method, a defect is formed in the device formation region. An extremely high-quality SOI wafer is obtained in which the silicon active layer and the buried oxide film are not destroyed due to defects in the silicon active layer even if the cleaning with hydrofluoric acid is performed.
[0020]
Further, according to the present invention, there is also provided a method for manufacturing an SOI wafer as described above. That is, at least a step of forming an oxide film on at least one of a base wafer and a bond wafer each made of a silicon single crystal, a step of forming an ion-implanted layer by ion-implanting the bond wafer, In a method for manufacturing an SOI wafer, the method further comprises: a step of bonding the implanted surface to a base wafer via the oxide film; and a step of performing stripping using the ion-implanted layer as a boundary. A silicon single crystal grown by a method, wherein the entire surface of the wafer is an N region on the lower side than the ring-shaped OSF region when the pulling speed is gradually reduced from a high speed to a low speed during the growth, and It is necessary to use the one that does not include the defect area detected by the Cu deposition method. Method for manufacturing an SOI wafer is provided that the symptoms (claim 5).
[0021]
When manufacturing a SOI wafer by the ion implantation delamination method, if a CZ silicon single crystal wafer whose entire surface is defect-free as described above is used as the base wafer, even if the interlayer insulating oxide film is formed to a thickness of less than 100 nm. Even when the bonding heat treatment or the like is performed, the dielectric breakdown characteristics of the oxide film are not deteriorated due to defects existing in the base wafer, and a high-quality SOI wafer with high electrical reliability is manufactured. be able to.
[0022]
In this case, the bond wafer is a silicon single crystal grown by the Czochralski method, and the entire surface of the wafer is formed in an OSF region which is formed in a ring shape when the pulling speed is gradually reduced from a high speed to a low speed during the growth. It is preferable to use an N region on the lower speed side which does not include a defect region detected by the Cu deposition method.
As described above, if the SOI wafer is manufactured using a defect-free bond wafer similarly to the base wafer, the device formed on the SOI layer will not be adversely affected, and the dielectric breakdown characteristics of the interlayer oxide film will not be affected. An extremely high-quality SOI wafer that can reliably prevent deterioration can be manufactured.
[0023]
Recently, when an SOI wafer is manufactured by an ion implantation separation method, a method has been proposed in which a separated bond wafer (peeled wafer) is subjected to a reclaiming treatment and reused as a base wafer (or a bond wafer) (for example, Japanese Patent Laid-Open Publication No. H11-163873). See Japanese Unexamined Patent Publication No. 11-297584. Therefore, if a defect-free bond wafer as described above is used, and then the peeled wafer is reprocessed and reused as a base wafer, a high-quality SOI wafer can be manufactured with a low manufacturing cost.
[0024]
Hereinafter, the present invention will be described in more detail.
The present inventors have conducted a detailed investigation on the influence of a base wafer of an SOI wafer by a bonding method on a buried oxide film. As a result, when an SOI wafer is manufactured using a high-speed grown silicon single crystal generally used in the past, that is, a silicon wafer having a large number of minute defects of 50 nm or more on the surface, an insulating oxide film is formed. When the film has a sufficient thickness of several hundred nm or more, problems such as deterioration of the dielectric breakdown characteristics due to the influence of the base wafer hardly occur. However, when the film is thinner than 100 nm, the base wafer does not. It has been found that there is a possibility that a failure may occur in maintaining the insulation property due to the influence of. In particular, when a 50 nm level buried oxide film, which has recently been required, is used, a conventional V-rich base wafer affects the interlayer insulating oxide film during bonding heat treatment or the like, and cannot maintain high insulating properties. It has been found that the possibility of impairing the reliability is extremely high.
[0025]
Therefore, the present inventors have made it possible to reduce the microdefects of the base wafer to obtain an SOI wafer with high electrical reliability in which the dielectric breakdown characteristics do not deteriorate even when the insulating oxide film is formed to 100 nm or less. We thought that it could be done and conducted the following investigation and examination.
First, when pulling up a silicon single crystal, when the growth rate is gradually reduced from a high speed to a low speed from the crystal shoulder to the straight tail, as described above, the OSF shrinks when a certain growth rate is reached. , Ni, and I (giant dislocation cluster generation) regions are known to be formed in this order. Recently, as shown in FIG. 2, a part of the Nv region in which a defect is detected by the Cu deposition method immediately after the disappearance of the OSF (hereinafter, may be referred to as a Cu deposition defect region) partially exists. (See, for example, JP-A-2002-201093).
[0026]
The Cu deposition method is a method of accurately measuring the position of a defect on a semiconductor wafer, improving the detection limit for defects on the semiconductor wafer, and accurately measuring and analyzing even finer defects. Is the law.
A specific method for evaluating a wafer is to form an insulating film of a predetermined thickness on the surface of a wafer, break the insulating film on a defective portion formed near the surface of the wafer, and electrolytically deposit Cu or the like on the defective portion. A substance is deposited (deposition). That is, in the Cu deposition method, when a potential is applied to an oxide film formed on the wafer surface in a liquid in which Cu ions are dissolved, a current flows to a portion where the oxide film is deteriorated, and the Cu ions become Cu. This is an evaluation method utilizing precipitation. It is known that a defect such as COP exists in a portion where the oxide film easily deteriorates.
[0027]
The defect site of the Cu-deposited wafer can be analyzed under a condensing light or directly with the naked eye to evaluate its distribution and density. Further, it can be observed with a microscope, a transmission electron microscope (TEM), or a transmission electron microscope (TEM). It can also be confirmed by a scanning electron microscope (SEM; Scanning Electron Microscope) or the like.
[0028]
The present inventors have further investigated defects in these regions.
More specifically, when the silicon single crystal growth is gradually reduced from a high speed to a low speed, the V region immediately before the OSF disappearance is identified by coordinates using a surface inspection device (MAGICS; trade name), and then a focused ion beam (FIB) process is performed. , And TEM observation of that point confirmed the presence of a minute pit defect of about 20 nm. In the V region, the void becomes finer in the region immediately before the disappearance of the OSF. Even if the minute pit defects in the V region are considerably fine, the initial oxide film breakdown voltage (TZDB: Time Zero Dielectric Breakdown) characteristic is significantly deteriorated. Let it.
[0029]
On the other hand, when the silicon single crystal growth gradually decreases from the high speed to the low speed, in the Cu deposition defect region immediately after OSF disappearance, there is no remarkable deterioration of the breakdown voltage level as in the V region, and the TZDB characteristic is almost 100% in-plane. Although a C mode was exhibited in the region, a slight deterioration was observed in the time-dependent dielectric breakdown (TDDB; Time Dependent Dielectric Breakdown) characteristics.
[0030]
As a result of such investigations and studies, as the thickness of the interlayer insulating oxide film required for some devices has recently been reduced, the bond wafer, that is, the silicon active layer has been used in the conventional V region or OSF. In addition to the case where a silicon single crystal wafer having a Cu deposition defect region also exists in a region or an N region, even when such a silicon wafer is used as a base wafer, it becomes an obstacle to the insulating property of an oxide film, and electrical characteristics It was found that a defect according to the above could occur.
In addition, vacancy-type defects existing in these regions may cause deterioration of the quality of the insulating oxide film during the bonding heat treatment. Particularly, in the case of a thin film whose film thickness is less than 100 nm, excellent insulating properties are obtained. It has been found that it is not possible to maintain the reliability, causing an electrical failure and significantly impairing the reliability.
[0031]
In order to avoid such an electrical failure, the present inventors consider that the base wafer of the SOI wafer is a mirror surface wafer of the N region having no defect region detected by the Cu deposition method. It has been found that even if the thickness of the SOI wafer is 100 nm or less, an SOI wafer having excellent electrical characteristics can be obtained, and the present invention has been completed.
[0032]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be specifically described with reference to the accompanying drawings, but the present invention is not limited thereto.
FIG. 1 is a flowchart showing an example of a process for manufacturing an SOI wafer according to the present invention by an ion implantation delamination method.
First, in the first step (a), two silicon mirror-finished wafers, that is, a bond wafer 21 serving as an SOI layer and a base wafer 22 serving as a support substrate are prepared. Here, in the present invention, as the base wafer 22, when the lifting speed is gradually reduced from a high speed to a low speed during the growth by the Czochralski method, the entire surface of the wafer is N wafer on the lower speed side than the OSF region generated in a ring shape. A silicon wafer which is a region and does not include a defect region detected by the Cu deposition method is used.
[0033]
The silicon single crystal in the above-described N region without the Cu deposition defect region is grown using, for example, a single crystal manufacturing apparatus 30 as shown in FIG. 3 while controlling V / G. Can be. The single crystal pulling apparatus 30 includes a pulling chamber 31, a crucible 32 provided in the pulling chamber 31, a heater 34 disposed around the crucible 32, a crucible holding shaft 33 for rotating the crucible 32, and a rotating mechanism thereof. (Not shown), a seed chuck 6 for holding a silicon seed crystal, a wire 7 for pulling up the seed chuck 6, and a winding mechanism (not shown) for rotating or winding the wire 7. Further, a heat insulating material 35 is arranged around the outside of the heater 34.
[0034]
The crucible 32 is provided with a quartz crucible on the side for containing the silicon melt (hot water) 2 inside, and a graphite crucible on the outside thereof.
Recently, a magnet (not shown) is installed outside the pulling chamber 31 in the horizontal direction, and a magnetic field in a horizontal direction or a vertical direction is applied to the silicon melt 2 so as to suppress the convection of the melt. In many cases, a so-called MCZ method is used to achieve stable growth.
[0035]
A cylindrical graphite tube (heat shield plate) 12 is provided so as to surround the grown silicon single crystal 1, and an annular outer heat insulating material 10 is provided on the outer periphery near the solid-liquid interface 4 of the crystal. . In some cases, an inner heat insulating material may be provided inside the graphite cylinder 12. Such a heat insulating material 10 is provided with a space of 2 to 20 cm between its lower end and the molten metal surface 3 of the silicon melt 2. By doing so, the difference between the temperature gradient Gc [° C./cm] at the center of the crystal and the temperature gradient Ge at the periphery of the crystal becomes small. For example, the furnace temperature is set so that the temperature gradient around the crystal becomes lower than the crystal center. Can also be controlled.
In addition, a cooling cylinder 14 is provided above the graphite cylinder 12 to flow a cooling medium for forced cooling. Further, a cylindrical cooling means for cooling the single crystal by spraying a cooling gas or blocking radiant heat may be provided.
[0036]
In order to manufacture a silicon single crystal using such a single crystal pulling apparatus 30, first, a high-purity polycrystalline silicon raw material is heated in a crucible 32 to a melting point (about 1420 ° C.) or higher and melted. Next, by unwinding the wire 7, the tip of the seed crystal is brought into contact with or immersed in the approximate center of the surface of the melt 2. Thereafter, the crucible holding shaft 33 is rotated and the wire 7 is wound while being rotated. Thus, the seed crystal is also pulled while rotating, and the growth of the single crystal is started. Thereafter, by appropriately adjusting the pulling speed and the temperature, it is possible to obtain the substantially columnar single crystal rod 1.
[0037]
In order to grow a silicon single crystal that is an N region and does not include a Cu deposition defect region, for example, when the growth rate (pulling rate) of the silicon single crystal during pulling is gradually reduced from a high speed to a low speed. The growth rate at the boundary where the defect region detected by the Cu deposition method, which remains after the ring-shaped OSF region has disappeared, and the boundary at which the interstitial dislocation loop occurs when the growth rate is gradually reduced. The crystal is grown by controlling the growth rate between the growth rate and the growth rate.
[0038]
That is, when the growth rate of the silicon single crystal during pulling is gradually reduced from a high speed to a low speed from the crystal shoulder to the straight tail, as shown in FIG. 2, the V region, the OSF ring region, Each phase is formed in the order of a Cu deposition defect region, an Nv region, a Ni region, and an I region (a giant dislocation cluster generation region). Among the N regions, defects detected by Cu deposition remaining after the OSF ring disappears. The single crystal is grown by controlling the growth rate between the growth rate at the boundary where the region disappears and the growth speed at which the I region occurs when the growth speed is further reduced. According to such a method, an N region which does not include a V region defect such as an FPD, an I region defect such as a giant dislocation cluster (LSEPD, LFPD), an OSF defect, and has no defect detected by the Cu deposition method. A silicon single crystal can be grown.
[0039]
Then, after processing the silicon single crystal grown as described above into a mirror-polished wafer (PW), PW is arbitrarily extracted from a unit lot for each ingot block, and is evaluated by a Cu deposition method. If it is free, it may be adopted as the base wafer 22.
[0040]
The bond wafer 21 may have a quality corresponding to the quality required for the silicon active layer. However, the bond wafer 21 is similar to the base wafer 22, that is, the entire surface of the wafer is formed in a ring shape. If an N region which is lower in speed than the OSF region and does not include a defect region detected by the Cu deposition method is used, a micro defect does not exist in the silicon active layer. And even if the interlayer insulating oxide film is formed to a thickness of about 50 nm, it is possible to reliably prevent the dielectric breakdown characteristics from being degraded by the influence of the base wafer in the subsequent bonding heat treatment and the like. The reliability can be made extremely high.
Furthermore, if the same bond wafer 21 as the base wafer 22 is used, and the peeled bond wafer is recycled and reused as described later, an SOI wafer with high electrical reliability can be manufactured at low cost. It becomes possible.
[0041]
Next, in step (b) of FIG. 1, the surface of at least one of the bond wafer 21 and the base wafer 22 is oxidized. Here, the bond wafer 21 is thermally oxidized to form an oxide film 23 on the surface thereof. At this time, the oxide film 23 has a thickness that maintains required insulation properties. In the present invention, an extremely thin oxide film having a thickness in the range of 10 to 100 nm can be formed.
[0042]
When a SOI wafer is manufactured by using a conventionally used silicon wafer having a large number of minute defects of, for example, 50 nm or more on its surface and setting the thickness of the buried oxide film to 100 nm or less as the base wafer, the oxide film is formed of the base wafer. Due to the influence of minute defects existing on the surface, there is a possibility that it will be degraded or destroyed by a subsequent bonding heat treatment or heat treatment in a device process. However, since the base wafer 22 of the present invention does not have any extremely minute defects existing in the Cu deposition defect region, even if the thickness of the oxide film 23 is set to 100 nm or less, a problem such as deterioration of dielectric breakdown characteristics may occur. There is no.
If the thickness of the oxide film 23 is less than 10 nm, it takes less time to form the oxide film, but the insulating property may not be maintained. Therefore, the thickness is preferably 10 nm or more.
[0043]
In the step (c), hydrogen ions are implanted from one surface of the bond wafer 21 having the oxide film 23 formed on the surface. Note that rare gas ions or mixed gas ions of hydrogen ions and rare gas ions may be implanted. As a result, an ion-implanted layer parallel to the surface at the average depth of penetration of ions can be formed inside the wafer. Note that the depth of the ion implantation layer at this time is reflected in the thickness of the finally formed SOI layer. Therefore, the thickness of the SOI layer can be controlled by performing ion implantation while controlling the implantation energy and the like. For example, the SOI layer can have a thickness of 200 nm or less.
[0044]
In the step (d), the surface of the bond wafer 21 on the ion-implanted side and the surface of the base wafer 22 are bonded via the oxide film 23. For example, by bringing the surfaces of two wafers 21 and 22 into contact with each other in a clean atmosphere at normal temperature, the wafers are bonded to each other without using an adhesive or the like.
[0045]
Next, in the step (e), a part of the bond wafer 21 is peeled off by the ion implantation layer 24 by heat treatment. For example, if the bonded wafer 21 and the base wafer 22 are bonded to each other and subjected to a heat treatment at a temperature of about 500 ° C. or more in an inert gas atmosphere, the separated wafer 25 may be rearranged due to crystal rearrangement and agglomeration of bubbles. And an SOI wafer 26 (SOI layer 27 + buried oxide film 23 + base wafer 22).
[0046]
Here, a method has recently been proposed in which the by-produced peeling wafer 25 is subjected to a regenerating process such as polishing on the peeling surface and reused as a base wafer or a bond wafer. As described above, since the bond wafer 21 is also a silicon wafer which is an N region and does not include a Cu deposition defect region, like the base wafer 22, the silicon wafer obtained by regenerating the peeled wafer 25 is used. Wafers can be used for both base wafers and bond wafers. Therefore, a similar high-quality SOI wafer can be manufactured by reusing the peeled wafer 25 as, for example, the base wafer 22. That is, the SOI wafer according to the present invention is manufactured from substantially one silicon wafer, and the manufacturing cost can be reduced.
[0047]
In the step (f), a bonding heat treatment is applied to the SOI wafer 26. In this step (f), since the bonding force between the wafers brought into close contact with each other in the bonding step and the peeling heat treatment step in the steps (d) and (e) is weak to be used in the device fabrication step as it is, the bonding heat treatment is used. The SOI wafer 26 is subjected to a high-temperature heat treatment so that the bonding strength is sufficient. For example, this heat treatment can be performed at 1050 ° C. to 1200 ° C. for 30 minutes to 2 hours in an inert gas atmosphere.
Even if such a high-temperature heat treatment is performed, since the entire surface of the base wafer 22 is defect-free, the dielectric breakdown characteristics of the buried oxide film 23 are not deteriorated, and the high insulating property can be maintained.
[0048]
In the step (g), the oxide film formed on the surface of the SOI wafer 26 is removed by hydrofluoric acid cleaning. At this time, if a vacancy-type defect exists in the silicon active layer 27, HF may reach the buried oxide film through the defect and a minute pit may be generated. However, in the present invention, the silicon active layer 27 is formed over the entire surface. Since it is composed of a silicon single crystal which is an N region and does not include a defect region detected by the Cu deposition method, the pits are enlarged even if the cleaning with hydrofluoric acid is performed, and the SOI layer 27 and the buried oxide film 23 become There is no destruction.
[0049]
Further, in the step (h), if necessary, oxidation for adjusting the thickness of the SOI layer 27 is performed, and then, in the step (I), so-called sacrificial oxidation for removing the oxide film 28 by hydrofluoric acid cleaning is performed.
In the SOI wafer manufactured through the steps (a) to (I) as described above, the entire surface of the base wafer 22 and the SOI layer 27 is also the N region outside the OSF region, and is detected by the Cu deposition method. Although the buried oxide film 23 is extremely thin, the insulation is maintained and the electrical reliability is extremely high even though the buried oxide film 23 is extremely thin.
[0050]
【Example】
Hereinafter, the present invention will be described with reference to Examples, but the present invention is not limited thereto.
(Experiment 1): Confirmation of Pulling Conditions Using the single crystal manufacturing apparatus 30 shown in FIG. 3, an experiment for gradually decreasing the crystal growth rate was performed as described below, and the growth rate at the boundary of each region was examined.
First, a silicon crucible having a diameter of 210 mm was grown by charging 150 kg of polycrystalline silicon as a raw material into a 24-inch (600 mm) diameter quartz crucible. The oxygen concentration was adjusted to 23 to 26 ppma (ASTM '79 value). When growing a single crystal, as shown in FIG. 4 (A), the growth rate was controlled so as to gradually decrease linearly from 0.70 mm / min to 0.30 mm / min from the head to the tail of the crystal. .
[0051]
Then, as shown in FIGS. 4 (A) and 4 (B), the pulled single crystal was vertically cut in the crystal axis direction from the head to the tail, and then a mirror-finished sample in the form of a wafer having a diameter of 200 mm was produced.
One of the samples was subjected to wafer lifetime (WLT) measurement after oxygen precipitation heat treatment (measurement device: SEMILAB WT-85), and the distribution state of each region of V region, OSF region, and I region and the growth rate of each region boundary. It was confirmed. The other was subjected to a Cu deposition process after the formation of the thermal oxide film, and the distribution of oxide film defects was confirmed. In addition, the detailed evaluation method in this experiment is as follows.
[0052]
(A) An ingot having a diameter of 210 mm is cut into blocks each having a length of 10 cm in the crystal axis direction, and then vertically cut in the crystal axis direction. Thereafter, as shown in FIG. 5, a diameter of 200 mm is perpendicular to the crystal axis ( 8 inch) wafer-shaped mirror-finished sample.
(B) The first sample of the above samples was subjected to heat treatment at 620 ° C. for 2 hours (nitrogen atmosphere) in a wafer heat treatment furnace, followed by 800 ° C. for 4 hours (nitrogen atmosphere) and 1000 ° C. for 16 hours (dry oxygen atmosphere). After performing the step heat treatment, cooling was performed, and a WLT map by SEMILAB WT-85 was created.
(C) The second wafer was subjected to Cu deposition processing after forming a thermal oxide film on the wafer surface, and the distribution of oxide film defects was confirmed. The evaluation conditions are as follows.
1) Oxide film: 25 nm
2) Electrolytic strength: 6 MV / cm
3) Voltage application time: 5 minutes
Experimental Results From the above experiments, results as shown in FIGS. 6A and 6B were obtained, and the growth rates at the boundaries of the V region, OSF region, N region, and I region were confirmed.
V region / OSF region boundary: 0.523 mm / min
OSF disappearance boundary: 0.510 mm / min
Cu deposition defect disappearance boundary: 0.506 mm / min
Precipitation N region / non-precipitation N region boundary: 0.497 mm / min
Non-precipitation N region / I region boundary: 0.488 mm / min
[0054]
(Experiment 2): Manufacture of SOI wafer Using the same pulling apparatus as in Experiment 1 shown in FIG. 3, 150 kg of raw material polycrystalline silicon was charged into a 24-inch quartz crucible, and then the growth rate was reduced to 0. In the range of 55 mm / min to 0.45 mm / min, the ingot having a diameter of 210 mm gradually decreased gradually from the head to the tail of the ingot from Experiment 1, and N containing Cu deposition defects in the region from 40 cm to 70 cm of the crystal straight body. Control was performed so that a region and an N region containing no Cu deposition defect were formed. Moreover, it produced so that oxygen concentration might be 24-26 ppma (ASTM'79). Then, quality evaluation and SOI processing were performed according to the following procedures.
[0055]
(1) After the crystal was pulled, the wafer was cut in order from the head side in the crystal axis direction of each crystal block, a number was printed by laser marking so that the cutting order could be understood, and the wafer was processed into a mirror-finished wafer.
[0056]
(2) The first PW on the head side in each block was divided into quarters, and FPD, LFPD, LSEP, and OSF were examined. Next, the Cu deposition defect distribution was confirmed on the head side second sheet of each block unit. Then, a total of five sheets from the head side third to seventh sheets in each block unit were put into the SOI wafer manufacturing process (SOI process). Again, the head-side eighth sheet is evaluated for FPD, LFPD, LSEP, and OSF, and the ninth sheet is subjected to the Cu deposition defect distribution, and the tenth to fourteenth sheets are fed into the SOI process in total of five sheets. The quality of two head-side wafers in units of seven wafers in the crystal axis direction was evaluated, and the remaining five wafers were processed into SOI wafers.
[0057]
(3) As a result of the above evaluation, the V region and the OSF region extend from the middle of the block of about 40 cm to 50 cm in the crystal body, and the N region and the crystal structure have Cu deposition defects up to about 50 cm in the crystal body. The N region where the Cu deposition defect did not occur from about 50 cm to about 70 cm of the body, and the I area was from about 70 cm of the crystal body to the tail side.
[0058]
(4) The mirror wafers of the lot of each of the above-mentioned (1) are used for the bond wafer and the base wafer, and the ion implantation into the bond wafer and the base wafer are performed by the ion implantation separation method based on the process shown in FIG. , An SOI wafer having an insulating oxide film having a thickness of 70 nm and a silicon active layer having a thickness of 200 nm was manufactured through a bonding heat treatment, a peeling heat treatment, a bonding heat treatment (bonding oxidation), and the like.
The active layer of the SOI wafer manufactured as described above was selectively etched with a potassium hydroxide solution and removed. Next, the base wafer having the remaining insulating oxide film layer was evaluated by the Cu deposition method at an electrolytic strength of 6 MV / cm.
[0059]
As a result, in the case of the insulating oxide film after the bonding oxidation, the breakdown of the oxide film was confirmed in the V region, the OSF region, and the base wafer in the N region where the Cu deposition defect occurs. Oxide film destruction did not occur on the base wafer in the N region that did not include the deposition defect region.
[0060]
Note that the present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and has substantially the same configuration as the technical idea described in the claims of the present invention, and any device having the same operation and effect can be realized by the present invention. It is included in the technical scope of the invention.
[0061]
For example, in the embodiment, the case where the SOI wafer is manufactured by the ion implantation delamination method using two silicon wafers has been described. The invention can also be applied to SOI wafers that are manufactured by being converted.
[0062]
【The invention's effect】
As described above, according to the present invention, there is provided an SOI wafer having the entire surface of the base wafer in the N region and not including the defect region detected by the Cu deposition method. With such an SOI wafer, even if the thickness of the buried oxide film is 100 nm or less, excellent insulating characteristics are maintained. It can be manufactured with a yield.
[Brief description of the drawings]
FIG. 1 is a flowchart showing an example of a manufacturing process of an SOI wafer according to the present invention.
FIG. 2 is an explanatory diagram showing a crystal region used when manufacturing an SOI wafer according to the present invention.
FIG. 3 is an example of a CZ silicon single crystal manufacturing apparatus that can be used in the present invention.
FIG. 4A is a relationship diagram showing a relationship between a single crystal growth rate and a crystal cutting position.
(B) It is explanatory drawing which shows a growth rate and each area | region.
FIG. 5 is an explanatory diagram showing a method for producing a Cu deposition evaluation sample.
FIG. 6 is a view showing (A) a wafer lifetime and (B) a Cu deposition defect in a crystal vertical section.
FIG. 7 is a diagram showing a growth rate and a crystal cutting position in Experiment 2.
FIG. 8 is a view showing a defect distribution of each crystal region by a Cu deposition method.
(A) V region (B) N region (Cu deposition defect occurrence)
(C) N region (no Cu deposition defect)
FIG. 9 is an explanatory diagram illustrating a crystal region.
[Explanation of symbols]
1 ... grown single crystal rod, 2 ... silicon melt, 3 ... hot water surface, 4 ... solid-liquid interface,
6 ... seed chuck, 7 ... wire, 10 ... outer heat insulator, 12 ... graphite cylinder,
21: Bond wafer, 22: Base wafer,
23: oxide film (insulating layer), 24: ion implantation layer, 25: release wafer,
26: SOI wafer, 27: silicon active layer (SOI layer),
28: oxide film, 30: single crystal pulling device, 31: pulling chamber,
32: crucible, 33: crucible holding shaft, 34: heater, 35: heat insulating material.

Claims (6)

An SOI wafer having a silicon active layer formed by bonding a base wafer and a bond wafer each made of a silicon single crystal via an oxide film, and then thinning the bond wafer, wherein the base wafer is A silicon single crystal grown by the Czochralski method, wherein the entire surface of the wafer is an N region outside the OSF region and does not include a defect region detected by the Cu deposition method. SOI wafer. The SOI wafer is formed by an ion implantation and stripping method in which the bond wafer is ion-implanted and separated by an ion-implanted layer formed to reduce the thickness of the bond wafer. Item 2. The SOI wafer according to Item 1. 3. The SOI wafer according to claim 1, wherein the thickness of the oxide film is in a range of 10 to 100 nm. 4. The silicon active layer is a single crystal of silicon grown by the Czochralski method, the entire surface is an N region outside the OSF region, and does not include a defect region detected by the Cu deposition method. The SOI wafer according to any one of claims 1 to 3, wherein: At least, a step of forming an oxide film on at least one of a base wafer and a bond wafer each made of a silicon single crystal, a step of forming an ion-implanted layer by ion-implanting the bond wafer, and an ion-implantation of the bond wafer. Bonding the side surface to a base wafer via the oxide film, and performing a peeling process using the ion-implanted layer as a boundary. In the method for manufacturing an SOI wafer, the Czochralski method is used as the base wafer. A grown silicon single crystal, the entire surface of the wafer being an N region on the lower side than the ring-shaped OSF region when the pulling speed is gradually reduced from a high speed to a low speed during the growth, and Characterized by using no defect area detected by the position method Manufacturing method of OI wafer. The bond wafer is a silicon single crystal grown by the Czochralski method, and the entire surface of the wafer is slower than the ring-shaped OSF region when the pulling speed is gradually reduced from high speed to low speed during growth. 6. The method for manufacturing an SOI wafer according to claim 5, wherein an N region on the side and not including a defect region detected by a Cu deposition method is used.

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