CN100452407C

CN100452407C - SOI wafer and production method therefor

Info

Publication number: CN100452407C
Application number: CNB2004800018809A
Authority: CN
Inventors: 樱田昌弘; 三田村伸晃; 布施川泉
Original assignee: Shin Etsu Handotai Co Ltd
Current assignee: Shin Etsu Handotai Co Ltd
Priority date: 2003-01-23
Filing date: 2004-01-22
Publication date: 2009-01-14
Anticipated expiration: 2024-01-22
Also published as: CN1723563A; JP2004265904A

Abstract

An SOI wafer in which a base wafer and a bond wafer respectively consisting of silicon single crystal are bonded via an oxide film, and then the bond wafer is thinned to form a silicon active layer, wherein the base wafer is formed of silicon single crystal grown by Czochralski method, and the whole surface of the base wafer is within N region outside OSF region and doesn't include a defect region detected by Cu deposition method, or the whole surface of the base wafer is within a region outside OSF region, doesn't include a defect region detected by Cu deposition method, and includes I region containing dislocation cluster due to interstitial silicon. Thereby, there is provided an SOI wafer that retains high insulating properties and has an excellent electrical reliability in device fabrication even in the case of forming an extremely thin interlevel dielectric oxide film with, for example, a thickness of 100nm or less.

Description

SOI wafer and manufacture method thereof

Technical field

The present invention relates to the SOI wafer; More specifically, relate to electrical reliability high high-quality SOI wafer and manufacture method thereof.

Background technology

In the past, use substrate as device, the SOI wafer that is formed with silicon active layer (soi layer) on support substrate is utilized widely.As manufacture method of SOI wafer so, for example known have manufacture method that is a so-called applying method that two silicon wafers are fitted via oxide-film.

A kind of ion as applying method injects the method for peeling off, be to become the silicon wafer of silicon active layer (in conjunction with wafer) or becoming the surface of the silicon wafer (base wafer) of support substrate, formation is as the oxide-film (also being referred to as to imbed oxide-film, layer insulation oxide-film etc.) of insulating barrier, again from surface in conjunction with a side of wafer, the ion of hydrogen etc. is carried out ion inject, thereby at the inner ion implanted layer (micro-bubble layer) that forms of wafer.And then, via oxide-film, will inject the face of side in conjunction with the ion of wafer, be fitted in after the base wafer, by heat treatment, ion implanted layer is peeled off as the border.Whereby, can access: on base wafer,, be formed with the SOI wafer of thin silicon active layer via oxide-film.Moreover, after peeling off, also have in order to improve that adhesion between silicon active layer and the base wafer is heat-treated (in conjunction with heat treatment) or for situations such as the oxide-film of removing the surface carry out that hydrofluoric acid is cleaned.

As the silicon wafer in the manufacturing that so is used in the SOI wafer, generally speaking, can use the silicon single crystal of being grown by Czochralski method (CZ method), but, in recent years, along with silicon active layer or imbed the raising that the filming of oxide-film requires, the quality requirements of employed silicon wafer is also more and more stricter.

Particularly about become silicon active layer in conjunction with wafer, a kind of few silicon single crystal of defective that generates is proposed, re-use the method for resulting thus high-quality silicon wafer.

At this, illustrate the speed that draws high when generating silicon single crystal by Czochralski method, and the defective of the silicon single crystal that generated between relation.

(hot-zone: CZ HZ) draws high in the machine structure, in the crystal axis direction, speed of growth V by being varied under the situation of low speed at a high speed, has been notified the defect map that obtains as shown in Figure 9 near the big stove of temperature gradient G in using common crystallization the solid liquid interface.

In Fig. 9, so-called V zone, for lattice vacancy (Vacancy) just because the many zones of defective of recess of being taken place of silicon atom deficiency, cave and so on; So-called I zone then is owing to there be dislocation or the many zones of unnecessary silicon atom piece that silicon took place between unnecessary silicon atom that is lattice.And between V zone and I zone, it is not enough or do not have surplus (surplus be'ss few) a neutral region (Neutral, following simple table is shown N) to exist atom; In addition, boundary vicinity in the V zone, be referred to as the defective of OSF (stacking fault, Oxidation Induced Stacking F ault are induced in oxidation), when on section, observing, be confirmed to be and be scattered in ring-type (hereinafter referred to as the OSF ring) with respect to the vertical direction of crystalline growth axle.

And, than under the situation faster, become the growth defect of FPD, LSTD, the COP etc. of the reason of the cavity that the point defect of lattice vacancy type concentrates in the speed of growth, be present in the diametric whole zone of crystallization to high-density, the zone that these defectives exist becomes the V zone.In addition, along with the reduction of the speed of growth, the OSF ring takes place from the periphery of crystallization, in the outside of this ring (low speed side), the n-quadrant takes place; If make the speed of growth further become low speed, then the OSF ring shrinks toward the center of wafer and offsets, and all faces become the n-quadrant.If reduce the speed of growth further, defective (big dislocation group) the low-density ground that then is considered to the L/D (Large Dislocation: the abbreviation of dislocation loop, LSEPD, LFPD etc. between lattice) of the occurrence cause of the dislocation loop of silicon set between lattice exists, and exists the zone of these defectives to become I zone (being also referred to as the L/D zone).

And the n-quadrant outside the ring of the OSF in the middle of V zone and the I zone becomes the FPD, the LSTD that there are not the lattice vacancy cause, COP, does not also have the LSEPD of silicon cause between lattice, the zone of LFPD.Moreover, recently,, as shown in Figure 9, have in abutting connection with the Nv zone (zones that lattice vacancy is many) in the OSF ring outside with in abutting connection with the Ni zone (the many zones of silicon between lattice) in I zone if classified further in the n-quadrant; Known in the Nv zone, after thermal oxidation, the oxygen amount of separating out is many, and in the Ni zone, does not almost have oxygen to separate out.

N-quadrant so, in the past in wafer face, exist only in some, still draw high the ratio that is the V/G of speed (V) and crystallization solid liquid interface direction of principal axis temperature gradient (G) by control, the n-quadrant that also can produce as shown in Figure 9 extends to laterally all crystallizations of face (all faces of wafer).

So, in the manufacturing of SOI wafer, also propose:, use the method for all faces as the silicon single crystal wafer of n-quadrant as in conjunction with wafer.For example, propose:, be controlled in the prescribed limit with the ratio (V/G) that draws high the temperature gradient G of axial crystallization solid liquid interface when drawing high silicon single crystal by Czochralski method (CZ method), draw high silicon single crystal drawing high speed V; As in conjunction with wafer, use the SOI wafer (for example, please refer to the spy and open 2001-146498 communique (5-8 page or leaf) and TOHKEMY 2001-44398 communique (2-4 page or leaf, Fig. 1)) of the silicon wafer of n-quadrant.

On the other hand, about base wafer, be to be used for supporting originally via the necessary wafer of the soi layer of dielectric film, on its surface, be not directly to carry out element to form.Therefore, also propose: resistance value etc. is not met the silicon wafer of the utmost points such as emulation (dummy grade) of goods specification, the scheme of using as base wafer (please refer to Japanese kokai publication hei 11-40786 communique).

Generally speaking, as base wafer, consider and improve quality and productivity etc., as shown in Figure 9, generate and to comprise in the some with the V zone of at a high speed the speed that draws high growth or the silicon single crystal in OSF zone or Nv zone, the silicon wafer of the mirror-like that is processed into by the silicon single crystal of high-speed rapid growth like this is widely used.

As mentioned above, in the surface and volume by the resulting silicon wafer of silicon single crystal of high-speed rapid growth, be formed with the lattice vacancy defective of COP that lattice vacancy concentrates and so on to high-density, surperficial then have most the small pit defects more than the 50nm.And, if will exist the silicon wafer of most small pit defects like this to use as base wafer, when producing the SOI wafer, the thickness that particularly will imbed oxide-film forms under the thin situation by requirement in recent years, can produce the problem that can't keep high-insulativity and damage electrical reliability.

Summary of the invention

So, the present invention puts in view of the above-mentioned problems and develops, and its purpose is to provide a kind of SOI wafer, even imbed under the situation as thin as a wafer that the thickness of oxide-film for example forms the following degree of 100nm, high-insulativity is also kept, electrical reliability height in device fabrication.

In order to achieve the above object, according to the present invention, provide a kind of SOI wafer, for will be respectively by the formed base wafer of silicon single crystal with in conjunction with wafer, after being fitted via oxide-film, aforementionedly form the SOI wafer of silicon active layer, it is characterized by in conjunction with the wafer filming by making:

The aforementioned substrates wafer, for by the silicon single crystal that Czochralski method generated, all faces of this wafer be the OSF zone the outside the n-quadrant and do not contain the silicon wafer of the defect area that is detected by the Cu sedimentation; Or all faces of this wafer are the outside in OSF zone, do not contain the defect area that is detected by the Cu sedimentation, and comprise to exist and result from that the silicon wafer in the I zone of the dislocation group of silicon constitutes between lattice.

If all faces of base wafer be the OSF zone the outside the n-quadrant and do not contain the SOI wafer that the CZ silicon single crystal of the defect area that is detected by the Cu sedimentation is constituted, then owing to do not have tiny flaw on the surface of base wafer, even the thickness of imbedding oxide-film on the base wafer for example is under the situation of the following film of 100nm, also can not be subjected to the defect influence on base wafer surface and produce insulation characterisitic destruction, and become the high SOI wafer of electrical reliability.

On the other hand, if all faces of base wafer are the outside in OSF zone, do not contain the defect area that is detected by the Cu sedimentation, and comprise to exist and result from the SOI wafer that the CZ silicon single crystal in the I zone of the dislocation group of silicon is constituted between lattice, then owing to do not have small lattice vacancy defective on the surface of base wafer, even the thickness of imbedding oxide-film on the base wafer for example is under the situation of the following film of 100nm, also can not be subjected to the lattice vacancy defect influence on base wafer surface and produce insulation breakdown, become the high SOI wafer of electrical reliability.Again, owing to being the silicon wafer in I zone, so low price than being easier to produce all faces of for example wafer that constitute base wafer.

At this moment, preferentially, the SOI wafer is, and is aforementioned in conjunction with in the wafer by ion is injected into, and peeled off at formed ion implanted layer, and the ion that carries out aforementioned filming in conjunction with wafer injects the wafer of peeling off method and forming.

As the applying method, also can cut by grinding, grind to make and make the SOI wafer, but the thickness of the soi layer of this moment is thicker in conjunction with the wafer filming with after fitting in conjunction with wafer and base wafer.On the other hand, if method is peeled off in injection according to ion, the degree of depth of ion implanted layer that is the thickness of soi layer can be made desired in recent years grade as thin as a wafer, and can make the SOI wafer of very high quality.

The thickness of aforementioned oxide-film can be in the scope of 10～100nm.

In recent years, the thickness of imbedding oxide-film for example is required to make the degree of 50nm, and SOI wafer of the present invention, even form so thin oxide-film, the insulation breakdown characteristic can be by deterioration yet, and can keep high-insulativity.

Again, preferentially, aforementioned silicon active layer is, by the silicon single crystal of growing by Czochralski method, all faces are the n-quadrant in the outside in OSF zone, and the silicon single crystal that does not comprise the defect area that is detected by the Cu sedimentation constitutes.

So, if silicon active layer also is made of by the n-quadrant in the outside in OSF zone and the CZ silicon single crystal that do not comprise the defect area that is detected by the Cu sedimentation all faces, then form the zone and do not have defective at device, in addition, even carrying out hydrofluoric acid cleans, do not exist yet result from the silicon active layer defective silicon active layer or imbed the ruined situation of oxide-film, and become the SOI wafer of very high quality.

And then, according to the present invention, also provide a kind of manufacture method of above-mentioned SOI wafer.That is, comprise at least: by the formed base wafer of silicon single crystal with in conjunction with at least one side in the wafer, form the step of oxide-film respectively; By ion being injected in conjunction with the step that forms ion implanted layer in the wafer; With this face, via aforementioned oxide-film, with the step of base wafer applying in conjunction with the ion injection side of wafer; The step that aforementioned ion implanted layer is peeled off as the border.It is characterized by:

As the aforementioned substrates wafer, use:

Silicon single crystal by czochralski-grown, all faces of this wafer are, the time will draw high speed by little by little becoming under the situation of low speed at a high speed in growth, for than the OSF zone that takes place annularly more low speed side the n-quadrant and do not contain the silicon wafer of the defect area that is detected by the Cu sedimentation; Or the time will draw high speed by little by little becoming under the situation of low speed at a high speed in growth, for than the OSF zone that takes place annularly more low speed side, do not contain the defect area that is detected by the Cu sedimentation and comprise to exist and result from the silicon wafer in the I zone of the dislocation group of silicon between lattice.

Inject when peeling off method and making the SOI wafer according to ion, as base wafer, if using all faces of aforesaid wafer is flawless CZ silicon single crystal wafer, even the formed thickness of oxide-film of imbedding is below 100nm, in conjunction with heat treatment etc. the time, can be owing to the defective that is present in the base wafer does not cause the situation of the insulation breakdown deterioration in characteristics of oxide-film yet, and can produce the high high-quality SOI wafer of electrical reliability.

On the other hand, inject when peeling off method and making the SOI wafer according to ion, as base wafer, if use the aforesaid defect area that is detected by the Cu sedimentation that do not contain, and comprise to exist and result from the CZ silicon single crystal wafer in the I zone of the dislocation group of silicon between lattice, even then imbedding the thickness of oxide-film is formed on below the 100nm, in conjunction with heat treatment etc. the time, can be owing to the lattice vacancy defective that is present in the base wafer does not cause the situation of the insulation breakdown deterioration in characteristics of oxide-film yet, thus can produce the high high-quality SOI wafer of electrical reliability.Again, be the silicon wafer in I zone as all faces of the employed for example wafer of base wafer, because being become, its control range extensively and with comparalive ease produces, so can be easily and produce high-quality SOI wafer at low cost.

In this case, preferentially, in conjunction with the wafer use be: by the silicon single crystal of czochralski-grown, all faces of this wafer, the speed that will draw high when generating is by little by little becoming under the situation of low speed at a high speed, for than the OSF zone that takes place annularly more low speed side the n-quadrant and do not contain the silicon wafer of the defect area that is detected by the Cu sedimentation

So, if use flawless wafer as making the SOI wafer in conjunction with wafer, the device that then is formed on the soi layer can not be adversely affected, and can positively prevent the deterioration of the insulation breakdown characteristic of interlayer dielectric yet, thereby can produce the SOI wafer of very high quality.

Again, also propose a kind ofly when utilizing ion to inject to peel off method when making the SOI wafer recently, the method for in addition utilizing again as base wafer (or in conjunction with wafer) after the Regeneration Treatment in conjunction with wafer (removed wafer) after peeling off (is for example opened flat 11-297583 communique with reference to the spy.)。Therefore,, afterwards,, utilize again, can reduce manufacturing cost and produce high-quality SOI wafer as base wafer or in conjunction with wafer with the removed wafer Regeneration Treatment if use is aforesaid flawless in conjunction with wafer.

As previously discussed, according to the present invention, it is n-quadrant and the SOI wafer that silicon wafer constituted that does not contain the defect area that is detected by the Cu sedimentation that a kind of all faces by base wafer can be provided.If use so SOI wafer, be below the 100nm even imbed the thickness of oxide-film, also keep excellent insulation characterisitic, therefore, if it is used on the manufacturing installation, then can with high finished product rate produce the device of electrical characteristic excellence.

Again, according to the present invention, a kind of all faces by base wafer can be provided is the outside in OSF zone, do not contain the defect area that is detected by the Cu sedimentation and comprise to exist and result from the SOI wafer that silicon wafer constituted in the I zone of the dislocation group of silicon between lattice.In this case, owing to base wafer can produce with comparalive ease, so manufacturing cost can be suppressed in the low-cost scope.

Description of drawings

Fig. 1 is the flow chart of expression about an example of the manufacturing step of SOI wafer of the present invention.

The key diagram of Fig. 2 (A) one example of employed crystal region when being illustrated in manufacturing about SOI wafer of the present invention.

Other routine key diagrams of Fig. 2 (B) employed crystal region when being illustrated in manufacturing about SOI wafer of the present invention.

Fig. 3 is an example of the CZ apparatus for manufacturing silicone single crystals that can use in the present invention.

Fig. 4 (A) is the graph of a relation of the relation of expression crystal growth speed and crystallization off-position.

Fig. 4 (B) is for being the expression speed of growth and each regional key diagram.

Fig. 5 estimates the key diagram of the manufacture method of sample for expression Cu deposition.

Vertically cut (A) wafer life cycle of processing section and reach (B) figure of Cu deposition defective for Fig. 6 represents crystallization.

Fig. 7 be illustrated in experiment in 2 the speed of growth and the figure of crystallization off-position.

Fig. 8 is the figure of expression according to the defect distribution of resulting each crystal region of Cu sedimentation.

(A) V zone

(B) n-quadrant (Cu deposition defective takes place)

(C) n-quadrant (no Cu deposition defective)

Fig. 9 is the key diagram of explanation crystal region.

Figure 10 (A) is the graph of a relation of the relation of expression crystal growth speed and crystallization off-position.

Figure 10 (B) is the expression speed of growth and each regional key diagram.

Figure 11 is the key diagram of the speed of growth of each silicon single crystal that expression generated.

Figure 12 is the figure of expression according to the resulting defect distribution of Cu sedimentation.

(A) base wafer in V zone

(B) base wafer in I zone (no Cu deposition defective)

Embodiment

Below, the present invention is described in further detail.

The present inventor to imbedding the influence of oxide-film, has carried out detailed investigation about the base wafer of the SOI wafer made by the applying method.Its result, learn if use the silicon single crystal that is the surperficial silicon wafer that has the tiny flaw of the above lattice vacancy type of 50nm of normally used high-speed rapid growth in the past, when making the SOI wafer, when imbedding under the situation that oxide-film has the thickness sufficient more than hundreds of nm, be difficult to produce because the problem of deterioration of the insulation breakdown characteristic that influence caused of base wafer and so on; But, if under the situation of the following film of 100nm, then might since the influence of base wafer and aspect the keeping of insulating properties the generation obstacle.Particularly form under the situation of imbedding oxide-film of the utmost points such as 50nm that always are required in recent years, the base wafer that is rich in V zone (V rich) in the past, marquis when in conjunction with heat treatment etc. can influence and imbed oxide-film, thereby can't keep high-insulativity, very likely damage electrical reliability.

Therefore, the present inventor thinks by reducing the tiny flaw of base wafer, even form under the following situation of imbedding oxide-film of 100nm, also can make not making insulation breakdown deterioration in characteristics and the electrical high SOI wafer of reliability, and then carry out following investigation and research.

At first, when drawing high silicon single crystal, from the crystallization shoulder to crystal ingot body afterbody, by at a high speed gradually under the situation of step-down speed, as previously mentioned, when reaching a certain speed of growth, OSF shrinks, then, in low-speed region more, known order of respectively meeting according to Nv, Ni, I (big dislocation group takes place) zone is formed.In addition, recently known in the Nv zone shown in Fig. 2 (A), exist after a part of OSF just offset, be detected the zone (following also have the Cu of being called deposition defect area) (for example please refer to the spy and open the 2002-201093 communique) of defective by the Cu sedimentation.

So-called Cu sedimentation is the position that determines the defective of semiconductor wafer exactly, improves the detection limit for the defective of semiconductor wafer, and the evaluation assessment of the wafer that can be measured exactly, analyze for more small defective.

The evaluation method of concrete wafer is to form the dielectric film of specific thickness on wafer surface, electrodisintegration is formed on the dielectric film near the aforementioned wafer surface the rejected region again, separates out the method for the electrolysed substance of (deposition) Cu etc. at rejected region.That is to say that the Cu sedimentation is to utilize in the liquid that is dissolved with the Cu ion, if the oxide-film that is formed on the wafer surface is applied current potential, electric current can flow through the oxide-film position of deterioration, and then the Cu ion becomes Cu and the evaluation assessment of the principle separated out.In the part of the easy deterioration of oxide-film, the known defective that has COP etc.

The rejected region of the wafer that is deposited by Cu can be under spotlight or directly analyze with naked eyes, estimates its distribution or density, so also can utilize microscopic examination, infiltration type electron microscope (TEM; Transmission Electron Microscope) or scanning electron microscope (SEM; ScanningElectron Microscope) etc. confirmed.

And the present inventor to the defective in these zones, further investigates.

Particularly, silicon monocrystal growth is by at a high speed gradually step-down speed the time, by surface examining device (MAGICS; Trade name) to the V zone of OSF before just will having offset carry out the coordinate location after, implement focused ion beam (FIB; Focused Ion Beam) processing when carrying out the tem observation of this point, confirms to have the small pit defect of about 20nm to exist.In addition, in the V zone, offset zone before the closer to OSF, lattice vacancy is got over miniaturization; But the small pit defect in V zone, even considerably fine, also can showing lands destroys the withstand voltage (TZDB of initial oxidation film; Time ZeroDielectric Breakdown) characteristic.

On the other hand, Cu deposition defect area after OSF when step-down is fast gradually by high speed about silicon monocrystal growth has just offset, not as the destruction of anti-significantly () as V zone pressure grade, the TZDB characteristic is in wafer face in about 100% the zone, though show the C state, at time correlation dielectric breakdown (TDDB; Time Dependent Dielectric Breakdown) on the characteristic, demonstrates deterioration a little.

The result who so investigates, studies, learn, make when imbedding the oxide-film filming when requirement recently according to a part of device, in conjunction with wafer that is silicon active layer, no matter be the situation that the silicon single crystal wafer that has Cu deposition defect area by employed V zone or OSF zone or n-quadrant is in the past constituted, and so silicon wafer is used under the situation of base wafer, also can produce obstacle for the insulating properties of oxide-film, and cause electrically bad.

Again, be present in these regional lattice vacancy type defectives, in conjunction with heat treatment the time, the danger that the membranous deterioration that causes imbedding oxide-film is arranged, particularly work as under the situation that thickness is the following film of 100nm, not only can't keep excellent insulating properties, and cause the obstacle of electrical aspect, become the reason of seriously damaging reliability.

Therefore, the present inventor has found out, for fear of so electrically bad, if base wafer with the SOI wafer, grow into and do not have the words of minute surface wafer that are detected the n-quadrant of defect area by the Cu sedimentation, even imbedding the thickness of oxide-film is below the 100nm, also can make the method for the SOI wafer of electrical excellence.

But, be grown to serve as the n-quadrant and not exist Cu to deposit the silicon single crystal of defect area, the speed of growth is limited in the narrow range, in addition, owing to require V/G is remained on the crystalline growth technology of the height of setting and so on, so productivity and fabrication yield are low, and the result will cause cost to rise.

Therefore, the present inventor, through research further, work out under the situation that the CZ silicon wafer that will contain the I zone uses as base wafer, even imbedding the thickness of oxide-film is below the 100nm, even also can produce the crystalline growth technology of not using height of the SOI wafer of electrical excellence with low cost, the method that also can make easily at low speed side, and finished the present invention.

Below, specifically describe embodiments of the invention with reference to accompanying drawing, but the present invention is not limited in these examples.

Fig. 1 injects the flow chart of an example that the method for peeling off is made the manufacturing step of SOI wafer of the present invention for expression by ion.

At first, in initial step (a), prepare two silicon mirror wafers, that is prepare to constitute the base wafer 22 in conjunction with wafer 21 and formation support substrate of soi layer.At this, among the present invention,, be to use all faces of wafer to be as base wafer 22:

When by czochralski-grown, with the speed that draws high by little by little becoming under the situation of low speed at a high speed, for than the OSF zone that takes place annularly more low speed side the n-quadrant and do not contain the silicon wafer (the 1st form) of the defect area that is detected by the Cu sedimentation; Or when growth, with the speed that draws high by little by little becoming under the situation of low speed at a high speed, for than the OSF zone that takes place annularly more low speed side, do not contain the defect area that is detected by the Cu sedimentation and contain to exist and result from the silicon wafer (the 2nd form) in the I zone of the dislocation group of silicon between lattice.

At first, as the 1st form, above-mentioned is n-quadrant and the silicon single crystal that does not have Cu deposition defect area, for example, can use monocrystalline manufacturing equipment as shown in Figure 3, grows while control V/G.

This monocrystalline draws high device 30, possesses: draw high chamber 31, be set at the crucible 32 that draws high in the chamber 31, be set at heater 34, the crucible retainer shaft 33 that makes crucible 32 rotations and its rotating mechanism (not shown) around the crucible 32, keep the brilliant chuck 6 of kind of the kind crystalline substance of silicon, the winding mechanism (not shown) that draws high kind of the messenger wire of brilliant chuck 67 and make messenger wire 7 rotations or reel.In the outer periphery of heater 34, adiabatic material 35 is set again.

Crucible 32, melted silicon (liquation) 2 sides of accommodating of side are provided with silica crucible within it, and graphite crucible then is set at its outside.

Moreover, often use recently, in the outside of the horizontal direction that draws high chamber 31, not shown magnetite is set,, suppresses the convection current of liquation by melted silicon 2 being applied the magnetic field of horizontal direction or vertical direction etc., with the stable growth of seeking monocrystalline, just so-called MCZ method.

Be provided with the graphite tube (thermal insulation board) 12 of the tubular that surrounded of silicon single crystal 1 that will growth again; And then near the periphery the solid liquid interface 4 of crystallization is provided with the adiabatic material 10 in the outside of ring-type.Moreover, the situation that inboard adiabatic material is set in the inboard of graphite tube 12 is also arranged.So adiabatic material 10 is configured to: between the liquid level 3 of its lower end and melted silicon 2, separate the interval of 2～20cm.Be provided with if so, the temperature gradient Gc of nucleus of crystal part (℃/cm) and the difference between the temperature gradient Ge of crystallization peripheral part diminish, it is lower than nucleus of crystal for example temperature in the stove can be controlled to the temperature gradient that makes the crystallization periphery.

Again, on graphite tube 12, cooling cylinder 14 is arranged, coolant is circulated and force and cool off.And, the ejection refrigerating gas also can be set or be provided with and cover the tubular cooling device that radiant heat cools off monocrystalline.

When using so monocrystalline to draw high device 30 to make silicon single crystal, at first, in crucible 32, make its fusion more than many crystallizations of high-purity raw material of silicon is heated to fusing point (about 1420 ℃).Then, by messenger wire 7 is rolled out, the surface that makes the preceding end in contact of kind of crystalline substance or be immersed in liquation 2 is central part approximately.Then, make 33 rotations of crucible retainer shaft, while messenger wire 7 rotations are batched.Whereby, plant crystalline substance on one side and also rotate and drawn high, so that monocrystalline begins is grown, after, draw high speed and temperature by adjustment suitably, just can access the monocrystal rod 1 of about cylindrical shape.

And, be generated as the n-quadrant and when not containing the silicon single crystal of Cu deposition defect area, for example, the speed of growth (drawing high speed) of the silicon single crystal in drawing high is little by little become under the situation of low speed by high speed, the speed of growth is controlled at: remain in annularly the OSF zone that takes place offset the border that defect area later, that detected by the Cu sedimentation offsets the speed of growth and, take place between the speed of growth on the border of dislocation loop between lattice when the speed of growth is reduced further; The crystallization of growing in this way.

That is, the speed of growth with the silicon single crystal in drawing high, from the crystallization shoulder to crystal ingot body afterbody, by at a high speed little by little under the situation of step-down speed, shown in Fig. 2 (A), corresponding to speed of growth V, according to the order of V zone, OSF ring zone, Cu deposition defect area, Nv zone, Ni zone, I zone (big dislocation group generation area), each in turn is formed mutually; But in the n-quadrant, the speed of growth is controlled at: remain in the border that the defect area that is detected by the Cu sedimentation after OSF ring is offset offsets the speed of growth and, when the speed of growth further decrescence the time, the single crystals of growing is in this way taken place between the speed of growth in I zone.According to method so, can grow into the silicon single crystal of n-quadrant, this silicon single crystal does not contain the V area defects of FPD etc., I area defects, the OSF defective that big dislocation group (LSEPD, LFPD) waits, and the defective that is detected by the Cu sedimentation.

And, with the silicon single crystal of above-mentioned growth, be processed into mirror ultrafinish wafer (PM) afterwards, from the unit batch of each crystal ingot piece, at random choose PW, estimate by the Cu sedimentation then, as long as do not having under the situation of defective, just it can be adopted as base wafer 22.

Moreover, about in conjunction with wafer 21, as long as use the desired quality of corresponding silicon active layer just passable, but in conjunction with wafer 21 if also use with the same wafer of base wafer 22 that is all faces of wafer for than the n-quadrant of low speed side more, the OSF zone that takes place annularly, and the silicon wafer that does not contain the defect area that is detected by the Cu sedimentation, then on silicon active layer, there is not tiny flaw, therefore not only can improve formed equipment energy characteristic, even and imbed the thickness that oxide-film forms the 50nm degree, in ensuing process in conjunction with heat treatment etc., can prevent positively that also it is high that electrical reliability is become owing to the deterioration of the insulation breakdown characteristic that influence caused of base wafer.

And then, also use the wafer identical in conjunction with wafer 21 with base wafer 22, as hereinafter described, with utilizing again after peeling off in conjunction with wafer carries out Regeneration Treatment, just can be to produce the high SOI wafer of electrical reliability at low cost.

But, in the time will making that so all faces of wafer are flawless silicon wafer, in the whole growth step of silicon single crystal, must control V/G equably makes and can become the n-quadrant in the crystallization diametric(al), and the setting range of the speed of growth is limited in the very strict scope, need very high crystalline growth technology, the result also has the situation that causes cost to rise.

Therefore, in the present invention, as the 2nd form, as base wafer 22, as previously mentioned, also can use a kind of by the formed silicon wafer of CZ silicon single crystal, this CZ silicon single crystal is: when when growth, in the speed that will draw high by little by little becoming under the situation of low speed at a high speed, for than the OSF zone that takes place annularly low speed side more, do not contain the defect area that is detected by the Cu sedimentation, and contain the CZ silicon single crystal in the I zone of the dislocation group that results between lattice.

If this kind silicon single crystal can not use the crystalline growth technology of height required when wanting growth wafer to become flawless silicon single crystal comprehensively.For example, when will growing into all faces when being the silicon single crystal in I zone, during crystalline growth, the diametric V/G of crystallization need not be subjected to the restriction that will control equably, can grow with comparalive ease at low speed side.Even suppose that the diametric V/G of crystallization is inhomogeneous, when making the crystallization of I zone, can use the high G in employed hot-zone when making than n-quadrant crystallization, that is near the big hot-zone of temperature gradient of solid liquid interface in the crystallization.Therefore,, all faces can be become the monocrystalline in I zone, draw high more at high speed with the situation that becomes the monocrystalline of n-quadrant than all faces of growth according to the design sequence of hot-zone.This is because the V/G value in the crystal plane does not need the cause of homogeneous.

Moreover, base wafer 22 as the 2nd form of the present invention is not limited only to the wafer that all faces become the I zone, shown in Fig. 2 (B), except the I zone, also can use by comprising the Ni zone that silicon is many between lattice and not containing the formed wafer of silicon single crystal that Cu deposits defective.Because so also not having the defective of lattice vacancy cause in the wafer face, so, also can not make its insulation breakdown deterioration in characteristics even imbedding oxide-film approaches.

On the other hand, about in conjunction with wafer 21, with the 1st homomorphosis, as long as use the desired quality of corresponding silicon active layer just passable, but owing on silicon active layer, form device, so, then can influence the quality of device if having defective at silicon active layer.So,, preferably use by the formed wafer of the silicon single crystal that does not have tiny flaw as in conjunction with wafer 21.Therefore, as in conjunction with wafer 21, the preferential use: all faces of wafer be than the n-quadrant of low speed side more, the OSF zone of generation annularly, and do not contain the silicon wafer of the defect area that is detected by the Cu sedimentation.

Then, in the step (b) of Fig. 1, oxidation is in conjunction with the surface of the wafer of at least one side in wafer 21 and the base wafer 22.At this, will form oxide-film 23 on its surface in conjunction with wafer 21 thermal oxidations.At this moment, oxide-film 23 will make the thickness that can keep desired insulating properties, and in the present invention, can form thickness is the interior oxide-film as thin as a wafer of scope of 10～100nm.

As base wafer, if use the employed in the past silicon wafer that for example has the lattice vacancy type tiny flaw more than most 50nm on the surface, making the thickness of imbedding oxide-film is the following SOI wafer of 100nm, then oxide-film is subjected to being present in the lattice vacancy defect influence on the surface of base wafer, afterwards in conjunction with in heat treatment or the device manufacturing step, might be because heat treatment and destroyed.But, in the present invention, as base wafer 22, owing to uses: as the n-quadrant and do not contain and be present in the silicon wafer (the 1st form) that Cu deposits the atomic little defective in the defect area; Or do not contain the defect area that is detected by the Cu sedimentation, and comprise to exist and result from the formed silicon wafer of CZ silicon single crystal (the 2nd form) in the I zone of the dislocation group of silicon between lattice; Even, oxide-film can not take place yet destroy,, also can not produce the problem of the deterioration and so on of insulation breakdown characteristic even for example the thickness of oxide-film 23 is made below the 100nm so utilize the Cu sedimentation to estimate.

Moreover, if the thickness that makes oxide-film 23 less than 10nm, though then the formation time of oxide-film reduces, might can't guarantee enough insulating properties, make more than the 10nm so be desirably.

In step (C), be formed with the surface in conjunction with a side of wafer 21 of oxide-film 23 from the surface, inject hydrogen ion.Moreover, also the mist ion of noble gas ion or hydrogen ion and rare gas can be carried out ion and injects.Whereby, can be in wafer inside, in ion on average enter the degree of depth, form and surperficial parallel ion implanted layer 24.Moreover the degree of depth of ion implanted layer of this moment is reflected in the thickness of the soi layer of final formation.Therefore, the injection energy that injects by the control ion etc. can be controlled the thickness of soi layer, for example also can make the soi layer of the following thickness of 200nm.

In step (d), will inject the surface of side and the surface of base wafer 22 in conjunction with the ion of wafer 21, via oxide-film 23, fitted.For example, under the clean environment of normal temperature,, need not to use sticker etc., come bond wafer by making the surface contact of two

wafers

21,22.

Then, in step (e),,, will be peeled off in conjunction with the some of wafer 21 at ion implanted layer 24 by heat treatment.For example, for being fitted and product after boning in conjunction with wafer 21 and base wafer 22, if under inert gas and under about temperature more than 500 ℃, impose heat treatment, then, be separated into removed wafer 25 and SOI wafer 26 (soi layer 27+ imbeds oxide-film 23+ base wafer 22) according to the arrangement again of crystallization and the aggegation of bubble.

At this, about the removed wafer 25 of accessory substance, propose recently a kind of release surface to be imposed the Regeneration Treatment of grinding etc., and it is utilized method again as base wafer or in conjunction with what wafer used.As previously mentioned, for using the n-quadrant and do not contain the silicon wafer of Cu deposition defect area,, can be used in base wafer and in conjunction with wafer 21 in conjunction with any of wafer so removed wafer 25 is carried out the resulting silicon wafer of Regeneration Treatment.Therefore, for example by removed wafer 25 is utilized as base wafer 22 again, also can produce same high-quality SOI wafer.That is SOI wafer of the present invention is created by a silicon wafer in fact, so can reduce manufacturing cost.

In step (f),, impose in conjunction with heat treatment for SOI wafer 26.This step (f), for because in the applying step of abovementioned steps (d), (e) and peel off in the heat treatment step by the adhesion between the wafer of fitting, if in element is made, to use under this state, then a little less than its adhesion, so as in conjunction with heat treatment, SOI wafer 26 is imposed the heat treatment of high temperature, make bond strength become abundant.For example, this heat treatment can with 1050 ℃～1200 ℃, be carried out in 30 minutes to 2 hours scope under the environment of inert gas.

Even so at high temperature heat-treat, because all faces of wafer of base wafer 22 are zero defect or the tiny flaw that does not have the lattice vacancy type at all faces of wafer, so the insulation breakdown characteristic of imbedding oxide-film 23 can be kept high-insulativity not by deterioration.

Step (g) is for to clean the process that is formed on SOI wafer 26 lip-deep oxide-films of removing by hydrofluoric acid.At this moment, if having lattice vacancy type defective, then imbed oxide-film, and small pit might take place because HF arrives by defective at silicon active layer 27; But all faces are constituted by n-quadrant and the silicon single crystal that do not contain the defect area that is detected by the Cu sedimentation because silicon active layer 27 is served as reasons, even clean so carry out hydrofluoric acid, pit can not take place yet enlarge and destruction soi layer 27 and the situation of imbedding oxide-film 23.

And then, in step (h), as required, be used for adjusting the oxidation of the thickness of soi layer 27; Then, in step (I), clean the so-called sacrificial oxidation of removing oxide-film 28 by hydrofluoric acid.

Through the SOI wafer 26 of aforesaid step (a)～(I) grow out, its base wafer 22, serve as reasons: all faces of wafer are the n-quadrant in the outside in OSF zone, and do not contain the CZ silicon single crystal of the defect area that is detected by the Cu sedimentation; Or all faces of wafer are the outside in OSF zone, do not contain the defect area that is detected by the Cu sedimentation, and contain to exist and result from that the CZ silicon single crystal in the I zone of the dislocation group of silicon constitutes between lattice.

On the other hand, silicon active layer 27, all faces of serving as reasons are constituted by the n-quadrant in the OSF zone outside and the CZ silicon single crystal that do not contain the defect area that is detected by the Cu sedimentation.That is owing to there is not the tiny flaw of lattice vacancy type on the surface of base wafer 22, even it is extremely thin to imbed oxide-film 23, high-insulativity is also kept, and electrically reliability is high.In addition, because soi layer 27 is a zero defect, when carrying out device formation, can reach high rate of finished products.

Below, enumerate embodiment and more specifically describe the present invention, but the present invention is defined in these embodiment.

(embodiment 1)

(experiment 1): draw high the affirmation of condition

Use the monocrystalline of Fig. 3 to draw high device 30, carry out the experiment decrescence of following crystal growth rate, investigation is in the speed of growth on each regional border.

At first, the polysilicon of 150kg is put into the silica crucible of diameter 24 inches (600mm) as raw material, come the silicon single crystal of growth diameter 210mm.Oxygen concentration then is controlled at 23～26ppma (ASTM ' 79 value).When growing single-crystal, shown in Fig. 4 (A), control growing speed, make its from the crystallization head to afterbody, by 0.70mm/min linearly decrescence to 0.30mm/min.

And, as Fig. 4 (A) (B) shown in, with the monocrystalline after drawing high from head to afterbody, in the crystal axis direction, slit shearing then, is produced the sample after the minute surface fine finishining of wafer shape of diameter 200mm.

To the one in the sample, measure (measuring instrument: SEMILAB WT-85), confirm V zone, OSF zone, each regional distribution situation in I zone and the speed of growth of each zone boundary by the wafer life cycle (WLT) that oxygen is separated out after the heat treatment.And then, to other one, then impose heat oxide film and form back Cu deposition processes, confirm the distribution situation of oxide-film defective.Moreover, the detailed assessment method in this experiment, as shown below.

(a) with the crystal ingot of diameter 210mm, cut into after the bulk with the length of the every 10cm of crystal axis direction, carry out slit shearing processing in the crystal axis direction, afterwards, as shown in Figure 5, in vertical direction, be finish-machined to the mirror finish sample of the wafer shape of diameter 200mm (8 inches) with respect to crystal axis.

(b) to the 1st in the said sample, after implementing 620 ℃ of (nitrogen environment) heat treatments in 2 hours in the wafer heat-treatment furnace, implement two sections heat treatments of 800 ℃ 4 hours (nitrogen environments) and 1000 ℃ 16 hours (dry oxygen environment), afterwards, cooled off, by SEMILAB WT-85, produce WLT figure.

(c) to the 2nd sample, then after forming heat oxide film on the wafer surface, implement the Cu deposition processes, confirm the distribution situation of oxide-film defective.Appreciation condition is as described below:

1) oxide-film: 25nm

2) electrolysis strength: 6MV/cm

3) voltage application time: 5 minutes

Experimental result

According to above-mentioned experiment, can obtain the result shown in (B) as Fig. 6 (A), confirmed the speed of growth of each zone boundary in V zone, OSF zone, n-quadrant, I zone.

V zone/OSF zone boundary: 0.523mm/min

OSF offsets border: 0.510mm/min

Cu deposition defective is offset border: 0.506mm/min

Separate out n-quadrant/non-border, n-quadrant: 0.497mm/min that separates out

Non-n-quadrant/I zone boundary: the 0.488mm/min that separates out

The manufacturing of (experiment 2) SOI wafer

By the draw high device identical with experiment shown in Figure 31, the polysilicon of 150Kg is put into the silica crucible of 24 inches of diameters as raw material, this time, as shown in Figure 7, with the speed of growth in the scope of 0.55mm/min to 0.45mm/min, from the crystallization head of the crystal ingot of diameter 210mm to afterbody, more lentamente decrescence than experiment 1, be controlled to and in the zone of the 40cm to 70cm of crystallization body portion, form the n-quadrant of containing Cu deposition defective and not contain the n-quadrant that Cu deposits defective.Again, oxygen concentration then is controlled at 24～26ppma (ASTM ' 79).And, according to following order, carry out quality evaluation and SOI processing.

(1) after crystallization draws high,, begins from the head in turn wafer to be cut off,, utilize laser labelling to put on number, be reprocessed into the minute surface wafer in order to learn its cut-out order in the crystal axis direction of each ingot.

(2) with the 1st PW of a side of each block unit, be divided into 1/4 size, investigation FPD, LFPD, LSEP, OSF.Then, to the 2nd PW of a side of each block unit, then confirm its Cu deposition defect distribution.And 5 PW altogether of a side the 3rd to the 7th of each block unit then put in the SOI wafer fabrication steps (SOI engineering).Estimate FPD, LFPD, LSEP, OSF with the 8th of correct side once more, then confirm its Cu deposition defect distribution for the 9th, 5 modes that then drop in the SOI journey altogether of the 10th to the 14th, with 2 of per 7 sides of being used as a unit of crystal axis direction, carry out quality evaluation, remaining 5 then are processed into the SOI wafer.

(3) result of above-mentioned evaluation is: from the centre of the block of about 40cm to 50cm of crystallization body portion, be V zone and OSF zone; To near the n-quadrant that takes place for Cu deposition defective the 50cm of crystallization body portion; Near about 50cm to 70cm of crystallization body portion, for the n-quadrant of Cu deposition defective does not take place; From near the zone till the afterbody 70cm of crystallization body portion then is the I zone.

(4) with per 5 a collection of minute surface wafers of above-mentioned (1), be used in conjunction with on wafer and the base wafer, ion according to step shown in Figure 1 injects the method for peeling off, through inject in conjunction with the ion of wafer, with the applying of base wafer, peel off heat treatment, in conjunction with heat treatment (applying oxidation) etc., produce the SOI wafer of silicon active layer with dielectric oxide film that thickness is 70nm and 200nm.

SOI wafer for making as stated above utilizes potassium hydroxide solution to select etching to remove active layer.Then, for base wafer,, estimate by the Cu sedimentation with the electrolysis strength of 6MV/cm with residual insulating oxide rete.

Its result, under the situation of the dielectric oxide film after the oxidation of fitting, in V zone, OSF zone and take place on the base wafer of n-quadrant of Cu deposition defect area, confirm to have the destruction (with reference to Fig. 8 (A), (B)) of oxide-film, but on the base wafer of the n-quadrant of not containing Cu deposition defect area, the destruction (with reference to Fig. 8 (C)) that oxide-film does not then take place.

(embodiment 2)

(experiment 3): draw high the affirmation of condition

At first, the polysilicon of 150Kg is put into the silica crucible of diameter 24 inches (600mm) as raw material, come the silicon single crystal of growth diameter 210mm.Oxygen concentration then is controlled at 23～26ppma (ASTM ' 79 value).When growing single-crystal, shown in Figure 10 (A), control growing speed, make its from the crystallization head to afterbody, by 0.80mm/min linearly decrescence to 0.40mm/min.

And, as Figure 10 (A) (B) shown in, with the monocrystalline after drawing high from head to afterbody, at crystal axis direction slit shearing, then, produce the sample after the minute surface fine finishining of wafer shape of diameter 200mm.

To one in the sample, measure (measuring instrument: SEMILAB WT-85), confirm V zone, OSF zone, each regional distribution situation in I zone and the speed of growth of each zone boundary by the wafer life cycle (WLT) that oxygen is separated out after the heat treatment.Moreover, the detailed assessment method in this experiment, as shown below.

(a) with diameter be the crystal ingot of 210mm, cut into after the bulk with the length of the every 10cm of crystal axis direction, carry out slit shearing processing in the crystal axis direction, afterwards, as shown in Figure 5, in vertical direction, be finish-machined to the mirror finish sample of the wafer shape of diameter 200mm (8 inches) with respect to crystal axis.

(b) to the 1st in the said sample, after implementing 620 ℃ of (nitrogen environment) heat treatments in 2 hours in the wafer heat-treatment furnace, implement 2 sections heat treatments of 800 ℃ 4 hours (nitrogen environment) and 1000 ℃ 16 hours (dry oxygen environment), afterwards, cooled off, by SEMILAB WT-85, produce WLT figure.

Experimental result

According to above-mentioned experiment, confirmed the speed of growth of each zone boundary in V zone, OSF zone, n-quadrant, I zone.

V zone/OSF zone boundary: 0.595mm/min

OSF zone/border, n-quadrant: 0.587mm/min

N-quadrant/I zone boundary: 0.579mm/min

The manufacturing of (experiment 4) SOI wafer

By the draw high device identical with experiment shown in Figure 33, the polysilicon of 150Kg is put into the silica crucible of 24 inches of diameters as raw material, the result of experiment 3 is the basis crystal ingot that to draw high two diameters be 210mm.

At this moment, as shown in figure 11, the 1st is set at the 0.65mm/min of regulation with its speed of growth from crystallization head to afterbody, draws high with this speed, makes region-wide formation V zone in face.Again, the 2nd is set at the 0.55mm/min of regulation with its speed of growth from crystallization head to afterbody, draws high with this speed, and this makes region-wide formation I zone in face.Oxygen concentration then is controlled at 24～26ppma (ASTM ' 79 value) and makes.And the minute surface wafer that will be made into by each crystal ingot uses as base wafer.

On the other hand, as in conjunction with wafer, then used to grow into the n-quadrant in different hot-zones and do not contain the silicon single crystal that is detected defect area by the Cu sedimentation, thus the resulting minute surface wafer of monocrystalline.

Use aforesaid, all faces of wafer to be the base wafer in V zone or I zone, and flawless in conjunction with wafer, the thickness of producing dielectric oxide film respectively is that the thickness of 70nm, silicon active layer is the SOI wafer of 200nm.

SOI wafer for making as above-mentioned method utilizes potassium hydroxide solution to select etching to remove silicon active layer.Then, for base wafer,, estimate by the Cu sedimentation with the electrolysis strength of 6MV/cm with residual insulating oxide rete.

As a result, under the situation of the dielectric oxide film after the oxidation of fitting, shown in Figure 12 (A), Zone Full is the base wafer side in V zone in the face, confirms to have the destruction of oxide-film.On the other hand, in the face Zone Full be the I zone in conjunction with wafer side, shown in Figure 12 (B), the destruction that oxide-film does not take place.

Moreover the present invention is not limited to the foregoing description.The foregoing description only is an example, every have with claim scope of the present invention in the identical in fact formation of technological thought put down in writing, and have identical action effect, at all events the person all is comprised in the technical scope of the present invention.

For example, in the above-described embodiments, illustrated, injected the situation that method is made the SOI wafer of peeling off by ion about using two silicon wafers; But the present invention also can be applied to after applying, makes the SOI wafer of making in conjunction with the rear side filming of wafer by grinding to cut to grind.

Claims

1. SOI wafer will be respectively by the formed base wafer of silicon single crystal with in conjunction with wafer, is after the oxide-film of 10～100nm is fitted via thickness, aforementionedly forms the SOI wafer of silicon active layer in conjunction with the wafer filming by making, and it is characterized by:

The aforementioned substrates wafer is the silicon single crystal of growing by by Czochralski method, and all faces of this wafer are the n-quadrant in the outside, OSF zone and the silicon wafer that does not contain the defect area that is detected by the Cu sedimentation; Or all faces of this wafer by the outside in OSF zone, do not contain the defect area that is detected by the Cu sedimentation and comprise to exist and result from that the silicon wafer in the I zone of the dislocation group of silicon is constituted between lattice.

2. SOI wafer as claimed in claim 1 is characterized by:

Aforementioned SOI wafer is aforementioned in conjunction with in the wafer by ion is injected into, and by being peeled off at formed ion implanted layer, the ion that carries out aforementioned filming in conjunction with wafer injects to be peeled off method and form.

3. SOI wafer as claimed in claim 1 or 2 is characterized by:

Aforementioned silicon active layer is by the silicon single crystal by czochralski-grown, and all faces are the n-quadrant in the outside in OSF zone, and the silicon wafer that does not contain the defect area that is detected by the Cu sedimentation constitutes.

4. the manufacture method of a SOI wafer comprises at least: by the formed base wafer of silicon single crystal with in conjunction with at least one side among the wafer, forming oxide-film and making the thickness of the oxide-film of imbedding is the step of 10～100nm respectively; By ion being injected in conjunction with the step that forms ion implanted layer in the wafer; With this face, via aforementioned oxide-film, with the step of base wafer applying in conjunction with the ion injection side of wafer; Step with aforementioned ion implanted layer is peeled off as the border is characterized by:

As the aforementioned substrates wafer, use

Silicon single crystal by czochralski-grown, all faces of this wafer, the time will draw high speed by little by little becoming under the situation of low speed at a high speed in growth, for than the OSF zone that takes place annularly more low speed side the n-quadrant and do not contain the silicon wafer of the defect area that is detected by the Cu sedimentation; Or, the time will draw high speed by little by little becoming under the situation of low speed at a high speed in growth, for than the OSF zone that takes place annularly more low speed side, do not contain the defect area that is detected by the Cu sedimentation and contain to exist and result from the silicon wafer in the I zone of the dislocation group of silicon between lattice.

5. the manufacture method of SOI wafer as claimed in claim 4 is characterized by:

As aforementioned in conjunction with wafer, use is by the silicon single crystal of czochralski-grown, all faces of this wafer, the time will draw high speed by little by little becoming under the situation of low speed at a high speed in growth, for than the OSF zone that takes place annularly more low speed side the n-quadrant and do not comprise the silicon wafer of the defect area that is detected by the Cu sedimentation.