JP4380141B2 - Silicon wafer evaluation method - Google Patents

Description

【００７１】
さらに、イオン注入剥離法に基づき、上記ロットの鏡面ウェーハをボンドウェーハとして使用し、ベースウェーハとの結合後に５０ｎｍ厚のＳＯＩ層に加工してＳＯＩウエーハを製造した。
このように製造されたＳＯＩウェーハの表面をパーティクルカウンター（ＫＬＡ−Ｔｅｎｃｏｒ社製Ｓｕｒｆｓｃａｎ ＳＰ−１）により測定したところ、欠陥等はほとんど検出されなかった。さらにその後、５０％弗酸溶液に３０分間無攪拌のまま放置し欠陥密度測定を行った場合でもエッチピット欠陥は検出されなかった。
【００７２】
尚、本発明は、上記実施形態に限定されるものではない。上記実施形態は、例示であり、本発明の特許請求の範囲に記載された技術的思想と実質的に同一な構成を有し、同様な作用効果を奏するものは、いかなるものであっても本発明の技術的範囲に包含される。
【００７３】
例えば、上記実施形態では、イオン注入剥離法によりＳＯＩウエーハを製造する際、本発明に係る評価方法に基づいて合格と判定したものをボンドウエーハとして使用する場合について説明したが、本発明のシリコンウエーハの評価方法は、上記のようにＳＯＩウエーハを製造する場合に限定して適用されるものではない。
【００７４】
例えば、ＳＯＩウエーハの製造に関して言えば、酸化膜を介さずに絶縁性の支持基板、例えば石英、ＳｉＣ、サファイア等の基板に直接貼り合わせてＳＯＩウエーハを製造する場合、また、ＳＩＭＯＸ法、すなわちシリコンウエーハに酸素をイオン注入した後、熱処理してＳＯＩウエーハを製造する場合においても、使用するシリコンウエーハの合否を本発明の評価方法によって的確に判定して、高品質のＳＯＩウエーハを効率的に製造することができる。
また、本発明に係るシリコンウエーハの評価方法は、ＳＯＩウエーハの製造に限らず、エピタキシャルウエーハの製造等、様々なデバイス作製用ウエーハの製造においてシリコンウエーハを評価する際に適用することができる。
【００７５】
【発明の効果】
以上説明したように、本発明に係るシリコンウエーハの評価方法によれば、Ｖ領域、ＯＳＦ領域、巨大転位クラスタ（ＬＳＥＰ、ＬＦＰＤ）領域およびＣｕデポジション欠陥領域を含まないニュートラル領域（Ｎ領域）であることを、迅速、容易に、かつ的確に判定することができる。そして、このような評価方法をＳＯＩウエーハの製造において適用すれば、ＳＯＩ製造工程内で表面に微小ピットが発生しない、優れた電気特性を持つＳＯＩウェーハを高歩留まりで効率的に得ることができる。
【図面の簡単な説明】
【図１】ＳＯＩウエーハの製造において本発明に係る評価方法を適用する場合の一例を示すフロー図である。
【図２】ＳＯＩウエーハの製造において本発明に係る評価方法を適用する場合の他の一例を示すフロー図である。
【図３】初期酸素濃度とＯＳＦ密度との関係、及びそれらとＣｕデポジション欠陥領域との関係示すグラフである。
【図４】本発明で使用することができるシリコン単結晶製造装置の一例を示す概略図である。
【図５】本発明の評価方法により判定し得る領域を示す説明図である。
【図６】（Ａ）単結晶成長速度と結晶切断位置の関係を示す関係図である。
（Ｂ）成長速度と各領域を示す説明図である。
【図７】Ｃｕデポジション評価試料の作製方法を示す説明図である。
【図８】ＳＯＩウエーハの製造工程の一例を示すフロー図である。
【図９】ボンドウエーハとして従来使用されている結晶領域を表す説明図である。
【符号の説明】
１…シリコン単結晶インゴット、 ２…シリコン融液、 ３…湯面、
４…固液界面、 ６…シードチャック、 ７…ワイヤ、 １０…外側断熱材、
１１…内側断熱材、 １２…黒鉛筒、 ２１…ボンドウエーハ、
２２…ベースウエーハ、 ２３…酸化膜（絶縁層）、
２４…イオン注入層、 ２５…剥離ウエーハ、 ２６…ＳＯＩウエーハ、
２７…シリコン活性層（ＳＯＩ層）、 ２８…酸化膜、
３０…単結晶引上げ装置、 ３１…引上げ室、 ３２…ルツボ、
３３…ルツボ保持軸、 ３４…ヒータ、 ３５…断熱材。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for evaluating a silicon wafer, and a method for manufacturing an SOI wafer using a high-quality silicon wafer determined based on the evaluation method.
[0002]
[Prior art]
Conventionally, an SOI wafer in which a silicon active layer (SOI layer) is formed on a support substrate has been widely used as a device substrate. As a method for manufacturing such an SOI wafer, for example, a bonding method in which two silicon wafers are bonded together through an oxide film is known.
FIG. 8 shows an example of a manufacturing process of an SOI wafer by an ion implantation separation method which is one of bonding methods.
[0003]
First, in the first step (1), a bond wafer 21 serving as an SOI layer and a base wafer 22 serving as a support substrate are prepared, and in a subsequent step (2), at least one of the bond wafer 21 and the base wafer 22 is prepared. Oxidizes the wafer surface. Here, the bond wafer 21 is thermally oxidized, and an oxide film 23 having a thickness of 2 nm to 3000 nm, for example, is formed on the surface in consideration of ensuring insulation and heat treatment time.
[0004]
In the step (3), hydrogen ions are ion-implanted from the surface on one side of the bond wafer 21 having the oxide film (insulating layer) 23 formed on the surface. Note that rare gas ions or mixed gas ions of hydrogen ions and rare gas ions may be ion-implanted. Thereby, the ion implantation layer 24 parallel to the surface can be formed inside the wafer at the average ion penetration depth. Note that the depth of the ion implantation layer at this time can be controlled by the thickness of the oxide film 23 and the magnitude of the acceleration voltage at the time of ion implantation, and is reflected in the thickness of the finally formed SOI layer.
[0005]
In the step (4), the ion-implanted surface of the bond wafer 21 and the surface of the base wafer 22 are bonded together via the oxide film 23. For example, by bringing the surfaces of the two wafers 21 and 22 into contact with each other in a clean atmosphere at room temperature, the wafers are bonded to each other without using an adhesive or the like.
[0006]
Next, in step (5), a part of the bond wafer 21 is peeled off by the ion implantation layer 24 by heat treatment. For example, if a bond wafer 21 and a base wafer 22 are bonded and bonded to each other and subjected to a heat treatment at a temperature of about 500 ° C. or higher in an inert gas atmosphere, the separation wafer 25 is caused by crystal rearrangement and bubble aggregation. And SOI wafer 26 (SOI layer 27 + buried oxide film 23 + base wafer 22).
[0007]
In step (6), a bonding heat treatment is applied to the SOI wafer 26. Since the bonding force between the wafers bonded in the bonding step (4) and the peeling heat treatment step (5) is weak to use in the device manufacturing process as it is, a high temperature heat treatment is applied to the SOI wafer 26 as a bonding heat treatment. To give sufficient bond strength. For example, the heat treatment can be performed in an inert gas atmosphere at 1050 ° C. to 1200 ° C. for 30 minutes to 2 hours.
[0008]
In step (7), the oxide film formed on the surface of the SOI wafer 26 is removed by hydrofluoric acid cleaning.
Further, in step (8), oxidation is performed to adjust the thickness of the SOI layer 27 as necessary. Next, in step (9), the oxide film 28 is removed by hydrofluoric acid cleaning, and the thickness of the SOI layer 27 is then removed. Can also be adjusted.
Through the steps (1) to (9) as described above, the SOI wafer 26 in which the silicon active layer 27 is formed on the insulating layer 23 can be manufactured.
[0009]
In the case of manufacturing an SOI wafer as described above, as a bond wafer, a silicon wafer having a surface having a minute pit defect having a size of 50 nm or more is generally used. However, in recent years, the demand for thinning the silicon active layer has increased, and the quality requirements of silicon wafers applicable to this have become strict.
[0010]
Therefore, as a method for reducing defects in the silicon active layer, a so-called neutral region free from defects caused by single crystal growth, such as those using an epitaxial layer, or grown-in defects such as FPD, LSTD, and COP. A material using a silicon single crystal of (N region) has been proposed.
[0011]
For example, an epitaxial layer is formed on a silicon wafer (bond wafer), boron is ion-implanted into the epitaxial layer, and then bonded to a support substrate through an oxide film, and the back surface of the bond wafer is ground and polished to thereby polish the SOI wafer. Has been proposed (see, for example, Patent Document 1).
However, when the wafer having the epitaxial layer formed as described above is used as a bond wafer, defects in the SOI layer are improved, but there is a problem that the manufacturing cost is remarkably increased because the number of steps for growing the epitaxial layer is increased.
[0012]
On the other hand, when a silicon wafer grown in an N region where there is no minute defect such as FPD or COP is used as the bond wafer, it is necessary to precisely control the growth conditions of the silicon single crystal, but an epitaxial layer is formed. There is an advantage that such a process is unnecessary.
[0013]
Here, the N region will be explained. A growth rate V is increased in the crystal axis direction with a CZ puller using a furnace structure (hot zone: HZ) having a large temperature gradient G in the vicinity of a solid-liquid interface in a crystal. It is known that a defect distribution map as shown in FIG. 9 is obtained when the speed is changed from low to low.
In FIG. 9, the V region is a vacancy, that is, a region in which there are many such as recesses and holes generated due to a shortage of silicon atoms, and the I region is a dislocation or excess generated due to the presence of extra silicon atoms. This is a region with a lot of silicon masses. There is a neutral (Neutral, hereinafter abbreviated as N) region where there is no shortage or excess of atoms between the V region and the I region, and the OSF is near the boundary of the V region. It has also been confirmed that defects called oxidation induced stacking faults (Oxidation Induced Stacking Faults) are distributed in a ring shape (hereinafter sometimes referred to as OSF rings) when viewed in a cross section perpendicular to the crystal growth axis. Yes.
[0014]
In general, when the growth rate is relatively high, there are high density of grown-in defects such as FPD, LSTD, COP, etc., which are attributed to voids in which vacancy-type point defects are gathered in the entire crystal diameter direction. The region where these defects exist is the V region. As the growth rate decreases, an OSF ring is generated from the periphery of the crystal, and L / D (Large Dislocation) is considered to be caused by a dislocation loop in which interstitial silicon is gathered outside the ring. Defects (abbreviated symbols, LSEPD, LFPD, etc.) (giant dislocation clusters) exist at a low density, and a region where these defects exist is an I region (sometimes referred to as an L / D region). Furthermore, when the growth rate is slowed down, the OSF ring shrinks to the center of the wafer and disappears, and the entire surface becomes the I region (in FIG. This is an example in which the V region and the I region are greatly separated because they are grown, and the above description does not completely match.)
[0015]
The N region outside the OSF ring between the V region and the I region is a region in which neither FPD, LSTD, or COP caused by holes nor LSEPD or LFPD caused by interstitial silicon exists. Recently, when the N region is further classified, as shown in FIG. 9, an Nv region (a region with many vacancies) adjacent to the outside of the OSF ring and an Ni region (interstitial silicon) adjacent to the I region are provided. It is known that in the Nv region, the amount of precipitated oxygen is large when thermal oxidation is performed, and in the Ni region, there is almost no oxygen precipitation.
Furthermore, very recently, it has also been found that there is a part of the Nv region in which extremely fine defects are detected by the Cu deposition method immediately after the disappearance of OSF (see, for example, Patent Document 4).
[0016]
The Cu deposition method is an evaluation of a wafer that can accurately measure the position of defects in a semiconductor wafer, improve the detection limit for defects in a semiconductor wafer, and accurately measure and analyze even finer defects. Is the law.
Specifically, an insulating film having a predetermined thickness is formed on the wafer surface, the insulating film on the defective portion formed near the surface of the wafer is destroyed, and an electrolytic substance such as Cu is deposited on the defective portion ( Deposition). In other words, in the Cu deposition method, when a potential is applied to an oxide film formed on the wafer surface in a liquid in which Cu ions are dissolved, a current flows through a portion where the oxide film is degraded, and the Cu ions become Cu. This is an evaluation method using the precipitation. It is known that a defect such as COP exists in a portion where the oxide film easily deteriorates.
The defect portion of the Cu-deposited wafer can be analyzed under a condenser lamp or directly with the naked eye to evaluate its distribution and density. Further, it is possible to evaluate the distribution and density of the wafer by using a microscope, a transmission electron microscope (TEM) or a scanning electron microscope ( SEM) or the like can also be confirmed.
[0017]
Conventionally, when a silicon single crystal ingot pulled up from a raw material melt is sliced into a wafer, the N region was only partially present in the wafer plane, but due to recent technological advances, the pulling speed (V) By controlling V / G, which is the ratio of the temperature gradient (G) in the axial direction of the crystal solid-liquid interface, a crystal in which the N region spreads across the entire lateral surface (wafer entire surface) can be manufactured (see FIG. 9).
[0018]
Therefore, also in the manufacture of SOI wafers, as described above, there has been proposed a method using a silicon single crystal wafer that becomes the entire N region as a bond wafer.
For example, when pulling a silicon single crystal by the Czochralski method (CZ method), the ratio (V / G) between the pulling speed V and the temperature gradient G at the crystal solid-liquid interface in the pulling axis direction is controlled within a predetermined range. Then, an SOI wafer using the N region silicon wafer is proposed as a bond wafer by pulling up the N region silicon single crystal (see, for example, Patent Document 2 and Patent Document 3).
[0019]
[Patent Document 1]
JP-A-10-79498 (page 4-6, FIG. 2)
[Patent Document 2]
JP 2001-146498 A (page 5-8)
[Patent Document 3]
JP 2001-44398 A (page 2-4, FIG. 1)
[Patent Document 4]
JP 2002-201093 A
[0020]
[Problems to be solved by the invention]
By the way, in order to confirm that the pulled silicon single crystal ingot is grown in a desired region, when performing an evaluation by a Cu deposition method (Cu deposition evaluation), mirror surface processing of the wafer is essential. In addition, after forming an oxide film on the wafer surface, it is necessary to perform an analysis after performing a process of depositing Cu (these processes are referred to as “Cu deposition process”). Therefore, it takes a considerable number of days to determine the presence or absence of microdefects by the Cu deposition method immediately after pulling up the silicon single crystal ingot, leading to a problem that the lead time is long and the processing cost is high.
[0021]
For example, when an SOI wafer is manufactured by an ion implantation separation method, an oxide film is removed after performing an oxidation process for bonding the bond wafer and the base wafer and an oxidation process for adjusting the thickness of the SOI layer. Therefore, hydrofluoric acid cleaning may be performed. However, even when a silicon single crystal grown in the N region is used as a bond wafer, a defect that the SOI layer is almost entirely or locally broken may occur. In particular, the above-described defects often occur when the SOI layer is formed thin. In the future, when it is required to further reduce the thickness of the SOI layer, even if a silicon wafer grown in such an N region is used as a bond wafer, the SOI layer will be significantly deteriorated. In addition, there is a possibility that the quality of the interlayer insulating oxide film of the SOI layer and the base wafer is impaired.
[0022]
Therefore, the inventors of the present invention, when manufacturing an SOI wafer, include an N region in which no defect region detected by the Cu deposition method (hereinafter, also referred to as “Cu deposition defect region”) exists in the N region. If a silicon single crystal ingot is pulled under such a condition and a silicon wafer obtained from this ingot is used as a bond wafer, an SOI wafer having excellent electrical characteristics is produced without generating micro-pits by hydrofluoric acid cleaning or the like. I thought that I could do it.
[0023]
The present invention has been made in view of the above-described problems, and includes a silicon wafer including a V region, an OSF region, a giant dislocation cluster (LSEP, LFPD) region, and a defect region detected by a Cu deposition method. The main object of the present invention is to provide a silicon wafer evaluation method that can quickly, easily, and accurately determine that it is in a neutral region (N region).
[0024]
[Means for Solving the Problems]
  In order to achieve the above object, according to the present invention, there is provided a silicon wafer evaluation method, wherein the initial oxygen concentration in the silicon wafer is Xppma (ASTM'79), and the wafer is 900 ° C. in a dry oxygen atmosphere. Oxidation treatment for 2 to 4 hours in the temperature range of 1 to 1100 ° C., and then oxidation treatment for 1 to 2 hours in the temperature range of 1100 to 1200 ° C. in a wet oxygen atmosphere containing more water vapor than the dry oxygen atmosphere. OSF maximum density generated on the surface of the wafer by applying Y / cm²When Y ≦ 1.3X²A method for evaluating a silicon wafer is provided, wherein determination is performed based on satisfying −10X..
[0025]
The inventors of the present invention have found that most of the N region silicon wafers in which no defect region is detected by the Cu deposition method are used in the evaluation method as described above.²It was found to satisfy −10X. Therefore, according to this evaluation method, from the relationship between the initial oxygen concentration of the silicon wafer and the maximum OSF density after the two-stage heat treatment, the N region has no defect region detected by the Cu deposition method. This can be easily and accurately determined. Further, such an evaluation method is easier to process than the Cu deposition method because mirror polishing is not necessarily required, and processing time and processing cost can be suppressed.
[0026]
  Although the scene to which such an evaluation method is applied is not particularly limited, for example, the determination by the evaluation method includes at least a pulling step of pulling up a silicon single crystal ingot from a raw material melt, and slicing the ingot to form a silicon wafer. It can be performed at least one of before the slicing step and after the mirror surface processing step in manufacturing the silicon wafer by a slicing step to be obtained and a mirror surface processing step to mirror the silicon wafer.
[0027]
For example, if the evaluation method is applied to a silicon wafer cut out as a sample before slicing the pulled silicon single crystal ingot, the silicon wafer obtained from the entire ingot can be efficiently evaluated. It is possible to quickly and accurately determine whether or not to perform the slicing process.
On the other hand, after the mirror finishing process, evaluation can be performed on mirror-finished wafers arbitrarily extracted from a large number of wafers, and final judgment should be made quickly and with high reliability. Can do.
[0028]
  Further, it is preferable to further determine the presence or absence of a grow-in defect before and after performing the determination by the evaluation method..
  The silicon wafers in the V region and I region where the grown-in defect exists are also Y ≦ 1.3X as described above.²Since −10X may be satisfied, by further determining whether or not there is a grown-in defect, it is possible to more reliably determine that the silicon wafer is an N region in which no Cu deposition defect region exists.
[0029]
  Further, the determination by the evaluation method may be performed before the slicing step, and the evaluation by the Cu deposition method may be performed after the mirror finishing step..
  Mirror finishing is indispensable for evaluation by the Cu deposition method, but the method for obtaining the relationship between the initial oxygen concentration and the maximum OSF density allows quick determination at a stage before the slicing process, and then advances to mirror finishing. Since the wafer has already been mirror-finished at the stage, for example, by performing evaluation using a Cu deposition method on an arbitrarily extracted mirror-finished wafer, the silicon wafer in the desired region has higher reliability. Can be determined.
[0030]
  Furthermore, according to the present invention, there is provided a method for manufacturing an SOI wafer to which the evaluation method is applied. That is, in an SOI wafer manufacturing method in which a silicon active layer is formed on an insulating layer, the silicon wafer evaluation method is determined as an N region silicon wafer in which no defect region detected by the Cu deposition method exists. Is used as a wafer for forming a silicon active layer of the SOI wafer, and a method for manufacturing an SOI wafer is provided..
[0031]
Thus, if an SOI wafer is manufactured by using, as the wafer for forming the silicon active layer of the SOI wafer, what is determined as the silicon wafer in the N region where the Cu deposition defect region does not exist by the evaluation method according to the present invention, for example, Even when the thickness of the silicon active layer is 200 nm or less, the silicon active layer is not destroyed by the hydrofluoric acid cleaning or the like and the silicon active layer is destroyed, and a high quality SOI wafer is manufactured. Can do.
[0032]
  In this case, the SOI wafer can be manufactured by an ion implantation delamination method..
  When an SOI wafer is manufactured by an ion implantation delamination method using a silicon wafer determined as a desired wafer by the evaluation method, the silicon active layer can be made extremely thin and uniform in thickness, and there is no defect. An extremely high quality SOI wafer can be manufactured.
[0033]
  Further, as the silicon wafer for forming the silicon active layer, one having an initial oxygen concentration of 15 ppma (ASTM'79) or more is preferably used..
  If it has such an initial oxygen concentration, the OSF necessary for the determination can be sufficiently generated in the oxidation process for performing the evaluation, and impurities that are adversely affected in the silicon active layer can be removed. The gettering ability to perform can be fully exhibited.
[0034]
Hereinafter, the present invention will be described in more detail.
The present inventors have raised the silicon single crystal ingot so that it becomes an N region where no Cu deposition defect region exists, and there is no defect region detected by the Cu deposition method until this is sliced into a mirror wafer. Intensive research was conducted on a method that can easily and reliably evaluate the existence of a non-existing N region silicon wafer without using the Cu deposition method.
As a result, the presence of minute defects detected by the Cu deposition method can be determined by using the density of OSF forcibly generated by subjecting the silicon wafer to a predetermined heat treatment and the initial oxygen concentration as a criterion. It was found that evaluation can be performed easily and accurately.
[0035]
Specifically, the present inventors perform two-step oxidation treatment at a predetermined temperature and time in a dry oxygen atmosphere and a wet oxygen atmosphere, and then remove the oxide film with a chemical solution to increase the OSF. It was confirmed that the sensitivity was detected.
Here, the present inventors set the OSF maximum density (pieces / cm 2) in the wafer plane.²) And the initial oxygen concentration of the wafer ppma (ASTM'79). At that time, the OSF density increases as the initial oxygen concentration increases, and when the OSF gradually decreases the crystal from high speed to low speed, the OSF shows the maximum density in the OSF region, and part of the V region, Nv region, and I region. It was confirmed that it was generated at a low density but decreased as it approached the Ni region.
Further, the boundary between the N region where the Cu deposition defect exists and the N region where the Cu deposition defect is free was investigated.
[0036]
As a result, a graph as shown in FIG. 3 is obtained, and the maximum OSF density is Y (pieces / cm²), When the initial oxygen concentration is Xppma (ASTM'79), the N region free of Cu deposition defects is Y ≦ 1.3X²It was found that it substantially corresponds to the OSF maximum density region that satisfies the relationship of −10X. So, Y ≦ 1.3X²Based on satisfying −10X, whether or not the defect region detected by the Cu deposition method is an N region silicon wafer can be determined quickly and with high sensitivity without performing mirror polishing or the like. As a result, the present invention has been completed.
[0037]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be specifically described with reference to the accompanying drawings. The silicon wafer evaluation method according to the present invention is not particularly limited in use of the silicon wafer to be evaluated, and can be applied to any silicon wafer. However, as a preferred embodiment, a silicon single crystal ingot is used. The case of applying in the process up to the manufacturing of the SOI wafer will be described.
[0038]
  FIG. 1 is a flowchart showing an example in which the evaluation method of the present invention is adopted in the process from manufacturing a silicon single crystal ingot to manufacturing an SOI wafer.
  First, in the first crystal manufacturing step (A), that is, the silicon single crystal pulling step, the silicon single crystal ingot is pulled from the raw material melt by the Czochralski method (CZ method). At this time, for example, using a single crystal pulling apparatus as shown in FIG.ShiThe silicon single crystal is grown without any defect region.
[0039]
The single crystal pulling apparatus 30 will be described. A pulling chamber 31, a crucible 32 provided in the pulling chamber 31, a heater 34 arranged around the crucible 32, a crucible holding shaft 33 for rotating the crucible 32, and its A rotation mechanism (not shown), a seed chuck 6 that holds a silicon seed crystal, a wire 7 that pulls up the seed chuck 6, and a winding mechanism (not shown) that rotates or winds the wire 7 are provided. . A heat insulating material 35 is disposed around the outside of the heater 34.
[0040]
The crucible 32 is provided with a quartz crucible on the inner side containing the silicon melt (hot water) 2 and on the outer side with a graphite crucible. A magnet (not shown) is installed outside the pulling chamber 31 in the horizontal direction, and a magnetic field in the horizontal direction or the vertical direction is applied to the silicon melt 2 to suppress convection of the melt and stabilize the single crystal. The so-called MCZ method is often used to achieve growth.
[0041]
Further, a cylindrical graphite tube (heat shield plate) 12 is provided so as to surround the grown silicon single crystal 1, and an annular outer heat insulating material 10 is provided on the outer periphery in the vicinity of the solid-liquid interface 4 of the crystal, and on the inner side. Inner heat insulating materials 11 are provided. These heat insulating materials 10 and 11 are installed with an interval of 2 to 20 cm between the lower end thereof and the molten metal surface 3 of the silicon melt 2. By providing such a graphite tube (heat shield plate) 12 and the heat insulating materials 10 and 11, the difference between the temperature gradient Gc [° C./cm] at the crystal central portion and the temperature gradient Ge at the crystal peripheral portion becomes small. The furnace temperature can also be controlled so that the temperature gradient around the crystal is lower than the crystal center.
Further, a cooling cylinder 14 is provided on the graphite cylinder 12 and forced cooling is performed by flowing a cooling medium. Further, a cylindrical cooling means for blowing a cooling gas or blocking the radiant heat to cool the single crystal may be provided.
[0042]
In order to manufacture a silicon single crystal using such a single crystal pulling apparatus 30, first, a high-purity polycrystalline silicon raw material of silicon is heated to a melting point (about 1420 ° C.) or higher in a crucible 32 to be melted. Next, the tip of the seed crystal is brought into contact with or immersed in the approximate center of the surface of the melt 2 by unwinding the wire 7. Thereafter, the crucible holding shaft 33 is rotated and the wire 7 is wound while being rotated. As a result, the seed crystal is also pulled up while rotating to start growing a single crystal. Thereafter, a substantially cylindrical silicon single crystal ingot 1 can be obtained by appropriately adjusting the pulling speed and temperature.
[0043]
In order to grow a silicon single crystal which is an N region and does not have a Cu deposition defect region, for example, when the growth rate of the silicon single crystal being pulled is gradually reduced, it remains after the OSF ring disappears. The crystal is controlled by controlling the growth rate between the growth rate of the boundary where the defect region detected by the Cu deposition method disappears and the growth rate of the boundary where the interstitial dislocation loop is generated when the growth rate is further reduced. Cultivate. That is, when the growth rate of the silicon single crystal being pulled is gradually decreased from a high speed to a low speed from the crystal shoulder to the straight tail, the V region, the OSF region, the Cu region according to the growth rate V as shown in FIG. Each phase is formed in the order of a deposition defect region, an Nv region, a Ni region, and an I region (giant dislocation cluster generation region). Among the N regions, a defect region detected by Cu deposition remaining after the OSF ring disappears The single crystal is grown by controlling the growth rate between the growth rate at the boundary where the annihilation disappears and the growth rate at which the I region is generated when the growth rate is gradually reduced. According to such a method, there is no V region defect such as FPD, I region defect such as giant dislocation cluster (LSEPD, LFPD), no OSF region, and no fine defect detected by the Cu deposition method. The silicon single crystal ingot in the region can be pulled up.
[0044]
Note that the oxygen concentration in the silicon single crystal may be set as appropriate according to the required gettering ability and the like, but if the oxygen concentration is too low, it is necessary for the determination in the oxidation treatment for later evaluation. Since there is a possibility that OSF cannot be generated sufficiently, it is preferable to control the initial oxygen concentration to be 15 ppma (ASTM'79) or more. In addition, with such an oxygen concentration, gettering ability for removing impurities and the like can be sufficiently exhibited in a subsequent device manufacturing process. The upper limit of the oxygen concentration is not particularly limited, but about 30 ppma is appropriate considering, for example, oxygen precipitates.
[0045]
Next, the pulled silicon single crystal ingot is sliced to obtain a wafer. However, as described above, since extremely strict control is required to grow the N region not including the Cu deposition defect region, it is not always aimed. A single crystal in a region cannot always be grown.
Therefore, it is necessary to inspect whether or not a desired single crystal has been manufactured, and the evaluation method according to the present invention (hereinafter sometimes referred to as “OSF evaluation”) is applied before the slicing step to determine (a ).
Specifically, for example, several wafers as samples are cut out from both ends of the ingot straight body, and lapping or the like is performed as necessary, and then the initial oxygen concentration X (ppma) is measured.
[0046]
Next, the sample silicon wafer is subjected to an oxidation treatment (dry oxidation treatment) for 2 hours to 4 hours in a temperature range of 900 ° C. to 1100 ° C. in a dry oxygen atmosphere. Further, oxidation treatment (wet oxidation treatment) is performed in a wet oxygen atmosphere containing more water vapor than the dry oxygen atmosphere in a temperature range of 1100 ° C. to 1200 ° C. for 1 hour to 2 hours (hereinafter referred to as such two-stage oxidation). The process may be referred to as “OSF heat treatment”), and the OSF is forcibly generated.
[0047]
After such two-stage heat treatment (OSF heat treatment), the maximum OSF density generated on the surface of the wafer is Y (pieces / cm²), Y ≦ 1.3X²A pass / fail decision is made based on satisfying −10X. In other words, if this equation is satisfied, the silicon wafer obtained by slicing the pulled silicon single crystal ingot is very likely to be an N region in which no Cu deposition defect region exists. It can be transferred to the process. On the other hand, when the above formula is not satisfied, it is expected that a silicon single crystal in a region different from the target is grown, and therefore, it is possible to take measures such as stopping the transfer to the slicing step. In addition, as shown in FIG. 3, although it is slight, Y ≦ 1.3X²Even if it does not satisfy −10X, there is an N region where there is no Cu deposition defect region. Therefore, if it is determined to be unacceptable, a determination is made here or later by the Cu deposition method, and again It can also be confirmed.
Thus, before slicing the ingot, it can be quickly determined whether or not the crystal has no Cu deposition defect region, which is extremely convenient in terms of the process.
[0048]
On the other hand, even if the V region or I region silicon single crystal is grown out of the N region for some reason, when the evaluation method as described above is performed, Y ≦ 1.3X²There is a possibility of satisfying −10X.
Therefore, it is desirable to use another wafer for the sample cut from both ends of the ingot, further evaluate the grown-in defects present in each of the V region and the I region, and determine the presence or absence of those defects (b). .
Specifically, the presence or absence of V region defects such as FPD and I region defects such as giant dislocation clusters (LSEPD and LFPD) is determined by etching a sample wafer using a predetermined etching solution. Just do it. In addition, you may perform evaluation about such a grow-in defect before OSF evaluation (a).
[0049]
As a result of these evaluations (a) and (b), if it is determined that the pulled silicon single crystal ingot is not an V region or an I region but an N region in which no Cu deposition defect region exists (pass), CW It moves to a manufacturing process (B) and slices an ingot in a slicing process, and obtains a silicon wafer. Thereafter, chamfering, lapping, etching and the like are performed on these silicon wafers to obtain a wafer (CW) flattened by lapping and etching.
[0050]
In the subsequent PW manufacturing process (C), that is, the mirror finishing process, the silicon wafer is mirror-polished using a polishing apparatus to obtain a mirror wafer (PW).
And since the silicon wafer mirror-finished here was obtained from the same ingot as the one determined to pass in the previous evaluations (a) and (b) for the sample cut from both ends of the ingot, The possibility of the N region where there is no Cu deposition defect region is very high, but the entire ingot is not necessarily grown in the same region.
[0051]
Therefore, if necessary, it is desirable to apply the previous evaluation method again to a sample that is arbitrarily extracted from a number of mirror-polished wafers (PW) after the mirror-finishing step (PW sampling OSF evaluation (c)). By performing such a sampling evaluation, it can be more reliably determined that the other specular wafer obtained from the same ingot is also a desired region. The specific evaluation procedure is the same as described above.
For the same reason, if it is determined again whether or not there is a grow-in defect (FPD, LFPD, LSEP, etc.) (PW sampling grow-in defect evaluation (d)), the reliability can be further improved.
[0052]
On the other hand, as shown in FIG. 2, after the mirror surface processing step, instead of OSF evaluation, evaluation by a Cu deposition method may be performed (PW sampling Cu deposition defect evaluation (e)).
The evaluation method according to the present invention reflects the defects detected by the Cu deposition method with high sensitivity, but does not completely match the evaluation results by the Cu deposition method. In addition, as described above, the evaluation by the Cu deposition method requires mirror finishing, and it takes time to determine, but at this stage, the wafer is already mirror-finished. Therefore, if a mirror wafer is arbitrarily extracted after the mirror processing step and evaluated by the Cu deposition method, it is relatively easy to determine that the silicon wafer is in a desired region with higher reliability. be able to.
In addition, after performing the evaluation by the Cu deposition method, it may be confirmed again that it is neither the V region nor the I region by determining whether or not there is a grow-in defect similarly to the above (d).
[0053]
If the sampling evaluation ((c) or (e) and (d)) as described above is judged to pass, all silicon wafers obtained from the same ingot are detected by the Cu deposition method. It can be determined as an N region silicon wafer (accepted product) in which no defect region exists.
[0054]
As described above, according to the evaluation method of the present invention, before slicing the pulled ingot, it is easily and accurately confirmed that the silicon single crystal in the N region where no Cu deposition defect region exists can be pulled up. After making such a determination, it is possible to proceed to a subsequent slicing step or the like to reliably manufacture a silicon wafer in a desired region. Accordingly, it is possible to shorten the waiting time for the evaluation result before entering the step of actually slicing the ingot, and the process can be made more efficient. In addition, it is possible to minimize the determination that there is a Cu deposition defect after slicing, mirror polishing, or the like.
[0055]
Then, if an SOI wafer is manufactured by using, as described above, a wafer that forms a silicon active layer of an SOI wafer, what is determined as a silicon wafer of an N region where there is no defect region detected by the Cu deposition method as described above, An extremely high quality SOI wafer can be obtained.
For example, when manufacturing an SOI wafer by an ion implantation delamination method, if a wafer determined to be acceptable by the evaluation method according to the present invention is used as a bond wafer, even if the silicon active layer is formed thinly to be 200 nm or less, The silicon active layer is not destroyed by the hydrofluoric acid cleaning, and an electrically reliable SOI wafer can be efficiently manufactured with a high yield.
[0056]
【Example】
EXAMPLES Hereinafter, although an Example is given and this invention is demonstrated, this invention is not limited to this.
(Experiment 1): Confirmation of criteria based on OSF density and initial oxygen concentration
Using the single crystal manufacturing apparatus 30 as shown in FIG. 4, the crystal growth rate was gradually decreased as follows, and the growth rate at the boundary of each region was examined.
First, 150 kg of polycrystalline silicon as a raw material was charged in a quartz crucible having a diameter of 24 inches (600 mm), and a silicon single crystal ingot having a diameter of 8 inches (200 mm) was pulled in the range from the V region to the N region. The ingot was cut and divided into crystal blocks, and then each crystal block was sliced sequentially from the head side in the crystal axis direction to obtain a wafer. At this time, a number was printed by laser marking so that the cutting order could be understood and processed into a mirror surface wafer.
[0057]
Then, two adjacent mirror wafers were extracted from each crystal block unit lot, and after one OSF heat treatment, the oxide film was removed by Secco etching to confirm the OSF distribution. In addition, OSF evaluation is performed by dry oxidation treatment for 3 hours in a temperature range of 1000 ° C., and then pyrooxidation treatment (wet oxidation treatment) for 100 minutes in a temperature range of 1150 ° C., followed by cooling (800 ° C. in and out), After removing the oxide film, the density measurement and the distribution were confirmed.
In addition, after the thermal oxide film was formed on the other sheet, a Cu deposition method was performed to confirm the distribution of oxide film defects. The evaluation conditions are as follows.
1) Oxide film: 25 nm
2) Electric field strength: 6 MV / cm
3) Voltage application time: 5 minutes
[0058]
OSF maximum density Y (pieces / cm²) And the initial oxygen concentration Xppma (ASTM'79), and the correlation between these and the Cu deposition defects, the same relationship as that shown in FIG. One condition is Y ≦ 1.3X²It was found to be in the range of -10X.
[0059]
(Experiment 2): Confirmation of pulling conditions
The 24 inch quartz crucible of the pulling apparatus shown in FIG. 4 is charged with 150 kg of raw material polycrystalline silicon, and the growth rate ranges from 0.7 mm / min to 0.3 mm / min from the crystal head to the tail of a 210 mm diameter ingot. Control was made to gradually decrease. The oxygen concentration was 23 to 26 ppma (ASTM'79).
[0060]
Then, as shown in FIGS. 6 (A) and 6 (B), it is vertically cut in the direction of the crystal axis from the head to the tail of the pulled single crystal, and then four wafer-shaped mirror-finished samples with a diameter of 200 mm are produced. did.
Three out of the four samples were measured for wafer lifetime (WLT) measurement (measuring instrument: SEMILAB WT-85) and seco-etching, distribution of each region of V region, OSF region, I region, FPD, LEP distribution The situation and the OSF generation state by the two-step heat treatment were investigated, and the growth rate of each region boundary was confirmed.
Furthermore, one of the samples cut vertically in the crystal axis direction is cut into a 200 mmφ wafer shape, and one is mirror-finished, a thermal oxide film is formed on the wafer surface, Cu deposition treatment is performed, and oxidation is performed. The distribution of film defects was confirmed.
Details in this experiment are as follows.
[0061]
(1) An ingot with a diameter of 210 mm is cut into blocks with a length of every 10 cm in the direction of the crystal axis, and then cut into pieces in the direction of the crystal axis, and then, as shown in FIG. After punching into a (8 inch) cylindrical shape, four wafer-shaped mirror-finished samples were finished.
[0062]
(2) Of the above samples, the first sample was heat treated in a wafer heat treatment furnace at 620 ° C. for 2 hours (nitrogen atmosphere), followed by 800 ° C. for 4 hours (nitrogen atmosphere) and 1000 ° C. for 16 hours (dry oxygen atmosphere). After performing the step heat treatment, it was cooled and a WLT map by SEMILAB WT-85 was prepared.
The second sheet was mirror-etched and then seco-etched to observe the distribution of FPD and LEP.
[0063]
(3) For the third sheet, after the OSF heat treatment, the oxide film was removed after seco etching, and the OSF distribution state was confirmed. In addition, OSF evaluation was performed after dry oxidation treatment was performed for 3 hours in a temperature range of 1000 ° C., and then wet oxidation treatment was performed for 100 minutes in a temperature range of 1150 ° C. (cooling in and out at 800 ° C.), and the oxide film was removed with a chemical The density measurement and the distribution were confirmed.
[0064]
(4) For the fourth sheet, a Cu deposition process was performed on the wafer surface after forming the thermal oxide film, and the distribution of oxide film defects was confirmed. The evaluation conditions are as follows.
1) Oxide film: 25 nm
2) Electric field strength: 6 MV / cm
3) Voltage application time: 5 minutes
[0065]
Experimental result
From the above experiments, the V region, the OSF region, the N region, and the I region were specified, and the maximum density of OSF in each region was measured.
V region: 220 / cm²
OSF area: 2259 / cm²
Cu deposition defect area: 1283 / cm²
Cu deposition defect free N region: 856 / cm²
Non-deposited N region: 0 / cm²
I region: 48 / cm²
[0066]
Furthermore, from the above results, the growth rate of each region boundary of the V region, the OSF region, the N region, and the I region was confirmed.
V region / OSF region boundary: 0.523 mm / min
OSF extinction boundary: 0.510 mm / min
Cu deposition defect disappearance boundary: 0.506 mm / min
Precipitation N region / non-deposition N region boundary: 0.497 mm / min
Non-deposited N region / I region boundary: 0.488 mm / min
From these results, in the crystal pulling apparatus used this time, in order to grow a silicon single crystal so as to be an N region in which no Cu deposition defect region exists, the growth rate is 0.506 to 0.488 mm / min. It turned out that it only has to be set to be within the range.
[0067]
(Experiment 3): Production of SOI wafer
With the same pulling device as Experiment 1 shown in FIG. 4, Y ≦ 1.3X²-10X (23 ≦ X ≦ 25: Initial oxygen concentration (ppma)) is set so that the growth rate from the straight body portion 10 cm to the straight body tail portion is set to 0.50 to 0.49 mm / min. The single crystal was pulled up.
Then, the pulled up crystal of 110 cm in length is cut into 10 cm lengths, each crystal block except the head 10 cm is processed into a mirror-finished wafer, and the mirror wafer is arbitrarily extracted from the unit lot, and then the initial oxygen concentration, Each quality of FPD, LFPD, LSEP, OSF by two-step heat treatment, Cu deposition defect, and oxide film breakdown voltage (C mode) was evaluated. In addition, when the oxide film withstand voltage characteristics are evaluated, the C-mode measurement conditions are as follows.
1) Oxide film: 25 nm
2) Measuring electrode: phosphorus-doped polysilicon
3) Electrode area: 8mm²
4) Judgment current: 1 mA / cm²
[0068]
FPD: No generation of all crystal blocks
LFPD, LSEP: No crystal block generation
Cu deposition defect: no crystal block generated
Oxide breakdown voltage (C mode): 100% of all blocks in crystal
[0069]
  Table 1 shows the initial oxygen concentration by sampling from each unit lot and the results of OSF evaluation after two-stage heat treatment.InShow. In the evaluation, the mirror wafer was divided into ½ size.
  From Table 1, Y ≦ 1.3X in all blocks²It was found to satisfy −10X.
[0070]
[Table 1]

[0071]
Furthermore, based on the ion implantation delamination method, the mirror wafer of the above lot was used as a bond wafer, and after bonding with the base wafer, it was processed into an SOI layer having a thickness of 50 nm to produce an SOI wafer.
When the surface of the SOI wafer manufactured in this way was measured with a particle counter (Surfscan SP-1 manufactured by KLA-Tencor), almost no defects were detected. Further, etch pit defects were not detected even when the defect density was measured by leaving the sample in a 50% hydrofluoric acid solution for 30 minutes without stirring.
[0072]
The present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and the present invention has substantially the same configuration as the technical idea described in the claims of the present invention, and any device that exhibits the same function and effect is the present invention. It is included in the technical scope of the invention.
[0073]
For example, in the above-described embodiment, when manufacturing an SOI wafer by the ion implantation delamination method, a case where a wafer determined to be acceptable based on the evaluation method according to the present invention is used as a bond wafer has been described. This evaluation method is not limited to the case of manufacturing an SOI wafer as described above.
[0074]
For example, in the case of manufacturing an SOI wafer, when an SOI wafer is manufactured by directly bonding to an insulating support substrate such as quartz, SiC or sapphire without an oxide film, the SIMOX method, that is, silicon Even when oxygen is ion-implanted into a wafer and heat-treated to produce an SOI wafer, the pass / fail of the silicon wafer to be used is accurately judged by the evaluation method of the present invention, and a high-quality SOI wafer is efficiently produced. can do.
The silicon wafer evaluation method according to the present invention is not limited to the manufacture of SOI wafers, but can be applied to the evaluation of silicon wafers in the manufacture of various wafers for device fabrication such as the manufacture of epitaxial wafers.
[0075]
【The invention's effect】
As described above, according to the silicon wafer evaluation method of the present invention, the V region, the OSF region, the giant dislocation cluster (LSEP, LFPD) region, and the neutral region (N region) that does not include the Cu deposition defect region. It can be determined quickly, easily and accurately. If such an evaluation method is applied in the manufacture of SOI wafers, an SOI wafer having excellent electrical characteristics in which no micro-pits are generated on the surface in the SOI manufacturing process can be obtained efficiently with a high yield.
[Brief description of the drawings]
FIG. 1 is a flowchart showing an example of applying an evaluation method according to the present invention in the manufacture of an SOI wafer.
FIG. 2 is a flowchart showing another example in the case of applying the evaluation method according to the present invention in the manufacture of an SOI wafer.
FIG. 3 is a graph showing the relationship between the initial oxygen concentration and the OSF density and the relationship between them and the Cu deposition defect region.
FIG. 4 is a schematic view showing an example of a silicon single crystal manufacturing apparatus that can be used in the present invention.
FIG. 5 is an explanatory diagram showing regions that can be determined by the evaluation method of the present invention.
FIG. 6A is a relationship diagram showing the relationship between single crystal growth rate and crystal cutting position.
(B) It is explanatory drawing which shows a growth rate and each area | region.
FIG. 7 is an explanatory view showing a method for producing a Cu deposition evaluation sample.
FIG. 8 is a flowchart showing an example of a manufacturing process of an SOI wafer.
FIG. 9 is an explanatory diagram showing a crystal region conventionally used as a bond wafer.
[Explanation of symbols]
1 ... Silicon single crystal ingot, 2 ... Silicon melt, 3 ... Hot water surface,
4 ... Solid-liquid interface, 6 ... Seed chuck, 7 ... Wire, 10 ... Outer insulation,
11 ... Inner heat insulating material, 12 ... Graphite cylinder, 21 ... Bond wafer,
22 ... Base wafer, 23 ... Oxide film (insulating layer),
24 ... Ion implantation layer 25 ... Peeling wafer 26 ... SOI wafer
27 ... Silicon active layer (SOI layer), 28 ... Oxide film,
30 ... Single crystal pulling device, 31 ... Pulling chamber, 32 ... Crucible,
33 ... crucible holding shaft, 34 ... heater, 35 ... heat insulating material.

Claims (4)

A silicon wafer evaluation method, wherein an initial oxygen concentration in a silicon wafer is Xppma (ASTM'79) of 15 ppma (ASTM'79) or more and 30 ppma or less , and the wafer is subjected to 900 to 1100 ° C in a dry oxygen atmosphere. The oxidation treatment is performed for 2 to 4 hours in the temperature range, and then the oxidation treatment is performed for 1 hour to 2 hours in the temperature region of 1100 ° C. to 1200 ° C. in a wet oxygen atmosphere containing more water vapor than the dry oxygen atmosphere. When the maximum OSF density generated on the surface of the wafer by Y is Y / cm ² , there is no defect region detected by the Cu deposition method on the basis of satisfying Y ≦ 1.3X ² −10X. A method for evaluating a silicon wafer, comprising determining whether the silicon wafer is in a region.   The determination by the evaluation method is performed by at least a pulling process for pulling up a silicon single crystal ingot from a raw material melt, a slicing process for slicing the ingot to obtain a silicon wafer, and a mirror finishing process for mirroring the silicon wafer. 2. The method for evaluating a silicon wafer according to claim 1, wherein the evaluation is performed at least one of before the slicing step and after the mirror finishing step when manufacturing a wafer.   3. The method for evaluating a silicon wafer according to claim 2, wherein the presence or absence of a grown-in defect is further determined before and after the determination by the evaluation method.   4. The method for evaluating a silicon wafer according to claim 2, wherein the evaluation by the evaluation method is performed before the slicing step, and the evaluation by the Cu deposition method is performed after the mirror finishing step.

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