JP6512184B2 - Method of manufacturing silicon wafer - Google Patents

Description

  The present invention relates to a method of manufacturing a silicon wafer.

  A silicon wafer (hereinafter sometimes referred to as "wafer") used as a substrate of a semiconductor device is generally cut out from a silicon single crystal grown by the Czochralski method (hereinafter sometimes referred to as "CZ method"). And manufactured through processes such as polishing. In crystals grown by the CZ method, crystal defects called grown-in defects may occur.

FIG. 1 is a longitudinal sectional view of a pulled-up silicon single crystal, and schematically shows an example of the relationship between defect distribution and V / G. V is a pulling rate of the silicon single crystal, and G is a temperature gradient in the growth direction of the silicon single crystal immediately after pulling.
The temperature gradient G is considered to be approximately constant due to the thermal characteristics of the CZ furnace's hot zone structure. Therefore, V / G can be controlled by adjusting the pulling speed V. In addition, FIG. 1 cut | disconnected the silicon single crystal grown making V / G fall gradually, cut it along the central axis, Cu was made to adhere to the cross section, and it observed by the X-ray topographic method after heat processing The results are shown schematically.

In FIG. 1, COP (Crystal Originated Particle) is an aggregate of vacancies in which atoms that should constitute a crystal lattice are lacking when growing a silicon single crystal. In addition, dislocation clusters are aggregates of interstitial silicon excessively incorporated between crystal lattices.
When such COP is incorporated into an oxide film when the wafer surface is thermally oxidized, the GOI (Gate Oxide Integrity) characteristics of the semiconductor element are degraded. Dislocation clusters also cause device characteristic failure.
Therefore, in order to solve such problems, it is conceivable to adjust the pulling rate V and the like to grow a silicon single crystal which does not contain COP and dislocation clusters.

Such a silicon single crystal, OSF shown in FIG. 1 (Oxidation induced Stacking Fault: oxygen induced stacking faults) region, P _V region will include at least one region of the P _I area. P _V region is close to the COP is an aggregate of vacancy, vacancy type point defects are dominant defect-free region. Also, P _I area is adjacent to the dislocation clusters, interstitial silicon type point defects are dominant defect-free region.

However, even a wafer consisting of a defect-free area containing neither COP nor dislocation clusters is not a perfect defect-free wafer.
P _I area does not include the most oxygen precipitation nuclei in as-grown state, the oxygen precipitate be subjected to a heat treatment hardly occurs.
However, the OSF region is adjacent to the region where COP occurs even if it is a defect-free region, and contains plate-like oxygen precipitates (OSF nuclei) in an as-grown state. For this reason, when thermally oxidizing at a high temperature (generally, 1000 ° C. to 1200 ° C.), the OSF nuclei become manifest as OSF. Also, _{P V} region includes oxygen precipitation nuclei in as-grown state, low and high temperatures (e.g., 800 ° C. and 1000 ° C.) when subjected to heat treatment in two stages of easily oxygen precipitates occurs.
Defects potentially present in such OSF region and _{P V} region, relative to the wafer in as-grown state, reactive ion etching (Reactive Ion Etching: RIE) by the applying, OSF nuclei and _{P V} region Can be detected by making the oxygen precipitate nuclei present on the surface of the substrate as protrusions on the etching surface. Hereinafter, defects that can be detected by RIE are referred to as RIE defects.

By the way, although the RIE defects potentially present in the wafer are generated when the heat treatment is performed under specific conditions, the influence on the yield of the device can not be ignored. For example, when an OSF is generated on the surface of a wafer, it causes leakage current and degrades device characteristics. Also, a possibility of oxygen precipitation nuclei of P _V regions to generate oxygen precipitates during the heat treatment in a device manufacturing process, when the oxygen precipitate is left to the active layer of the element of the device, the leakage current in the device is generated There is.
Therefore, a method of manufacturing a wafer capable of suppressing the influence on the device yield has been studied (see, for example, Patent Document 1).

In the manufacturing method of Patent Document 1, and growing a silicon single crystal containing only at least one region of the P _V region and the P _I area, 1300 ° C. higher than 1400 ° C. or less with respect to the wafer sliced from the silicon single crystal By performing the rapid thermal processing, the RIE defects are eliminated over a depth of at least 1 μm from the wafer surface.

Patent No. 5578172 gazette

  However, in the manufacturing method as described in Patent Document 1, all the wafers are heat-treated at a temperature higher than 1300 ° C. regardless of the quality of the wafers. Therefore, for example, the heat treatment at Ta ° C. For wafers that can be reduced, heat treatment may be performed at Tb ° C. lower than Ta ° C. or at Tc ° C. considerably higher. In the case of heat treatment at Tb ° C., RIE defects can not be sufficiently reduced, and in the case of heat treatment at Tc ° C., although RIE defects can be sufficiently reduced, excess load is applied to the heat treatment apparatus due to excessive heating. The heat treatment may not be performed at an appropriate temperature depending on the quality of the

  An object of the present invention is to provide a method for producing a silicon wafer capable of producing a silicon wafer having a sufficiently reduced RIE defect by an appropriate heat treatment according to the quality before the heat treatment.

  As a result of intensive studies, the inventors have found that silicon wafers that do not contain COP and dislocation clusters differ in heat treatment conditions that can sufficiently reduce RIE defects depending on the state of occurrence of OSF before heat treatment. It has been completed.

  That is, in the method for producing a silicon wafer according to the present invention, a growing step of growing a silicon single crystal free of COP and dislocation clusters by the Czochralski method, and an OSF generation state of an evaluation wafer obtained from the silicon single crystal In the OSF evaluation step of evaluating the and, when an OSF is present in the evaluation wafer, an RTO process is performed on a silicon wafer obtained from the same silicon single crystal as the evaluation wafer under conditions of 1310 ° C. or higher And the heat treatment step of performing the RTO treatment on the silicon wafer under the condition of less than 1310.degree.

Here, the RTO (Rapid Thermal Oxidation) treatment is a rapid heating / rapid cooling heat treatment performed in an oxidizing atmosphere.
According to the present invention, RIE defects can be sufficiently reduced in any case by RTO processing under different conditions depending on the presence or absence of OSF. Therefore, a silicon wafer with sufficiently reduced RIE defects can be manufactured by appropriate heat treatment according to the quality before heat treatment.

The method for manufacturing a silicon wafer according to the present invention includes an RIE defect density evaluation step of evaluating the RIE defect density of another evaluation wafer obtained from the same silicon single crystal as the evaluation wafer having no OSF, wherein the heat treatment step When the RIE defect density is 5 × 10 ⁶ / cm ³ or more, the RTO process is performed on a silicon wafer obtained from the same silicon single crystal as the other evaluation wafer under the conditions of 1270 ° C. or more, and the RIE defect density is In the case of less than 5 × 10 ⁶ pieces / cm ^3, it is preferable to perform the RTO treatment on the silicon wafer under the conditions of 1250 ° C. or higher.

  According to the present invention, RIE defects can be sufficiently reduced in any case by performing RTO processing under different conditions according to the RIE defect density for a silicon wafer in which no OSF is present.

The schematic diagram which shows an example of the relationship between the defect distribution and V / G in a silicon single crystal. The schematic diagram which shows the structure of the pulling-up apparatus which concerns on one Embodiment of this invention. The schematic diagram which shows the structure of the heat processing apparatus in the said one Embodiment. The figure which shows the temperature profile of RTO process in the said one Embodiment. The figure which shows the relationship between RTO process temperature in Experiment 1 which concerns on the Example of this invention, and the in-plane largest RIE defect density before and behind RTO process. The figure which shows the relationship between RTO process temperature in Experiment 2 of the said Example, and the in-plane largest RIE defect density before and behind RTO process.

One embodiment of the present invention will be described with reference to the drawings.
The wafer manufacturing method of the present embodiment includes a growth step of growing a silicon single crystal free of COP and dislocation clusters by the CZ method, and OSF evaluation of evaluating the generation situation of OSF of the evaluation wafer obtained from the silicon single crystal. In the process and the RIE defect density evaluation process for evaluating the RIE defect density of other evaluation wafers obtained from the same silicon single crystal as the evaluation wafer without the OSF, and the evaluation results in the OSF evaluation process and the RIE defect density evaluation process And a heat treatment step of performing RTO processing on a silicon wafer obtained from the same silicon single crystal as the evaluation wafer.
In the following, the pulling apparatus used in the growth step and the heat treatment apparatus used in the heat treatment step will be described, and then the details of the wafer manufacturing method will be described.

[Device configuration]
[Configuration of pulling apparatus]
As shown in FIG. 2, the pulling device 1 is a device used in the CZ method, and includes a pulling device main body 2 and a control unit 3.
The pulling apparatus body 2 includes a chamber 21, a crucible 22 disposed at the center of the chamber 21, a heater 23 as a heating unit that radiates heat to the crucible 22 and heats it, a heat insulating cylinder 24, and a cable 25 and a thermal shield 26.

A gas inlet 21A for introducing an inert gas such as Ar gas into the chamber 21 is provided above the chamber 21. At the lower part of the chamber 21, a gas exhaust port 21B for exhausting the gas in the chamber 21 by driving of a vacuum pump (not shown) is provided.
An inert gas is introduced into the chamber 21 at a predetermined gas flow rate from the gas inlet 21A at the top of the chamber 21 under the control of the control unit 3. Then, the introduced gas is discharged from the gas exhaust port 21B at the lower part of the chamber 21 so that the inert gas flows downward from above in the chamber 21.

The crucible 22 melts silicon, which is a raw material of the wafer, to form a silicon melt M. The crucible 22 is supported by a support shaft 27 which can be rotated and lifted at a predetermined speed. The crucible 22 includes a bottomed cylindrical quartz crucible 221 and a graphite crucible 222 which houses the quartz crucible 221.
The heater 23 is disposed outside the crucible 22 and heats the crucible 22 to melt silicon in the crucible 22.
The heat insulating cylinder 24 is disposed to surround the crucible 22 and the heater 23.
One end of the cable 25 is connected to a pulling drive (not shown) disposed above the crucible 22, and the seed crystal SC is attached to the other end. The cable 25 moves up and down at a predetermined speed under the control of the pull-up drive unit by the control unit 3 and rotates around the axis of the cable 25.
The heat shield 26 blocks the radiant heat radiated upward from the heater 23.

  The control unit 3 controls the gas flow rate in the chamber 21 and the furnace internal pressure, the heating temperature in the chamber 21 by the heater 23, the temperature of the crucible 22 and silicon single on the basis of a control program stored in a memory (not shown) The single-crystal silicon SM is manufactured by controlling the rotational speed of the crystal SM, the elevation timing of the seed crystal SC and the like.

[Configuration of heat treatment apparatus]
As shown in FIG. 3, the heat treatment apparatus 5 includes a chamber 51.
In the chamber 51, a wafer tray 52, a base plate 53 disposed on the wafer tray 52, and three support pins 54 erected on the base plate 53 are provided. The three support pins 54 are arranged at intervals of 120 ° in top view in order to horizontally support the circular (silicon) wafer W.

Further, outside the chamber 51, an upper heating unit 55, a lower heating unit 56, and a pyrometer 57 are provided.
The upper heating unit 55 includes a plurality of upper heating lamps 551 disposed above the chamber 51, and the lower heating unit 56 includes a plurality of lower heating lamps 561 disposed below the chamber 51. . The upper heating lamp 551 and the lower heating lamp 561 are halogen lamps, and their light emission states are configured to be independently controllable. With such a configuration, by individually controlling the upper heating lamp 551 and the lower heating lamp 561, the temperature distribution in the surface of the wafer W can be controlled.
The pyrometer 57 is disposed below the lower heating unit 56 and measures the temperature of the wafer W.

  In the chamber 51, a gas introduction port 51A for introducing an inert gas, a reaction gas or the like into the chamber 51, a gas exhaust port 51B for exhausting the gas in the chamber 51, and the wafer W are transported out of the chamber 51. And an opening 51C for the purpose. When the wafer W is transferred into the chamber 51, the opening 51C is covered by an automatic shutter (not shown).

[Wafer manufacturing method]
When manufacturing a wafer, first, a growth step is performed using the pulling apparatus 1 shown in FIG.
In this growth step, silicon is introduced into the crucible 22 and the silicon is heated and melted in an Ar gas atmosphere. Next, the seed crystal SC attached to the cable 25 is immersed in the silicon melt M, and the seed crystal SC is gradually pulled up while rotating the seed crystal SC and the crucible 22 to manufacture the silicon single crystal SM.
At this time, it is preferable to control the manufacturing conditions so that the oxygen concentration of the silicon single crystal SM is 9.5 × 10 ¹⁷ atoms / cm ³ or more.
In pulling, the ratio V / G of the pulling speed V to the temperature gradient G in the growth direction of the silicon single crystal SM immediately after pulling is between a value corresponding to A in FIG. 1 and a value corresponding to C. It is preferable to control the manufacturing conditions so that Thereby, silicon single crystal SM free of COP and dislocation clusters can be manufactured. In addition, it is more preferable to control the manufacturing conditions so that the ratio V / G falls between the value corresponding to A and the value corresponding to B in FIG. This makes it possible to produce a silicon single crystal SM free of OSF, COP and dislocation clusters. Note that such a silicon single crystal SM improves the hot zone structure in which the graphite crucible 222, the heater 23, the heat insulating cylinder 24, and the heat shield 26 are disposed, and the temperature in the growth direction of the silicon single crystal SM immediately after pulling up. It can be manufactured by the pulling apparatus 1 capable of adjusting the radial distribution of the gradient G.

Next, the wafer W acquisition process is performed.
In this acquisition step, the wafer W can be obtained by cutting the silicon single crystal SM into a plurality of blocks and then performing slicing, lapping, chemical etching, mirror polishing, and other processes.

Next, an evaluation wafer is selected from the wafers W acquired in the acquisition step, and the occurrence status of the OSF of the evaluation wafer is evaluated (OSF evaluation step).
As a method of evaluating the state of occurrence of OSF, the evaluation wafer is subjected to heat treatment at a temperature of 1000 ° C. ± 30 ° C. for 2 hours or more and 5 hours or less under oxygen atmosphere. After heat treatment for less than a time, Seco etching may be performed and then microscopic observation may be performed.

Next, another evaluation wafer is obtained from the same silicon single crystal SM as the evaluation wafer having no OSF, and the RIE defect density of this evaluation wafer is evaluated (RIE defect density evaluation step). The following method can be exemplified as the RIE defect density evaluation method.
First, the evaluation wafer is loaded into a reactive ion etching apparatus, and etching is performed for about 5 μm in an HBr / Cl ₂ / He + O ₂ mixed gas atmosphere, with a Si / SiO ₂ selectivity of 100 or more. I do. Next, the evaluation wafer after reactive ion etching is washed with an aqueous solution of hydrofluoric acid to remove the reaction product attached at the time of reactive ion etching, and then the RIE defect density at a plurality of places on the etched surface is measured. Then, the maximum value is evaluated as the RIE defect density of the evaluation wafer.

Next, based on the evaluation results in the OSF evaluation step and the RIE defect density evaluation step, a heat treatment step is performed on the wafer W acquired from the same silicon single crystal SM as the evaluation wafer.
In this heat treatment process, the RTO process is performed on the wafer W under the conditions shown in FIG. 4 using the heat treatment apparatus 5 shown in FIG. Basic RTO processing is performed as follows.

First, the wafer W is placed on the support pins 54 in the chamber 51 held at the temperature T2 by the control of the upper heating unit 55 and the lower heating unit 56.
Then, the gas is introduced from the gas introduction port 51A and the gas is exhausted from the gas exhaust port 51B to make the inside of the chamber 51 be an oxidizing atmosphere, and then the upper heating unit 55 and the lower heating unit 56 are controlled. Thus, the wafer W is rapidly heated to the processing temperature T3 at the temperature rising rate ΔTu. The oxidizing atmosphere is preferably 100% oxygen, but is not limited thereto. For example, a mixed gas atmosphere of oxygen and an inert gas may be used.
Next, the temperature T3 is held for the holding time K.
After that, by controlling the upper heating unit 55 and the lower heating unit 56, the wafer W is rapidly cooled to the temperature T1 at the temperature lowering rate ΔTd, and then the RIE defect is sufficiently reduced by cooling to the room temperature. A wafer W is obtained.

In the above RTO process,
・ When OSF exists ・ When OSF does not exist and RIE defect density before RTO treatment is 5 × 10 ⁶ / cm ³ or more ・ OSF does not exist and RIE defect density before RTO treatment The processing temperature T3 in the case of less than 5 × 10 ⁶ / cm ³ is as shown in Table 1 below.
The holding time K is preferably 10 seconds to 60 seconds, and more preferably 30 seconds or less from the viewpoint of productivity.

  When OSF is present, the treatment temperature T3 may be 1310 ° C. or higher, but is preferably less than 1350 ° C. from the viewpoint of the service life of the heat treatment apparatus.

Here, in general, the RTO process is performed by supporting the outer peripheral portion of the silicon wafer with a plurality of support pins. In this case, slip dislocation may occur in the contact portion with the support pin due to stress due to the weight of the silicon wafer acting on the contact point with the support pin, thermal stress due to temperature distribution, and the like.
From the viewpoint of suppressing the occurrence of such slip dislocations, the processing temperature T3 is more preferably lower than the above range regardless of the presence or absence of OSF and the RIE defect density.

  As described above, RIE defects can be sufficiently reduced in any case by RTO treatment under different conditions according to the presence or absence of the OSF of the evaluation wafer and the RIE defect density before the RTO treatment.

Here, the reason why the wafer W in which the RIE defects are sufficiently reduced by the RTO process as described above is obtained is supplemented.
In general, oxygen of about 10 ¹⁸ atoms / cm ³ is contained as an impurity in the silicon single crystal SM grown by the CZ method. This oxygen is in the vicinity of the melting point of silicon is a solid solution between the crystal lattice, the wafer W sliced from the silicon single crystal SM, part of oxygen is deposited as a silicon oxide (SiO _2), P _V region Form crystal defects such as oxygen precipitate nuclei.
When the RTO process is performed on such a wafer W in an oxidizing atmosphere, the silicon oxide in the crystal defects in the wafer W disappears due to the movement of the oxygen atoms that constitute the wafer into the crystal lattice. Then, after the silicon oxide disappears, vacancies remain. Since the RTO process is performed in an oxidizing atmosphere, interstitial silicon is implanted from the front side of the wafer W to fill the vacancies. Consequently, RIE defects due to oxygen precipitation nuclei of OSF and _{P V} region due to OSF nuclei disappear or reduce.

  EXAMPLES The present invention will next be described in more detail by way of examples, which should not be construed as limiting the invention thereto.

[Experiment 1: Relationship between RTO processing temperature and occurrence of RIE defects before and after RTO processing in a wafer containing OSF and not containing COP and dislocation clusters]
First, a silicon single crystal containing OSF and containing neither COP nor dislocation cluster was manufactured by controlling V / G using the above-described pulling apparatus 1. The occurrence status of OSF was confirmed by the method exemplified in the above embodiment. Next, a wafer was cut out from this silicon single crystal, and the RIE defect density at a plurality of locations of the wafer was measured by the method exemplified in the above embodiment, and the maximum value was determined as the in-plane maximum RIE defect density.
The measurement results of the in-plane maximum RIE defect density are shown in Table 2.

As shown in Table 2, all the in-plane maximum RIE defect densities of Experimental Examples 1 to 18 containing OSF and not containing COP and dislocation clusters are larger than the detection limit (8 × 10 ⁴ / cm ³ ). there were.
In addition, since the samples of Experimental Examples 1 to 5, Experimental Examples 6 to 11, Experimental Examples 12 to 14, Experimental Examples 15 to 16, and Experimental Examples 17 to 18 are wafers respectively cut out of the same silicon single crystal, Experimental Examples 1 The values of the maximum in-plane RIE defect density before RTO treatment of Experimental Example 6, Experimental Example 12, Experimental Example 15, and Experimental Example 17 are shown in Experimental Examples 2 to 5, Experimental Examples 7 to 11, Experimental Examples 13 to 14, It used as a value of Example 16 and Experimental example 18.
Next, RTO processing is performed on the samples of Experimental Examples 1 to 18 under the following conditions using the above-described heat treatment apparatus 5, and the in-plane maximum RIE defect density is measured on the sample after this RTO processing by the above method. did.
Temperature T1: 600 ° C
Temperature T2: 800 ° C
Processing temperature T3: See Table 2. Holding time K: 10 seconds Temperature rising rate ΔTu: 50 ° C./sec Temperature lowering rate ΔTd: 33 ° C./sec In RTO treatment, it is not the wafer after RIE defect density measurement but the same A wafer cut from a silicon single crystal, which was not subjected to RIE defect density measurement, was used. The results are shown in Table 2. Further, the relationship between the RTO processing temperature and the in-plane maximum RIE defect density before and after the RTO processing is shown in FIG. In FIG. 5, although the number of data is considerably smaller than that of Table 1, it is because there is a sample having the same maximum in-plane RIE defect density before and after RTO processing.

As shown in Table 2 and FIG. 5, in the case of Experimental Examples 2 to 5 and 8 to 18 where the processing temperature T3 is 1310 ° C. or higher, the in-plane maximum RIE defect density is the detection limit regardless of the RIE defect density before RTO treatment. The following wafers were obtained, ie, wafers with sufficiently reduced RIE defects. On the other hand, in the case of Experimental Examples 1, 6 and 7 in which the processing temperature T3 is less than 1310 ° C. (1290 ° C., 1300 ° C.), the wafer having the maximum in-plane RIE defect density larger than the detection limit, ie, the RIE defects are sufficiently reduced No wafer was obtained.
From the above, Experimental Examples 2 to 5, 8 to 18 correspond to Examples of the present invention, Experimental Examples 1, 6 and 7 correspond to Comparative Examples, and a wafer containing OSF and containing neither COP nor dislocation cluster In the case, it has been confirmed that a wafer having a sufficiently reduced RIE defect can be manufactured by performing the RTO process at a process temperature T3 of 1310 ° C. or higher.

[Experiment 2: Relationship between RTO processing temperature and occurrence of RIE defects before and after RTO processing in a wafer not containing OSF, COP and dislocation clusters]
First, by controlling V / G of the above-described pulling apparatus 1, a silicon single crystal free of OSF, COP and dislocation clusters was manufactured. Then, samples (wafers) of Experimental Examples 19 to 61 were manufactured in the same manner as in Experiment 1 above, and the in-plane maximum RIE defect density before RTO treatment was measured. The results are shown in Tables 3 to 5.
In Experimental Examples 19 to 53, as in Experiment 1, when the maximum in-plane RIE defect density before RTO treatment is the same, the value of one sample was used as the value of the other sample.

As shown in Tables 3 and 4, in Experimental Examples 19 to 53 which do not contain OSF, COP and dislocation clusters, the RIE defect density before RTO treatment was 5 × 10 ⁶ / cm ³ or more. On the other hand, as shown in Table 5, in the experimental examples 54 to 61 not containing OSF, COP and dislocation clusters, the RIE defect density before the RTO treatment was less than 5 × 10 ⁶ / cm ³ .
Next, in the same manner as in Experiment 1, a wafer cut out from the silicon single crystal from which the samples of Experimental Examples 19 to 61 were obtained, which has not been subjected to RIE defect density measurement, is subjected to RTO processing and RTO processing. The in-plane maximum RIE defect density was measured. The results are shown in Tables 3 to 5. Further, the relationship between the RTO processing temperature and the in-plane maximum RIE defect density before and after the RTO processing is shown in FIG.
The RTO treatment was the same as Experiment 1 except that the treatment temperature T3 was changed to the conditions shown in Tables 3 to 5.

As shown in Tables 3 and 4 and FIG. 6, in Experimental Examples 19 to 53, Experimental Examples 22, 23, 28, 28, 32, 33, 37, 38, 42, 43, in which the treatment temperature T3 is 1270 ° C. or higher. In the cases of 47, 48, 52 and 53, the in-plane maximum RIE defect density after RTO treatment was below the detection limit, but in the case of other experimental examples where the treatment temperature T3 is less than 1270 ° C, it is larger than the detection limit It became a value.
From the above, Experimental Examples 22, 23, 27, 28, 32, 33, 33, 37, 38, 42, 43, 47, 48, 52, 53 correspond to Examples of the present invention, and Experimental Examples 19 to 21, 24 to 26, 29 to 31, 34 to 36, 39 to 41, 44 to 46, 49 to 51 correspond to comparative examples, which do not contain OSF, COP and dislocation clusters, and have RIE defect density before RTO treatment In the case of a wafer of 5 × 10 ⁶ pieces / cm ³ or more, it has been confirmed that a wafer having a sufficiently reduced RIE defect can be manufactured by performing the RTO treatment at a treatment temperature T3 of 1270 ° C. or more.

On the other hand, as shown in Table 5 and FIG. 6, in all of Experimental Examples 54 to 61, the in-plane maximum RIE defect density after RTO treatment was below the detection limit. Further, from the results of Experimental Examples 19 to 53, it can be inferred that the in-plane maximum RIE defect density decreases as the processing temperature T3 increases.
From these facts, when the RIE defect density before RTO treatment is less than 5 × 10 ⁶ pieces / cm ³ , the RIE defect is sufficiently reduced at the treatment temperature T3 of 1250 ° C. Therefore, the treatment temperature T3 is 1250 ° C. It can be estimated that the RIE defects are sufficiently reduced.
From the above, Experimental Examples 54 to 61 correspond to the examples of the present invention and do not contain OSF, COP and dislocation clusters, and the RIE defect density before RTO treatment is less than 5 × 10 ⁶ / cm ³ . In the case of a wafer, it has been confirmed that a wafer having a sufficiently reduced RIE defect can be manufactured by performing the RTO process at a process temperature T3 of 1250 ° C. or higher.

  SM: silicon single crystal, W: wafer.

Claims (2)

A growing step of growing a silicon single crystal free of COP and dislocation clusters by the Czochralski method;
An OSF evaluation step of evaluating the generation situation of the OSF of the evaluation wafer obtained from the silicon single crystal;
When an OSF is present in the evaluation wafer, an RTO process is performed on a silicon wafer obtained from the same silicon single crystal as the evaluation wafer under conditions of 1310 ° C. or higher, and when no OSF is present in the evaluation wafer, the silicon wafer And a heat treatment step of performing RTO treatment under conditions of less than 1310 ° C., and a method of manufacturing a silicon wafer. In the method of manufacturing a silicon wafer according to claim 1,
Including the RIE defect density evaluation step of evaluating the RIE defect density of other evaluation wafers obtained from the same silicon single crystal as the evaluation wafer without OSF,
In the heat treatment step, when the RIE defect density is 5 × 10 ⁶ pieces / cm ³ or more, an RTO treatment is performed on a silicon wafer obtained from the same silicon single crystal as the other evaluation wafer under conditions of 1270 ° C. or more A method for producing a silicon wafer, wherein the RTO treatment is performed on the silicon wafer under conditions of 1250 ° C. or higher when the RIE defect density is less than 5 × 10 ⁶ / cm ³ .

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