JP2010173887A - Production process of silicon wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a production process of silicon wafers which reduces RIE defects present in perfect regions. <P>SOLUTION: A silicon single crystal ingot having an oxygen concentration of below 1.2×10<SP>18</SP>atoms/cm<SP>3</SP>(former ASTM) is pulled. Silicon wafers are cut out from the ingot. Out of the silicon wafers obtained, ones containing a region in which an RIE defect density caused by reactive ion etching is 1×10<SP>4</SP>-1×10<SP>10</SP>pieces/cm<SP>3</SP>are subjected to a heat treatment. The heat treatment comprises heating the wafers up to 900-1,000°C at a first temperature elevation rate of 2-5°C/min, heating them up to a specific temperature of over >1,000°C and ≤1,200°C at a second temperature elevation rate of at most 2°C/min, and holding the specific temperature for 5-180 minutes in a hydrogen and/or argon gas atmosphere. The heat treatment procedure reduces the RIE defect density caused by reactive ion etching at a specific depth of 2-10 μm from the surface down to ≤1×10<SP>4</SP>pieces/cm<SP>3</SP>. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a silicon wafer obtained by slicing an ingot pulled up by the Czochralski method (hereinafter referred to as CZ method). More specifically, the present invention relates to a method for reducing crystal defects by heat treating a silicon wafer.

  When a silicon single crystal ingot is grown by the CZ method, the type and distribution of defects contained in the ingot depend on the ratio V / G between the pulling speed V of the ingot and the temperature gradient G in the pulling direction of the ingot. As shown in FIG. 2, when V / G is large, vacancies become excessive, and microvoids (generally called COP) that are aggregates of vacancies are generated. On the other hand, when V / G is small, the interstitial silicon atoms become excessive, and dislocation clusters that are aggregates of interstitial silicon atoms are generated. For this reason, in order to grow an ingot containing neither COP nor dislocation clusters, it is necessary to control so that V / G falls within an appropriate range in the radial direction and the pulling direction of the ingot. First, since the pulling speed V is constant at any position in the radial direction of the ingot, it is necessary to design a hot zone in the CZ furnace so that the temperature gradient G falls within a predetermined range. Next, regarding the pulling direction of the ingot, since the temperature gradient G depends on the pulling length of the ingot, it is necessary to change the pulling speed V in the pulling direction of the ingot in order to keep V / G within a predetermined range.

As described above, silicon wafers that do not contain COPs and dislocation clusters that are pulled up by controlling V / G are mass-produced and are used in the manufacture of electronic devices. However, these wafers are never uniform over the entire surface, and include a plurality of regions that behave differently when heat-treated. As shown in FIG. 2, between the region where the COP is the area dislocation clusters occur generated, in order of V / G is large, OSF region, the three regions of the P _V region and P _I region there To do. The OSF region is a state in which no heat treatment is performed immediately after the pulling (as-grown state) and includes plate-like oxygen precipitates (OSF nuclei) at a high temperature (generally 1000 to 1200 ° C.). This is a region where OSF (Oxidation induced Stacking Fault) occurs when thermal oxidation occurs. In addition, the P _V region includes oxygen precipitation nuclei in a state in which no heat treatment is performed immediately after the pulling (as-grown state), and it has a low temperature (for example, 800 ° C.) and a high temperature (for example, 1000 ° C.). This is a region where oxygen precipitates are likely to occur when two-stage heat treatment is performed. Furthermore the P _I area, pulling Nothing contains most oxygen precipitation nuclei in a state not subjected to heat treatment (state of the as-grown) immediately after heat treatment in the region where oxygen precipitate hardly occurs even if subjected to is there. Defects such as oxygen precipitation nuclei existing in the P _V region and OSF nuclei existing in the OSF region are defects (hereinafter referred to as “reactive ion etching”, hereinafter referred to as RIE) that are manifested on the wafer surface. RIE defect).

Conventionally, there has been proposed a method of pulling a silicon single crystal in a P _V region where there is much oxygen precipitation outside the OSF region (Japanese Patent Laid-Open No. 11-157996). According to this method, a silicon wafer that has an extremely low defect density over the entire crystal surface and is capable of gettering (IG) by oxygen precipitation under the manufacturing conditions that are easy to control, without any dislocation clusters and COPs. It can be manufactured while maintaining high productivity. Further, since the oxygen concentration on the whole surface of the wafer sliced from the silicon single crystal is less than 24 ppma (ASTM'79 value) [corresponding to about 1.2 × 10 ¹⁸ atoms / cm ³ (former ASTM)], the growth of OSF nuclei Even if the OSF ring or the potential nucleus of the OSF ring is present in the wafer, the semiconductor device is not affected. That is, the wafer is subjected to high-temperature heat treatment in the semiconductor device manufacturing process. When the OSF thermal oxidation treatment is performed, the OSF ring nucleus is latent, but the OSF ring is not generated.

JP 11-157996 (Claims 1 and 7, paragraphs [0011], paragraph [0017], paragraph [0056])

  In recent years, in the process of manufacturing semiconductor devices, along with miniaturization and high precision of semiconductor devices, long-term low-temperature heat treatment has been performed without high-temperature heat treatment. As a result, there is a concern that the RIE defect existing in the perfect region, particularly around the Pv region, which has not been a problem in the past, has an adverse effect on the device. If the RIE defect remains in the active layer (for example, a depletion layer) of the device, it may cause a leak current in the device.

  An object of the present invention is to provide a silicon wafer manufacturing method capable of reducing RIE defects existing in a perfect region.

The first aspect of the present invention is that a region where vacancy type point defects exist predominantly in a silicon single crystal ingot is a V region, and a region where interstitial silicon type point defects exist predominantly is an I region. When a perfect region where no agglomerates of vacancy type point defects and agglomerates of interstitial silicon type point defects exist is defined as a P region, silicon in which no agglomerates of point defects cut out from an ingot composed of the P region exist In a method for manufacturing a wafer, a silicon single crystal ingot having an oxygen concentration of less than 1.2 × 10 ¹⁸ atoms / cm ³ (former ASTM) is pulled up, and the RIE defect density obtained by the reactive ion etching method cut out from the ingot. There the silicon wafer includes a region that is 1 × ^{10 4} ~1 × 10 10 atoms / cm ^3, hydrogen and / or argon gas atmosphere from 900 to 100 A second temperature increase within a range of 2 ° C./min or less up to a predetermined temperature within a range of more than 1000 ° C. and less than or equal to 1200 ° C. By performing heat treatment at a predetermined temperature within a range of 2 to 10 μm from the surface, the RIE defect density by the reactive ion etching method is set to 1 by heating at a speed and further holding at the predetermined temperature for 5 to 180 minutes. × 10 ⁴ pieces / cm ³ or less

  A second aspect of the present invention is an invention based on the first aspect, and is characterized in that the main surface or both surfaces are polished after the heat treatment.

In the manufacturing method according to the first aspect of the present invention, even if the RIE defect density is as high as 1 × 10 ⁴ to 1 × 10 ¹⁰ pieces / cm ³ before performing the heat treatment on the wafer, The RIE defect density at a predetermined depth within the range of 2 to 10 μm from the surface is 1 × 10 ⁴ pieces / cm ³ or less. As a result, since RIE defects can be reduced, it is possible to suppress the occurrence of a leak current in the device even if the semiconductor device is miniaturized and highly accurate.

  In the manufacturing method according to the second aspect of the present invention, the atoms on the surface of the silicon wafer are rearranged by the heat treatment, and the haze (surface roughness) when measured with a particle counter such as SP2 is increased, and minute particles are measured. Difficult to do. For this reason, by polishing the silicon wafer to a predetermined depth after the heat treatment, an increase in the haze can be suppressed, and a low-haze silicon wafer corresponding to device miniaturization can be provided.

(A) is a schematic diagram of a wafer having RIE defects before heat-treating the silicon wafers of the embodiments and examples of the present invention, and (b) is an RIE after heat-treating the silicon wafers of the embodiments and examples of the present invention. It is a schematic diagram of a wafer without a defect. It is a schematic diagram showing the distribution of glow-in defects on a vertical plane including a crystal axis with respect to V / G in a silicon single crystal ingot.

  Next, an embodiment for carrying out the present invention will be described with reference to the drawings. The silicon wafer of the present invention is produced by slicing a silicon single crystal ingot from a silicon melt in a hot zone furnace by a CZ method with a predetermined pulling speed profile based on Boronkov theory, and then slicing the ingot. Is done. When a silicon single crystal ingot is grown by the CZ method, the type and distribution of defects contained in the ingot depend on the ratio V / G between the ingot pulling speed V and the temperature gradient G in the pulling direction of the ingot. As shown in FIG. 2, when V / G is large, vacancies become excessive, and microvoids (generally called COP) that are aggregates of vacancies are generated. This region is a V region in which vacant point defects such as COP exist predominantly. When V / G is small, the interstitial silicon atoms become excessive and dislocation clusters that are aggregates of interstitial silicon atoms are generated. This region is an I region in which interstitial silicon type point defects such as dislocation clusters are dominantly present. Further, a perfect region where no aggregate of interstitial silicon type point defects and no aggregate of hole type point defects exists is defined as a P region.

On the other hand, between the region where dislocation clusters and region (V region) in which the COP occurs is generated (I region), in order of V / G is large, OSF region, 3 in the P _V region and P _I area There are two areas. The OSF region is a state in which no heat treatment is performed immediately after the pulling (as-grown state) and includes plate-like oxygen precipitates (OSF nuclei) at a high temperature (generally 1000 to 1200 ° C.). This is a region where OSF is generated when thermally oxidized. In addition, the P _V region includes oxygen precipitation nuclei in a state in which no heat treatment is performed immediately after the pulling (as-grown state), and it has a low temperature (for example, 800 ° C.) and a high temperature (for example, 1000 ° C.). This is a region where oxygen precipitates are likely to occur when two-stage heat treatment is performed. Furthermore the P _I area, pulling Nothing contains most oxygen precipitation nuclei in a state not subjected to heat treatment (state of the as-grown) immediately after heat treatment in the region where oxygen precipitate hardly occurs even if subjected to is there. The P _V region and the P _I region are combined to form a P region.

The oxygen concentration in the ingot pulled up by the CZ method is less than 1.2 × 10 ¹⁸ atoms / cm ³ (former ASTM), preferably 1.0 × 10 ¹⁸ atoms / cm ³ (former ASTM) or less. Here, the oxygen concentration in the ingot was limited to less than 1.2 × 10 ¹⁸ atoms / cm ³ (former ASTM), and was 1.2 × 10 ¹⁸ atoms / cm ³ (former ASTM) or more after heat treatment. This is because OSF nuclei may remain and RIE defects may not be reduced. Further, a region which is cut out from the ingot and has a RIE defect density of 1 × 10 ⁴ to 1 × 10 ¹⁰ pieces / cm ³ , preferably 1 × 10 ^{4 to} 5 × 10 ⁸ pieces / cm ³ by reactive ion etching. It is a silicon wafer containing. Here, the RIE defect density was limited to the range of 1 × 10 ⁴ to 1 × 10 ¹⁰ pieces / cm ^{3 when} the RIE defect density was sufficiently low when the density was less than 1 × 10 ⁴ pieces / cm ^3. This is because if the amount exceeds 1 × 10 ¹⁰ pieces / cm ³ , RIE defects remain in the vicinity of the surface layer even if heat treatment is performed.

The RIE defect is a defect that appears on the wafer surface by the reactive ion etching method. In order to make silicon oxide appear as needle-like protrusions by reactive ion etching, reactive ion etching is performed under conditions where Si is easier to etch than SiO ₂ , that is, under a higher Si / SiO ₂ selection ratio. There is a need to do. As a result, oxygen precipitates (SiO ₂ ) are hardly etched and become apparent as needle-like protrusions. As an etching gas, when oxygen precipitates in a silicon wafer are etched using a general magnetron RIE apparatus (Precision 5000 ETCH, manufactured by Applied Materials), a halogen-based mixed gas such as HBr or NF _{3 is used.} Alternatively, it is preferable to use a mixed gas of any one of He and O ₂ . This halogen-based etching gas has higher etching selectivity in the order of F, Cl, and Br with respect to oxygen precipitation defects in silicon. In order to generate this, a Br-based gas is most preferable, and the order of Cl and F follows. Further, it is preferable to set the conditions so that the Si / SiO ₂ selection ratio is 100 or more. Further, after the reactive ion etching, cleaning is performed with an aqueous hydrofluoric acid solution to remove reaction products attached during the reactive ion etching. Then, the needle-like protrusions on the wafer surface etched by reactive ion etching are measured using a particle counter (manufactured by KLA-Tencor) or the like, and the number of RIE defects per cm ³ is calculated.

  When measuring the RIE defect density at a relatively shallow position of the wafer, for example, at a depth of 3 to 5 μm from the wafer surface, the surface of the wafer is mirror-polished by 3 μm and the wafer surface is washed and dried, or hydrofluoric acid. Then, the wafer surface is etched by 3 μm with an aqueous solution containing nitric acid, and the wafer surface is cleaned and dried, and then further etched by 2 μm by a reactive ion etching method. Then, the number of needle-like protrusions is measured using a particle counter (manufactured by KLA-Tencor). When measuring the RIE defect density at a relatively deep position of the wafer, for example, at a depth of 8 to 10 μm from the wafer surface, the surface of the wafer is mirror-polished by 8 μm and the wafer surface is cleaned and dried, or is The wafer surface is etched by 8 μm with an aqueous solution containing acid and nitric acid, and this wafer surface is cleaned and dried, and then further etched by 2 μm by the reactive ion etching method. Then, the number of needle-like protrusions is measured using a particle counter (manufactured by KLA-Tencor).

On the other hand, with respect to the silicon wafer obtained by slicing the ingot pulled up by the CZ method, it is within a range of 2 to 5 ° C./min from 900 to 1000 ° C. in a gas atmosphere of either hydrogen or argon or both. Heating at a first temperature rising rate, heating at a second temperature rising rate in the range of 2 ° C./min or less to a predetermined temperature in the range of over 1000 ° C. and below 1200 ° C. A heat treatment is performed for 180 minutes, preferably 5 to 120 minutes. Here, the reason that the first heating rate is limited to the range of 2 to 5 ° C./min is that there is a problem that the productivity is lowered at less than 2 ° C./min. This is because (dislocation) occurs and the yield is lowered. The reason for limiting the second temperature rising rate to 2 ° C./min or less is that if it exceeds 2 ° C./min, slip defects (dislocations) occur and the yield decreases. Further, the holding temperature is limited to the range of over 1000 ° C. and below 1200 ° C. The reason that the RIE defect remains in the vicinity of the surface layer even when heat treatment is carried out at 1000 ° C. or less. This is because there is a problem that the rearrangement is likely to occur and the yield is lowered. Furthermore, the holding time was limited to the range of 5 to 180 minutes. If the heat treatment was performed for less than 5 minutes (particularly in combination with 1000 ° C.), there was a problem that RIE defects remained in the vicinity of the surface layer, and 180 minutes This is because the RIE defect reduction effect is hardly changed, and the productivity is lowered. The second temperature increase rate is set smaller than the first temperature increase rate. This is because slip dislocation (slip) is likely to occur when the temperature is increased due to the oxygen concentration being less than 1.2 × 10 ¹⁸ atoms / cm ³ (former ASTM). This is because the movement speed of the slip dislocation increases and the slip dislocation becomes easy to extend. This phenomenon is particularly noticeable for wafers with a current mainstream diameter of 300 mm.

  In order to raise the temperature from room temperature to 900 ° C., first, the temperature in the vertical furnace is raised and maintained at, for example, about 500 ° C., and the wafer is put in the vertical furnace, and then the temperature is increased from 500 to 900 ° C. to 10 ° C. It is preferable to heat at a predetermined rate of temperature increase in the range of ˜50 ° C./min, preferably 5˜20 ° C./min. In addition, after the above heat retention time has elapsed, the temperature up to 1000 ° C. is within a range of 2 ° C./min, the range from 1000 to 900 ° C. is within the range of 2 to 5 ° C./min, and the temperature from 900 ° C. to the temperature at which the wafer is taken out is 50 ° C. It is preferable to cool at a predetermined temperature decrease rate of 1 minute or less.

In the method of manufacturing a silicon wafer thus configured, even if the RIE defect density before the heat treatment is performed on the wafer is 1 × 10 ⁴ to 1 × 10 ¹⁰ pieces / cm ³ and a high-density region is included, When the above heat treatment is performed on the wafer, the RIE defect density at a predetermined depth within the range of 2 to 10 μm from the surface is extremely reduced to 1 × 10 ⁴ pieces / cm ³ or less. As a result, even when the semiconductor device is miniaturized and highly accurate, it is possible to suppress the occurrence of leakage current in the device. That is, as shown in FIG. 1A, the wafer according to the present embodiment is a region where the outer peripheral portion is almost free of RIE defects and the central portion is a region where RIE defects are present at high density before heat treatment. However, after the heat treatment, as shown in FIG. 1B, the RIE defect in the central portion disappears and becomes the same as the outer peripheral region where there was almost no RIE defect from the beginning. This is an area where there is almost no.

  In addition, the atoms on the surface of the silicon wafer are rearranged by the heat treatment, and haze (surface roughness) at the time of measurement with a particle counter such as SP2 increases, and it may be difficult to measure minute particles. For this reason, by polishing the silicon wafer to a predetermined depth after the heat treatment, an increase in the haze can be suppressed, and a low-haze silicon wafer corresponding to device miniaturization can be provided. The polishing amount for reducing the haze of the main surface is sufficient if it is 0.05 μm or more. Further, by polishing both surfaces after the heat treatment, it is possible to remove minute flaws introduced into the support contact surface when holding the wafer during the heat treatment. The polishing amount for removing the fine scratches is desirably 2 μm or more.

Next, examples of the present invention will be described in detail together with comparative examples.
<Example 1>
A silicon single crystal ingot having a diameter of 300 mm was pulled using a silicon single crystal pulling apparatus. This ingot has a straight body length of 600 mm, a crystal orientation of (100), a resistivity of 8 to 12 Ωcm, and an oxygen concentration of 1.15 × 10 ¹⁸ atoms / cm ³ (former ASTM). Met. The ingot was grown by adjusting the V / G at the time of pulling up so as to consist only of a perfect region not including COP and dislocation clusters. After slicing the ingot, a wafer was obtained through chamfering, grinding, etching, mirror polishing, and cleaning. The wafer was subjected to the following heat treatment in an argon gas atmosphere. First, the temperature in the vertical furnace was raised to 500 ° C., and the wafer was put in the vertical furnace, and then heated to 500 to 900 ° C. at a temperature raising rate of 15 ° C./min. Subsequently, it heated at 900-1000 degreeC with the 1st temperature increase rate of 3 degree-C / min. Next, after heating at 1000-1200 degreeC with the 2nd temperature increase rate of 1 degree-C / min, it hold | maintained at 1200 degreeC for 60 minutes. Further, the wafer was cooled to 1000 ° C. at 1.5 ° C./min, to 900 ° C. at 3 ° C./min, and to a temperature for taking out the wafer at a temperature decreasing rate of 10 ° C./min. This wafer was referred to as Example 1.
<Example 2>
The same crystal as in Example 1 was pulled up, and the ingot was sliced to obtain a wafer through chamfering, grinding, etching, and cleaning. The wafer was heat-treated in the same manner as in Example 1, then polished on both sides by 8 μm (single side: 4 μm), and finished and washed.

<Comparative Example 1>
The same ingot as in Example 1 was sliced to obtain a wafer. The wafer was subjected to the following heat treatment in an argon gas atmosphere. First, the temperature in the vertical furnace was raised to 500 ° C., and the wafer was placed in the vertical furnace, and then heated to 500 to 900 ° C. at a temperature raising rate of 15 ° C./min. Next, it was kept at 900 ° C. for 60 minutes. Further, the wafer was cooled to room temperature at a temperature decreasing rate of 10 ° C./min. This wafer was referred to as Comparative Example 1.

<Comparative test 1 and evaluation>
For the wafers after heat treatment of Example 1, Example 2, and Comparative Example 1, the RIE defect density at a depth of 3 to 5 μm from the main surface was measured. First, the wafer surface was etched by 3 μm with an aqueous solution containing hydrofluoric acid and nitric acid. The wafer surface was washed and dried, and then reactive ion etching was performed. This reactive ion etching was performed using a magnetron RIE apparatus (Precision 5000 ETCH, manufactured by Applied Materials) under conditions with a high Si / SiO ₂ selection ratio, that is, conditions under which SiO ₂ is difficult to etch. As the etching gas, a mixed gas of HBr and O ₂ was used. Further, the conditions were set so that the Si / SiO ₂ selection ratio was 120. After reactive ion etching, cleaning with hydrofluoric acid aqueous solution is performed to remove reaction products adhering during reactive ion etching, and the needle-like protrusions on the wafer surface etched by reactive ion etching are treated with a particle counter (KLA-Tencor) The number of RIE defects per cm ³ was calculated. The results are shown in Table 1. In addition, about the wafer before the heat processing of Example 1, Example 2, and Comparative Example 1, the RIE defect density in the depth of 3-5 micrometers from the main surface was also measured similarly to the above.

表１から明らかなように、比較例１のウェーハでは、熱処理前のＲＩＥ欠陥密度が８×１０⁷個／ｃｍ³と多かったのに対し、熱処理後のＲＩＥ欠陥密度も７．９×１０⁷個／ｃｍ³と多く、殆ど変化がなかった。これに対し、実施例１のウェーハでは、熱処理前のＲＩＥ欠陥密度が８×１０⁷個／ｃｍ³と多かったのに対し、熱処理後のＲＩＥ欠陥密度が１．２×１０³個／ｃｍ³と極めて少なくなった。この結果、本発明の熱処理によって、ＲＩＥ欠陥を低減できることが分かった。即ち、実施例１のウェーハは、熱処理前には、図１（ａ）に示すように、外周部がＲＩＥ欠陥の殆どない領域であり中心部がＲＩＥ欠陥が高密度に存在する領域であったけれども、熱処理後には、図１（ｂ）に示すように、中心部のＲＩＥ欠陥が消滅して、最初からＲＩＥ欠陥が殆どなかった外周部の領域と同様になり、その結果、全面が微小欠陥（ＲＩＥ欠陥）の殆どない領域となった。

As is clear from Table 1, the wafer of Comparative Example 1 had a high RIE defect density of 8 × 10 ⁷ pieces / cm ³ before the heat treatment, whereas the RIE defect density after the heat treatment was 7.9 × 10 ^7. There were many changes per piece / cm ^3, and there was almost no change. In contrast, in the wafer of Example 1, the RIE defect density before heat treatment was as high as 8 × 10 ⁷ pieces / cm ³ , whereas the RIE defect density after heat treatment was 1.2 × 10 ³ pieces / cm ^3. And very few. As a result, it was found that RIE defects can be reduced by the heat treatment of the present invention. That is, as shown in FIG. 1A, the wafer of Example 1 was a region where the outer peripheral portion was almost free of RIE defects and the central portion was a region where RIE defects were present at a high density before heat treatment. However, after the heat treatment, as shown in FIG. 1B, the RIE defect in the central portion disappears and becomes the same as the outer peripheral region where there was almost no RIE defect from the beginning. The region was almost free of (RIE defects).

In the wafer of Example 2, the RIE defect density before the heat treatment was as high as 8 × 10 ⁷ pieces / cm ³ , whereas the RIE defect density after the heat treatment was 2.0 × 10 ³ pieces / cm ^3. The haze was reduced with respect to Example 2 as well. In Example 1, even though the maximum sensitivity of the particle counter SP-2 manufactured by KLA-Tencor was measured, a sufficient S / N ratio was not obtained due to the effect of haze, and it was only possible to measure up to 45 nm. In Example 2, it was possible to measure up to 37 nm LPD (Light Point Defect).

Claims (2)

A region where vacant point defects exist predominantly in a silicon single crystal ingot is designated as V region, and a region where interstitial silicon type point defects exist predominantly as I region, and agglomerates of vacant point defects And when a perfect region where no agglomerates of interstitial silicon type point defects exist is defined as a P region,
In a method for producing a silicon wafer in which no agglomerates of point defects cut out from an ingot composed of the P region exist,
Pulling up a silicon single crystal ingot having an oxygen concentration of less than 1.2 × 10 ¹⁸ atoms / cm ³ (former ASTM),
A silicon wafer including a region cut out from the ingot and having a RIE defect density of 1 × 10 ⁴ to 1 × 10 ¹⁰ pieces / cm ³ by a reactive ion etching method is used in a hydrogen and / or argon gas atmosphere. Heat to 1000 ° C. at a first rate of temperature rise in the range of 2-5 ° C./min, and rise to a predetermined temperature in the range of over 1000 ° C. and below 1200 ° C., and a second rise in the range of 2 ° C./min. RIE defect density by reactive ion etching at a predetermined depth in the range of 2 to 10 μm from the surface is performed by heating at a temperature rate and further performing a heat treatment for 5 to 180 minutes at the predetermined temperature. 1 * 10 < ⁴ > piece / cm < ³ > or less The manufacturing method of the silicon wafer characterized by the above-mentioned.   A method for producing a silicon wafer, comprising polishing a main surface or both surfaces after the heat treatment according to claim 1.

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