JP2001044207A - Ig processing method, ig wafer prepared thereby, and single-crystal silicon ingot used therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an IG wafer having a high IG capability, where a wafer is heat-treated for a smaller number of times and a desired IG effect can be exhibited by a heat treatment at 950 deg.C or lower, as well as to obtain a single- crystal silicon ingot suitable for this IG wafer. SOLUTION: The IG processing method involves the steps of rapidly heating a silicon wafer, after which it is immediately cut out of a silicon single-crystal ingot and ground and polished, starting from the room temperature to 700-950 deg.C at a rate of 10 deg.C/minute or higher, and thereafter holding the heated wafer for 0.5-30 minutes. The ingot is lifted from a silicon melt, such that oxidation induced stacking faults(OSF) are formed in an area which is 25% or more of the total wafer area when thermally oxidized in the form of a wafer, and contains oxygen precipitates accompanying no formation of dislocations in amounts of 1×105-3×107 pieces/cm3. In this IG wafer, a DZ layer is formed to a depth of 1-100 μm from the wafer surface and has a density range for oxygen prec ipitates of 1×105-3×107 pieces/cm3 at a portion deeper than the DZ layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LS
The present invention relates to a method of heating a silicon wafer to perform an intrinsic gettering (hereinafter, referred to as IG) process in order to obtain a silicon wafer suitable for manufacturing I. More specifically, the present invention relates to a silicon single crystal ingot pulled up by the Czochralski method (hereinafter, referred to as CZ method), and a method of performing IG processing on a silicon wafer cut from the ingot at a low temperature of 950 ° C. or less.

[0002]

2. Description of the Related Art In recent years, high integration of semiconductor devices such as DRAMs has been required based on mass production of megabit memories, and silicon wafers have been required to have higher quality. One way to meet this need is to:
There is an IG processing method. This processing method creates defects in the interior of the silicon wafer in advance, or intentionally adds impurities, absorbs the contamination generated in the course of the subsequent process around the previously created defects, and removes the surface of the wafer where devices are made. This is a processing method for preventing generation of defects and contamination in a nearby area. On the other hand, due to recent high integration of devices, the heat treatment temperature in the device process tends to be lower than 1000 ° C., and with the lowering of the temperature, there is a strong demand for lowering the temperature in the IG process which is the preceding process.

[0003] For this reason, the present applicant holds a silicon wafer cut from a silicon single crystal ingot and immediately after grinding and polishing at 500 to 800 ° C. for 0.5 to 20 hours to store oxygen precipitation nuclei in the wafer. A silicon wafer containing the oxygen precipitation nuclei from room temperature to 800 to 1
A step of rapidly heating to 000 ° C. and holding for 0.5 to 20 minutes, a step of rapidly heating and holding the silicon wafer held for 0.5 to 20 minutes further to room temperature, and Heat from 700 ° C to 800 to 1100 ° C at a rate of 2 to 10 ° C / min.
An IG treatment method including a step of holding for 8 hours was proposed (Japanese Patent Application Laid-Open No. 8-45945).

In this processing method, when the wafer is rapidly heated under the above temperature conditions, the temperature inside the wafer as well as the wafer surface temporarily drops below the thermal equilibrium concentration, interstitial silicon atoms become depleted, and oxygen precipitation nuclei grow stably. It is an environment that is easy to do. At the same time, the interstitial silicon atoms are compensated for and become stable, so that interstitial silicon atoms are generated on the wafer surface, and the generated interstitial silicon atoms begin to diffuse into the wafer. The vicinity of the wafer surface, which was in a depleted state of interstitial silicon atoms, is immediately saturated by the generation of interstitial silicon atoms, and the oxygen precipitation nuclei begin to disappear. However, it takes a certain amount of time for the interstitial silicon atoms generated on the wafer surface to diffuse into the inside of the wafer. Therefore, an environment in which oxygen precipitate nuclei are more likely to grow as the depth goes deeper from the wafer surface. Therefore, the density of the oxygen precipitation nuclei is lower as the surface is closer to the wafer surface, and the longer the heat treatment time (0.5 to 20 minutes), the thickness of the oxygen precipitation nuclei, that is, the layer in which no defect is formed (hereinafter, referred to as a DZ layer). It becomes big. Also, as the temperature is higher in the range of 800 to 1000 ° C., the diffusion coefficient of interstitial silicon atoms increases, and the thickness of the DZ layer increases in a short time. When the wafer is rapidly heated and allowed to cool to room temperature and then heated again to 800 to 1100 ° C., the oxygen precipitation nuclei inside the wafer that survived by the rapid heating grow to become oxygen precipitates, and serve as a stable IG source.

[0005]

However, in the above-mentioned IG processing method, as a pretreatment for generating an IG source, a silicon wafer immediately after grinding and polishing is subjected to 0.1 to 500.degree.
This required a step of introducing oxygen precipitation nuclei into the wafer by holding the wafer for 5 to 20 hours, and further required a heat treatment for growing the oxygen precipitation nuclei inside the wafer into oxygen precipitates after rapid heating. For this reason, there has been a problem that the number of heat treatments in the state of the wafer is large. An object of the present invention is to reduce the number of heat treatments in a silicon wafer state,
An object of the present invention is to provide an IG processing method which exhibits a desired IG effect by heat treatment at a temperature of not more than ° C. It is another object of the present invention to provide an IG wafer having a high IG capability manufactured by this processing method. Still another object of the present invention is to provide a silicon single crystal ingot suitable for this IG wafer.

[0006]

The invention according to claim 1 is
A silicon wafer cut from a silicon single crystal ingot and immediately after being ground and polished is rapidly heated from room temperature to 700 to 950 ° C. at a rate of 10 ° C./min or more, and 0.5 to 3
This is an IG processing method in which a silicon single crystal ingot is subjected to thermal oxidation treatment in a state of a silicon wafer for at least 0%, and an oxidation induced stacking fault (hereinafter, referred to as OSF) is formed in at least 25% of the total area of the wafer. ) Is generated from the silicon melt so as to generate oxygen precipitates without dislocation generation from 1 × 10 ^{5 to} 3 × 1.
A IG treatment, which comprises 0 ⁷ / cm ^3.
By using an ingot containing oxygen precipitates of a predetermined density in the OSF region present in the above ratio when the wafer is formed, the conventional pre-heat treatment step of introducing oxygen precipitate nuclei into the wafer and the growth step of the oxygen precipitate nuclei are performed. It becomes unnecessary, and a high IG effect is achieved by rapidly heating the wafer cut immediately after grinding and polishing from the ingot under the above conditions.

According to a second aspect of the present invention, there is provided the I
An IG wafer made by the G processing method, wherein a layer (DZ layer) in which oxygen precipitates are not formed is 1 to
An IG wafer formed over a depth of 100 μm and having an oxygen precipitate of 1 × 10 ^{5 to} 3 × 10 ⁷ / cm ^{3 in} a portion deeper than the DZ layer. The wafer subjected to IG processing by the method according to claim 1 has the above characteristics and exhibits a high IG effect.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The silicon wafer of the present invention has a C
After the ingot is pulled up from the silicon melt in the hot zone furnace by the Z method with a predetermined pulling speed profile based on Voronkov's theory, the ingot is sliced. Generally, when a silicon single crystal ingot is pulled up from a silicon melt in a hot zone furnace by the CZ method, point defects and agglomerates: Defects). Point defects have two general forms: vacancy type point defects and interstitial silicon type point defects. A vacancy-type point defect is one in which one silicon atom has separated from one of the normal positions in the silicon crystal lattice. Such holes become hole type point defects. On the other hand, if an atom is found at a position (interstitial site) other than the lattice point of the silicon crystal, this becomes an interstitial silicon point defect.

[0009] Point defects are generally formed at the interface between the silicon melt (molten silicon) and the ingot (solid silicon). However, by continuously pulling up the ingot, the portion that was the contact surface starts to cool down with pulling up. During cooling, vacancy-type point defects or interstitial silicon-type point defects merge with each other by diffusion to form vacancy agglomerates or interstitial agglomerates. Is formed. In other words, the aggregate is a three-dimensional structure generated due to the merging of point defects. Aggregates of vacancy type point defects are C
OP (Crystal Originated Particle), LSTD (Las
er Scattering Tomograph Defects) or FPD (Flow
Aggregates of interstitial silicon-type point defects containing defects called Pattern Defects (LDs)
e Dislocation). What is COP?
When the silicon wafer after mirror polishing is washed with a mixed solution of ammonia and hydrogen peroxide, the pits are caused by crystals formed on the wafer surface. These pits are also detected as particles together with the original particles when the wafer is measured with a particle counter. LSTD is a source that generates scattered light having a different refractive index from silicon when irradiating infrared rays into a silicon single crystal,
The FPD is a source of a trace exhibiting a unique flow pattern that appears when a silicon wafer manufactured by slicing an ingot is chemically etched with a Secco etchant for 30 minutes. The LD is an interstitial dislocation and is also called a dislocation cluster, or a dislocation pit because a pit is generated when a silicon wafer having this defect is immersed in a selective etching solution containing hydrofluoric acid as a main component.

[0010] Boronkov's theory states that the number of defects is small and high.
Raising the ingot to grow a pure ingot
V (mm / min), hot zone structure
G (° C / mm)
V / G (mm ^Two/ Min ・ ℃)
And In this theory, as shown in FIG.
Schematic of vacancy concentration and interstitial silicon concentration as a function
Express, the boundary of vacancy / interstitial silicon region on the wafer
It is explained that it is determined by V / G. More details
Specifically, when the V / G ratio is above the critical point, vacancy-type point defects dominate
While the ingot which exists in the end is formed, the V / G ratio is
Below the critical point, interstitial silicon-type point defects predominate
An ingot is formed.

[0011] The predetermined pull rate profile of the present invention is that when the ingot is pulled from the silicon melt in a hot zone furnace, the ratio of the pull rate to the temperature gradient (V / G) is an aggregate of interstitial silicon type point defects. Aggregates of vacancy-type point defects which are equal to or higher than the first critical ratio ((V / G) ₁ ) for preventing generation of vacancies are located in the region where vacancy-type point defects predominantly exist in the center of the ingot. It is determined so as to be maintained at or below the second critical ratio ((V / G) ₂ ).

The profile of the pulling speed is determined by simulating the reference ingot in the axial direction experimentally and by simulation based on the above-mentioned Bornkov theory. That is, after the simulation,
This is performed by confirming the axial slice of the ingot and the sliced wafer, and repeating the simulation. For the simulation, a plurality of kinds of pulling speeds are determined within a predetermined range, and a plurality of reference ingots are grown. As shown in FIG. 2, the pulling speed profile for the simulation is from a high pulling speed (a) such as 1.2 mm / min to a low pulling speed (c) of 0.5 mm / min and again a high pulling speed (d). It is adjusted to. The low pull rate may be 0.4 mm / min or less, and the change in pull rates (b) and (d) is preferably linear.

A plurality of reference ingots pulled at different speeds are individually sliced in the axial direction. Optimal V /
G is determined from the correlation of the results of the axial slicing, wafer validation and simulation, followed by the determination of the optimal pulling speed profile, which is used to produce the ingot. The actual pulling speed profile will depend on many variables including but not limited to the desired ingot diameter, the particular hot zone furnace used and the quality of the silicon melt.

FIG. 3 shows the fact that a drawing of a cross section of the ingot when the pulling speed is gradually reduced and V / G is continuously reduced is illustrated. In FIG. 3, [V] represents an abundant region where vacancy type point defects predominantly exist in the ingot, [I] represents a region where interstitial silicon type point defects predominantly exist, and vacancy type points. Perfect regions where there are no defect aggregates and no interstitial silicon type point defect aggregates are indicated as [P]. As shown in FIG. 3, the axial position P ₁ of the ingot contains a region where vacancy type point defects at the center dominantly present. Position P ₂ includes an area smaller vacancy type point defects at the center dominantly present as compared to the position P _1. Position P ₄ includes a ring region and the central perfect area that exists dominantly interstitial silicon type point defects. The position P ₃ is neither vacancy type point defects at the center, all since there is no silicon point defect interstitial the edge portion is perfect area.

As is apparent from FIG. 3, the wafer W ₁ corresponding to the position P ₁ includes a region in which vacancy type point defects predominantly exist in the center. The wafer W ₄ corresponding to the position P ₄ is
It includes a ring in which interstitial silicon type point defects predominantly exist and a central perfect region. Further, the wafer W ₃ corresponding to the position P ₃ is a perfect area because there is no void type point defect at the center and no interstitial silicon type point defect at the edge. The wafer W ₂ corresponding to the position P ₂ includes a region in which the vacancy type point defect is predominantly present in an area of 中央 of the total area of the wafer (50%) in comparison with the wafer W ₁ .

A small area in contact with the perfect area of the area where the vacancy type point defects are predominantly present is an area where neither COP nor LD is generated in the wafer surface. However, this silicon wafer is heat-treated at a temperature of 1000 ° C. ± 30 ° C. for 2 to 5 hours in an oxygen atmosphere according to the conventional OSF revealing heat treatment, and subsequently at a temperature of 1130 ° C. ± 30 ° C. for 1 to 16 hours. Heat treatment produces OSF. As shown in FIG. 4, OSF ring is generated in the vicinity of the peripheral edge of the wafer in the wafer W _1. COP tends to appear in a region surrounded by the OSF ring and in which vacancy-type point defects are predominantly present. On the other hand, in the wafer W ₂ OS
F occurs not in a ring shape but in a disk shape at the center of the wafer. Silicon wafers used in the present invention is a the wafer W _2, the wafer total area 25
% Or more OSF occurs. If the OSF is less than 25% of the total area of the wafer, oxygen precipitates (hereinafter referred to as BMD (Bulk Mic)
ro Defect). ) Occurs in a narrow area and sufficient IG
Less effective. Preferably it is 50-80%.

As shown in FIG. 5, the silicon wafer W ₂ of the present invention is obtained by slicing an ingot grown with a pulling speed profile selected and determined so that the OSF is not ring-shaped but becomes apparent at the center. It is made. FIG. 6 is a plan view thereof. In the silicon wafer W ₂ OS
Since F does not form a ring, it is COP-free.
Also, there is no occurrence of LD (interstitial dislocation). Ingot to produce a silicon wafer W ₂ of the present invention includes oxygen precipitates without dislocation at the rate of 1 × 10 ⁵ ~3 × 10 ⁷ cells / cm ^3. For this reason, as shown in Japanese Patent Application Laid-Open No.
Held at a relatively low temperature of ~ 800 ° C for 0.5-20 hours,
It is not necessary to introduce oxygen precipitation nuclei in the wafer at high density. When the BMD density is less than 1 × 10 ⁵ / cm ^3, it is difficult to obtain a sufficient IG effect when rapid heating is performed in a wafer state. 3 × 10 ⁷ / cm ³ is the maximum BMD density that can occur in the OSF region.

The rapid heating method of the present invention is preferably a method in which a silicon wafer at room temperature containing oxygen precipitates not accompanied by dislocation generation at the above ratio is quickly placed in a furnace heated to a temperature of 700 to 950 ° C. A silicon wafer at room temperature containing oxygen precipitates without the above-mentioned ratio is placed in a high-speed heating furnace using a lamp capable of generating high heat, a lamp switch is turned on, heat radiation is started, and a temperature of 700 to 950 ° C. is rapidly reached. May be used. Here, rapid heating means 1
This means that heat treatment is performed at a temperature rising rate of 0 ° C./min or more, preferably 30 ° C./min or more. When the wafer is rapidly heated by lamp light irradiation, the wafer can be uniformly heated, and therefore there is an advantage that the wafer is less likely to be warped as compared with a case where the wafer is placed in a preheated furnace. The final temperature reached by rapid heating is 7
If the temperature is lower than 00 ° C., the disappearance of the oxygen precipitate in the vicinity of the wafer surface is insufficient, and the DZ layer cannot be sufficiently secured. Also 95
If the temperature exceeds 0 ° C., dislocations occur before oxygen precipitates near the wafer surface disappear, and the DZ layer cannot be sufficiently secured.
Preferably it is 800-900 degreeC. If the holding time is less than 0.5 minutes, the time for reducing the oxygen precipitate on the wafer surface is too short, and the disappearance of the oxygen precipitate on the wafer surface is insufficient, so that a sufficient DZ layer cannot be secured. Also 30
If the amount exceeds the above range, a DZ layer having an unnecessarily thick thickness can be obtained, and the productivity is adversely affected. For this reason, the holding time is 0.
5 to 30 minutes. Preferably, it is 10 to 30 minutes. The rapid heating is performed in a nitrogen atmosphere, an oxygen atmosphere, or the air. Preferably, it is in a nitrogen atmosphere. After the rapid heating, when the silicon wafer is allowed to cool to room temperature, a DZ layer is formed over a depth of 1 to 100 μm from the wafer surface, and the BMD density in a portion deeper than the DZ layer is 1
An IG wafer of × 10 ^{5 to} 3 × 10 ⁷ pieces / cm ³ is obtained.

[0019]

Next, examples of the present invention will be described together with comparative examples. <Example 1> 1000 wafers under oxygen atmosphere
V / G shown in FIG. 1 is equal to or higher than the critical point so that OSF is generated in 25% of the total area of the wafer when heat-treated at 1100 ° C. for 2 hours and subsequently heat-treated at 1100 ° C. for 12 hours.
In a region of (V / G) ₁ or more and (V / G) ₂ or less, a silicon single crystal ingot was pulled from the silicon melt. The ingot corresponding to the position P ₂ where the full length thereof is shown in FIG. After lapping and chamfering the silicon wafer sliced from the pulled ingot, the wafer surface was damaged by chemical etching to obtain a mirror-finished wafer. The mirror surface wafer was heated from room temperature to 850 ° C. at a heating rate of 30 ° C./min, held for 5 minutes, and then allowed to cool to room temperature.

<Embodiment 2> 50% of the total area of the wafer is O
A wafer processed in the same manner as in Example 1 except that the ingot was pulled so as to generate SF was heated at 850 ° C. for 5 minutes at the same heating rate as in Example 1. <Example 3> A wafer processed in the same manner as in Example 1 was pulled at 850 ° C at the same heating rate as in Example 1 after pulling up the ingot so that OSF was generated in 80% of the total area of the wafer.
Heated for 0.5 minutes. <Example 4> After the ingot was pulled up so that OSF was generated in 80% of the total area of the wafer, the wafer processed in the same manner as in Example 1 was heated at 850 ° C at the same heating rate as in Example 1.
Heat for 5 minutes.

<Embodiment 5> 80% of the total area of the wafer is O
After pulling up the ingot so as to generate SF, the wafer processed in the same manner as in Example 1 was heated at 850 ° C. for 10 minutes at the same heating rate as in Example 1. <Example 6> A wafer processed in the same manner as in Example 1 was pulled at 850 ° C at the same heating rate as in Example 1 after pulling up the ingot so that OSF was generated in 80% of the total area of the wafer.
Heat for 20 minutes. <Example 7> After the ingot was pulled up so that OSF was generated in 80% of the total area of the wafer, the wafer processed in the same manner as in Example 1 was heated at 850 ° C at the same heating rate as in Example 1.
Heat for 30 minutes.

<Embodiment 8> 80% of the total wafer area is O
After pulling up the ingot so as to generate SF, the wafer processed in the same manner as in Example 1 was heated at the same heating rate as in Example 1 at 700 ° C. for 5 minutes. Example 9 A wafer processed in the same manner as in Example 1 was pulled at 800 ° C. at the same heating rate as in Example 1 after pulling up the ingot so that OSF was generated in 80% of the total area of the wafer.
Heat for 5 minutes. <Embodiment 10> A wafer processed in the same manner as in the first embodiment after pulling up the ingot so as to generate OSF in 80% of the total area of the wafer at the same temperature rising rate as that in the first embodiment is 950.
C., heated for 5 minutes.

<Comparative Example 1> O was added to 15% of the total area of the wafer.
After pulling up the ingot so as to generate SF, the wafer processed in the same manner as in Example 1 was heated at 850 ° C. for 5 minutes at the same heating rate as in Example 1. <Comparative Example 2> After the ingot was pulled up so that OSF was generated in 80% of the total area of the wafer, the wafer processed in the same manner as in Example 1 was heated at 650 ° C at the same heating rate as in Example 1.
Heat for 5 minutes. <Comparative Example 3> After the ingot was pulled up so that OSF was generated in 80% of the total area of the wafer, the wafer processed in the same manner as in Example 1 was subjected to the same heating rate as in Example 1 at 1000
C., heated for 5 minutes.

<Comparative Example 4> O was added to 80% of the total area of the wafer.
After pulling up the ingot so as to generate SF, the wafer processed in the same manner as in Example 1 was heated at 850 ° C. for 40 minutes at the same heating rate as in Example 1. <Comparative Evaluation> The silicon wafers of Examples 1 to 10 and Comparative Examples 1 to 4 were cleaved, and the surface of the wafer was further lighted (Wr).
ight) Selective etching was performed using an etching solution, and the width of the DZ layer and the oxygen precipitate (BMD) density at a depth of 250 μm from the wafer surface were measured by observation with an optical microscope. Table 1 shows the results. FIG. 7 shows a microphotograph of the BMD in the wafer after the rapid heating in Example 4 magnified 50,000 times.

[0025]

[Table 1]

As is clear from Table 1, after the IG heat treatment, the OSF region in Comparative Example 1 was too small at 15%, so that the BMD density is said to exhibit an IG effect of 10 ⁶ /.
cm ³ did not come. In Comparative Example 2, the DZ layer could not be formed on the wafer surface because the heat treatment temperature was too low at 650 ° C. In Comparative Example 3, the heat treatment temperature was 100
Since the temperature was too high at 0 ° C., an unnecessarily wide DZ layer was formed. Further, in Comparative Example 4, since the heat treatment time was too long, 40 minutes, an unnecessarily wide DZ layer was formed. On the other hand, in the silicon wafers of Examples 1 to 10, the BMD density is considered to have an IG effect of 10 ⁶ to 10 ^7.
/ Cm ³ units. In particular, in Examples 3 to 8 in which the OSF region is 80%, the BMD density is on the order of 10 ⁷ / cm ³ , of which Examples 5 to 7 in which the heat treatment time is 10 to 30 minutes and Example 10 in which the heat treatment temperature is 950 ° C. As a result, a wide DZ layer of 45 to 85 μm was obtained. Also, from the micrograph of FIG.
It can be seen that oxygen precipitates present in the wafer after the rapid heat treatment are accompanied by dislocations.

[0027]

As described above, according to the present invention, silicon thermal treatment is performed so that oxidation-induced stacking faults (OSF) occur in at least 25% of the total area of the wafer when the wafer is subjected to thermal oxidation treatment. Using an ingot containing 1 × 10 ^{5 to} 3 × 10 ⁷ oxygen precipitates / cm ³ , which is pulled up from the solution and does not involve dislocation generation, a wafer cut from the ingot is heated at a temperature of 700 to 950 ° C. Rapid heating at low temperature eliminates the need for conventional pre-heat treatment and oxygen precipitation nucleus growth steps to introduce oxygen precipitation nuclei in the wafer,
The wafer cut from the ingot and immediately after grinding and polishing can be made into a wafer having a high IG capability with a small number of heat treatments.

[Brief description of the drawings]

FIG. 1 is a diagram based on Bornkov's theory showing that when the V / G ratio is above the critical point, a vacancy-rich ingot is formed, and when the V / G ratio is below the critical point, an interstitial silicon-rich ingot is formed. .

FIG. 2 is a characteristic diagram showing a change in pulling speed for determining a desired pulling speed profile.

FIG. 3 shows a porosity-rich region of a reference ingot according to the invention,
X indicating interstitial silicon-rich region and perfect region
Schematic diagram of line topography.

FIG. 4 shows a silicon wafer W ₁ corresponding to a position P ₁ in FIG.
The figure which shows the situation in which an OSF ring appears.

5 is a cross-sectional view sliced in the axial direction through the axial center of the ingot corresponding to the position P ₁ in FIG.

FIG. 6 shows a silicon wafer W ₂ corresponding to a position P ₂ in FIG.
The figure which shows the situation in which OSF appears in the center part of FIG.

FIG. 7 is a photomicrograph showing the state of oxygen precipitates in the wafer after rapid heating in Example 4.

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[Procedure amendment]

[Submission date] July 28, 1999 (July 7, 1999
8)

[Procedure amendment 1]

[Document name to be amended] Drawing

[Correction target item name] Fig. 7

[Correction method] Change

[Correction contents]

FIG. 7

Claims (3)

[Claims] 1. A silicon wafer cut from a silicon single crystal ingot and immediately after grinding and polishing is removed from room temperature by 70
An IG processing method in which the silicon single crystal ingot is rapidly heated to 0 to 950 ° C. at a rate of 10 ° C./min or more and maintained for 0.5 to 30 minutes, and the silicon single crystal ingot is thermally oxidized in a silicon wafer state. At this time, the silicon precipitate was pulled up from the silicon melt so that oxidation-induced stacking faults occurred in 25% or more of the total area of the wafer, and oxygen precipitates without dislocation generation were reduced to 1 × 10 5
An IG treatment method comprising ^{5 to} 3 × 10 ⁷ particles / cm ³ . 2. An IG wafer produced from the IG processing method according to claim 1, wherein a layer on which no oxygen precipitate is formed is 1 to 1 from the wafer surface.
An IG wafer formed over a depth of 00 μm and having 1 × 10 ^{5 to} 3 × 10 ⁷ / cm ³ oxygen precipitates in a portion deeper than the layer. 3. A silicon single crystal ingot pulled from a silicon melt so as to generate oxidation-induced stacking faults in at least 25% of the total area of the wafer when the silicon wafer is subjected to a thermal oxidation treatment, wherein the dislocation is 1 × 10 ⁵ to 1 × 10 ⁷ oxygen precipitates without generation
Silicon single crystal ingot for IG wafers, characterized in that the ingot contains 1 / cm ³ .