JP5278324B2 - Manufacturing method of silicon single crystal wafer for IGBT - Google Patents

Description

The present invention relates to an IGBT silicon single crystal wafer used for manufacturing an insulated gate bipolar transistor (IGBT) and a method for manufacturing an IGBT silicon single crystal wafer.
This application claims priority on August 29, 2007 based on Japanese Patent Application No. 2007-2223065 for which it applied to Japan, and uses the content for it here.

Insulated Gate Bipolar Transistor (hereinafter referred to as IGBT) is a gate voltage-driven switching element suitable for controlling high power, and is used for inverters in trains, hybrid vehicles, air conditioners, refrigerators, etc. It has been. As shown in FIGS. 5A to 5C, the IGBT is provided with three electrodes, ie, an emitter E, a collector C, and a gate G. The gate is formed on the surface side of the element via an insulating oxide film SiO _2. The current between the emitter E on the device surface side and the collector C on the back surface side is controlled by the applied voltage.
As described above, since the IGBT is an element that controls current with a gate insulated by an oxide film, the quality of the gate oxide film (hereinafter referred to as GOI) is important. If a defect is included in the silicon single crystal wafer, the defect is taken into the gate oxide film and causes a dielectric breakdown of the oxide film.

Further, the IGBT is not an element that uses only the vicinity of the surface of the wafer in the horizontal direction like an LSI such as a memory, but is an element that uses the wafer in the vertical direction (thickness direction) as shown in FIGS. 5A to 5C. Properties are affected by the bulk quality of the wafer. In particular, recombination lifetime and resistivity are important qualities. Since the recombination lifetime is reduced by crystal defects in the substrate, it is necessary to control so that no crystal defects occur even after the device process. Regarding the resistivity, uniformity and stability are required. It is important that it is uniform not only in the plane of the wafer but also between the wafers, that is, in the length direction of the silicon ingot, and does not change even after the device thermal process.
If a plurality of received elements on the wafer plane, that is, a plurality of elements are provided in parallel, if the resistivity differs between these elements, a large current concentrates on the low resistivity element and breaks. Therefore, the uniformity and stability of the resistivity are important. As described above, when a plurality of elements are miniaturized in parallel, a large current is concentrated due to the difference in resistivity, and the current is concentrated on a specific element, resulting in damage. It is important that the process does not change.

Further, as shown in FIG. 5A, as a substrate for a so-called punch through (hereinafter referred to as PT) type IGBT in which the depletion layer contacts the collector side when the current is turned off, an epitaxial wafer (hereinafter referred to as an epi wafer) is used. Is used. However, the PT type IGBT has a problem of high cost because it uses an epi-wafer. Also, switching loss increases at high temperatures for lifetime control. For this reason, the ON voltage decreases at a high temperature, and current may concentrate on a specific element during parallel use, causing damage.
In order to overcome the drawbacks of the PT-type substrate, a non-punch through (hereinafter referred to as NPT) type IGBT in which the depletion layer does not contact the collector side at the time of OFF has been developed. More recently, an FS-IGBT having a trench gate structure and a field stop (hereinafter referred to as FS) layer formed on the collector side as shown in FIG. It has come to be manufactured. As a substrate for an NPT type or FS type IGBT, a wafer having a diameter of 150 mm or less (hereinafter referred to as an FZ wafer) cut out from a silicon single crystal conventionally grown by a floating zone method (hereinafter referred to as FZ method). ) Is used.

Although the FZ wafer is cheaper than the epi wafer, it is necessary to increase the diameter of the wafer in order to further reduce the manufacturing cost of the IGBT. However, it is extremely difficult to grow a single crystal having a diameter larger than 150 mm by the FZ method, and even if it can be produced, it is difficult to stably supply it at a low price.
Therefore, we tried to manufacture a silicon single crystal wafer for IGBT by the Czochralski method (CZ method) that can easily grow a large diameter crystal of φ200 mm or more, preferably φ300 mm or more.

The techniques described in Patent Documents 1 to 3 described below are all aimed at reducing defects in the wafer. In Patent Document 1, the entire surface is grown by the CZ method and doped with nitrogen. A silicon single crystal consisting of an N-region, having an interstitial oxygen concentration of 8 ppma or less, or doped with nitrogen, excluding at least void-type defects and dislocation clusters from the entire surface, and having an interstitial oxygen concentration of 8 ppma or less A wafer is disclosed.
Patent Document 2 discloses a method for producing a silicon single crystal that is pulled up using the Czochralski method while being doped with oxygen and nitrogen, and 6.5 × 10 ¹⁷ atoms / day while the single crystal is pulled up. A method for producing a silicon single crystal doped with oxygen at a concentration of less than cm ³ and nitrogen at a concentration of more than 5 × 10 ¹³ atoms / cm ³ is disclosed.
Further, in Patent Document 3, a nitrogen concentration of 2 × 10 ¹⁴ atoms / cm ³ or more and 2 × 10 ¹⁶ atoms / cm ³ or less grown from a melt added with nitrogen by the Czochralski method, and 7 × 10 ¹⁷ atoms is used. Containing oxygen concentration of / cm ³ or less, various surface defect densities are FPD ≦ 0.1 / cm ² , SEPD ≦ 0.1 / cm ² , and OSF ≦ 0.1 / cm ² , A silicon semiconductor substrate is disclosed in which the defect density is LSTD ≦ 1 × 10 ⁵ / cm ³ and the oxide film breakdown voltage characteristics are TZDB high C mode pass rate ≧ 90% and TDDB pass rate ≧ 90%.
JP 2001-146498 A JP 2000-7486 A JP 2002-29891 A

However, although Patent Documents 1 to 3 disclose a wafer manufacturing method that is free of crystal defects, the wafer characteristics necessary for the IGBT are not clarified. In order to grow a crystal having defect-free CZ silicon having an interstitial oxygen concentration of 7 × 10 ¹⁷ atoms / cm ³ or less and a variation in resistivity within a wafer surface of 5% or less, a quartz crucible is rotated. The speed and the rotation speed of the crystal need to be significantly changed from the conventional conditions, and the pulling speed margin for growing defect-free crystals is reduced, resulting in a decrease in yield.
Conventionally, as an EG process, a polycrystalline silicon layer as a gettering layer is formed on the back side of the wafer to remove heavy metal contamination in the IGBT manufacturing process. It is preferable not to do this because it leads to an increase in manufacturing costs. However, in the IGBT device process, it is necessary to have gettering ability, and an IGBT silicon single crystal wafer having IG ability without being subjected to EG has been demanded.

  The present invention has been made in view of the above circumstances, and can increase the pulling speed margin, does not require EG treatment, and has a sufficiently thick DZ layer as an IGBT wafer. In addition, an object of the present invention is to provide an IGBT silicon single crystal wafer manufacturing method and an IGBT silicon single crystal wafer capable of manufacturing a wafer having an IG capability and a small variation in resistivity.

When a silicon single crystal wafer is manufactured by the Czochralski method (hereinafter sometimes referred to as the CZ method), a wafer having a large diameter of about 300 mm can be manufactured. The wafer manufactured by the CZ method is For this reason, it is not suitable for an IGBT wafer.
(1) In the CZ method, excessive vacancies aggregate when a single crystal is grown, and COP defects (Crystal Originated Particles) of about 0.2 to 0.3 μm are generated. When manufacturing an IGBT, a gate oxide film is formed on the wafer surface. When a COP defect is exposed on the wafer surface or a COP defect existing in the vicinity of the wafer surface is taken into the gate oxide film. Degrading GOI (Gate Oxide Integrity). Therefore, a wafer that does not contain COP defects is necessary so that the GOI does not deteriorate, but it is difficult to manufacture a defect-free wafer by the CZ method.
(2) The silicon single crystal wafer manufactured by the CZ method contains excess oxygen of about 1 × 10 ¹⁸ atoms / cm ³ , and such a wafer has a low temperature of about 1 hour at 450 ° C. When heat treatment (heat treatment corresponding to the sintering process in the IGBT manufacturing process) is performed, oxygen donors are generated, and the resistivity of the wafer changes before and after the heat treatment.
(3) The resistivity of a silicon single crystal wafer manufactured by the CZ method can be controlled by the amount of dopant added to the silicon melt, and phosphorus is added as a dopant to an IGBT wafer, but phosphorus has a segregation coefficient. Since it is small, the concentration greatly changes along the length direction of the silicon single crystal. Therefore, within a single silicon single crystal, the range of wafers having a resistivity that matches the design specifications is narrow.
(4) The silicon single crystal wafer manufactured by the CZ method contains excess oxygen of about 1 × 10 ¹⁸ atoms / cm ^3. Oxygen precipitates as SiO ₂ and degrades the recombination lifetime.

(5) CZ silicon contains about 10 × 10 ¹⁷ atoms / cm ³ of oxygen, and when subjected to a low-temperature heat treatment at about 450 ° C. for about 1 hour in an IGBT device process, oxygen donors are generated and the resistance of the substrate The rate will change. In addition, in the nitrogen-doped crystal, a heat treatment (typically 650 ° C. × 30 minutes) for eliminating the oxygen donor is performed. However, in the device process, for example, sintering of Al wiring is performed at a temperature around 450 ° C. For this reason, there is a problem that the resistivity in the device region where the IGBT device is formed becomes higher than the resistivity at the time of wafer shipment when the device manufacturing process is performed. For this reason, in order to improve the handling property in the device process adjacent to the device region, the oxygen precipitate BMD does not exist in the device region which is about 100 to 200 μm in the depth direction from the wafer outermost surface. In order to have a gettering (IG) effect, a wafer having sufficient BMD in this region has been demanded.

  In order to solve the above problems (1) to (5), the present inventors have conducted intensive research. As a result, by adopting the following configuration, a wafer having the wafer characteristics necessary for the IGBT is obtained as CZ. It was found that it can be manufactured by the method.

The method for producing a silicon single crystal wafer for IGBT of the present invention is a method for producing a silicon single crystal wafer for IGBT obtained by growing a silicon single crystal by the Czochralski method,
A pulling step of growing a single crystal having an interstitial oxygen concentration of 8.5 × 10 ¹⁷ atoms / cm ³ or less at a speed capable of pulling a silicon single crystal at a growth rate of a grown -in defect-free silicon single crystal ;
A hole injection step of performing RTA treatment of a wafer sliced from the single crystal at 1175 ° C. or higher;
After the hole injecting step, heat treatment is performed at a temperature range of 1000 ° C. to 1100 ° C. for a processing time of 1 to 16 hours to form an IGBT device having a thickness direction dimension of 100 to 200 μm on the surface side of the entire wafer surface. A hole-control heat treatment step for forming a device region and a gettering region to be removed after device formation on the back side of the device region;
Have
When a silicon single crystal is grown by the Czochralski method, an n-type dopant is added to the silicon melt, or phosphorus is added to the silicon melt at 2.9 × 10 ¹³ atoms / cm ³ or more to 2.9 × 10 ¹⁵ atoms. / cm ³ or less, the Do p-type dopant small segregation coefficient than the phosphorus, so that the concentration in the crystal in accordance with the segregation coefficient becomes 1 × 10 ¹⁵ atoms / cm ³ or less 1 × 10 ¹³ atoms / cm ³ or more It is characterized in that phosphorus is doped by adding neutron irradiation to the silicon single crystal after being added to the silicon single crystal.
The silicon single crystal wafer for IGBT of the present invention is a silicon single crystal wafer for IGBT composed of a silicon single crystal grown by the Czochralski method,
A device region provided on the entire surface of the wafer and having an IGBT device formed on the front surface side, and a gettering region located on the back side of the device region and removed after device formation;
The thickness direction dimension of the device region is 100 to 200 μm,
COP defects and dislocation clusters are eliminated in the entire crystal diameter direction, the interstitial oxygen concentration is 8.5 × 10 ¹⁷ atoms / cm ³ or less, and the variation in resistivity within the wafer surface is 5% or less. It is Ru can.
In the device region, the oxygen precipitate density of 20 nm or more is 5 × 10 ³ pieces / cm ³ or less after the IGBT device process heat treatment in the device region, and 20 nm after the IGBT device process heat treatment in the gettering region. The oxygen precipitate density can be 5 × 10 ⁴ pieces / cm ³ or more and 1 × 10 ⁷ pieces / cm ³ or less.
In the present invention, the silicon single crystal may have 5 × 10 ¹² atoms / cm ³ or more and 5 × 10 ¹⁵ atoms / cm ³ or less, or 1 × 10 ¹³ atoms / cm ³ or more and 5 × 10 ¹⁵ atoms / cm ³ or less. Nitrogen can be doped.
In the present invention, the silicon single crystal is grown at a pulling speed capable of pulling a grown-in defect-free silicon single crystal when grown by the Czochralski method, and the silicon after pulling The single crystal may be formed by neutron irradiation and doping with phosphorus.
The method for producing a silicon single crystal wafer for IGBT of the present invention is a method for producing a silicon single crystal wafer for IGBT obtained by growing a silicon single crystal by the Czochralski method,
A pulling step of growing a single crystal having an interstitial oxygen concentration of 8.5 × 10 ¹⁷ atoms / cm ³ or less at a speed capable of pulling a silicon single crystal at a growth rate of a grown-in defect-free silicon single crystal;
A hole injection step of performing RTA treatment of a wafer sliced from the single crystal at 1175 ° C. or higher;
After the hole injecting step, heat treatment is performed at a temperature range of 1000 ° C. to 1100 ° C. for a processing time of 1 to 16 hours to form an IGBT device having a thickness direction dimension of 100 to 200 μm on the surface side of the entire wafer surface. A hole-control heat treatment step for forming a device region and a gettering region to be removed after device formation on the back side of the device region;
Ru can have.
In the present invention, the silicon single crystal can be doped with nitrogen of 5 × 10 ¹² atoms / cm ³ or more and 5 × 10 ¹⁵ atoms / cm ³ or less.
According to the present invention, a hydrogen atom-containing substance having a hydrogen gas equivalent partial pressure in the range of 40 Pa or more and 400 Pa or less can be introduced into the atmospheric gas in the CZ furnace.
In the present invention, when a silicon single crystal is grown by the Czochralski method, an n-type dopant is added to the silicon melt, or phosphorus is added to the silicon melt at 2.9 × 10 ¹³ atoms / cm ³ or more and 2.9. A p-type dopant having a segregation coefficient smaller than that of phosphorus is 10 × ¹⁵ atoms / cm ³ or less, and the concentration in the crystal is 1 × 10 ¹³ atoms / cm ³ or more and 1 × 10 ¹⁵ atoms / cm ³ depending on the segregation coefficient. Phosphorus can be doped by adding to the following or by irradiating the pulled silicon single crystal with neutrons.

The silicon single crystal wafer for IGBT of the present invention is a silicon single crystal wafer for IGBT composed of a silicon single crystal grown by the Czochralski method,
A device region provided on the entire surface of the wafer and having an IGBT device formed on the front surface side, and a gettering region located on the back side of the device region and removed after device formation;
The thickness direction dimension of the device region is 100 to 200 μm,
COP defects and dislocation clusters are eliminated in the entire crystal diameter direction, the interstitial oxygen concentration is 8.5 × 10 ¹⁷ atoms / cm ³ or less, and the variation in resistivity within the wafer surface is 5% or less. As a result, BMD does not occur in the device region where the IGBT is formed (wafer outermost surface to hundreds of tens of μm), and in the thickness region that is removed by back grinding, ) Can be provided with a wafer in which BMD is intentionally made by RTA processing. As a result, in the device region, there is no change in resistivity that affects the device characteristics as being defect-free, and EG processing is performed without performing EG processing, and handling capability in the device process is improved. It is possible to improve and prevent heavy metal contamination that affects device manufacturing.

  In wafers that have been subjected to vacancy injection processing by RTA in a mixed atmosphere of argon and nitrogen, vacancy existing in the surface layer is stable when low-temperature heat treatment from 600 ° C to 900 ° C is performed for a long time during the initial device process. Turn into. As a result, BMD is formed with a high density in a device region having a thickness of 100 to 200 μm or 150 μm from the surface layer in a subsequent heat treatment step in the device process, which causes deterioration in IGBT characteristics. Therefore, by performing heat treatment of the vacancies near the surface layer injected by the vacancy injection RTA process at a temperature of 1000 ° C. to 1100 ° C. for about 1 to 16 hours after the RTA process, about 150 μm from the outermost surface of the wafer. It is possible to provide a silicon single crystal wafer for IGBT in which oxygen precipitation does not occur in the device region and oxygen precipitation occurs at a deeper position. If an IGBT is manufactured using such a wafer through an IGBT device process, after the device is formed, the portion on the back side deeper than the device region is removed and the thickness is reduced before the thinning step (back grinding step). The device region (device active region) can be protected from metal contamination by the gettering (IG) effect of BMD included in a deep position of 150 μm or more from the outermost surface. Since the portion of the deep region including the BMD is removed by the back grinding, the completed IGBT element does not include the BMD, and hence the IGBT characteristics are not deteriorated by the BMD. Moreover, since the silicon single crystal wafer for IGBT according to the present invention has IG capability in the wafer from the beginning in the device process, the manufacturing cost can be reduced by omitting the EG processing such as polysilicon film formation processing (PBS) on the back surface. Is also possible.

In the device region, the oxygen precipitate density of 20 nm or more is 5 × 10 ³ pieces / cm ³ or less after the device process heat treatment for IGBT in the device region, and 20 nm after the device process heat treatment for IGBT in the gettering region. When the oxygen precipitate density is 5 × 10 ⁴ pieces / cm ³ or more and 1 × 10 ⁷ pieces / cm ³ or less, a gettering region having sufficient gettering capability on the device region side inside the gettering region It is possible to provide a wafer having a device region that is homogeneous in the wafer thickness direction inside the device region and has a device region in which the IGBT characteristics do not deteriorate after the IGBT device process.
Specifically, in the wafer thickness direction from the wafer outermost surface, oxygen precipitation does not occur even after passing through the IGBT device process, that is, a device region having a uniform thickness dimension of about 100 to 200 μm in which BMD is not detected, and this In contact with the device region, through the IGBT device process, the BMD is approximately homogeneous in the wafer thickness direction and the density of oxygen precipitates of 20 nm or more is 5 × 10 ⁴ pieces / cm ³ or more and 1 × 10 ⁷ pieces / cm ³ or less. A wafer having a layer and a back side region having the same characteristics as the device region from the BMD layer to the back surface of the wafer can be obtained.

Furthermore, the silicon single crystal wafer for IGBT of the present invention is an IGBT silicon single crystal wafer made of silicon single crystal grown by the Czochralski method, and COP defects and dislocation clusters are eliminated in the entire crystal diameter direction. The interstitial oxygen concentration is 8.5 × 10 ¹⁷ atoms / cm ³ or less, and the resistivity variation within the wafer surface is 5% or less.
Furthermore, in the silicon single crystal wafer for IGBT of the present invention, the silicon single crystal is grown at a pulling speed capable of pulling up the grown-in defect-free silicon single crystal when grown by the Czochralski method. It is preferable that the silicon single crystal after being pulled is irradiated with neutrons and doped with phosphorus.
Further, in the silicon single crystal wafer for IGBT of the present invention, when the silicon single crystal is grown by the Czochralski method, the grown-in defect free from the silicon melt doped with the n-type dopant. It is preferable that the silicon single crystal is grown at a pulling speed capable of pulling up.
Furthermore, in the silicon single crystal wafer for IGBT of the present invention, the silicon single crystal is preferably doped with nitrogen of 5 × 10 ¹² atoms / cm ³ or more and 5 × 10 ¹⁵ atoms / cm ³ or less.

Furthermore, in the silicon single crystal wafer for IGBT of the present invention, the pass rate of TZDB at a breakdown electric field of 8 MV / cm is 90% or more, and oxygen donors generated when heat treatment is performed at 450 ° C. for 1 hour. The density is 9.8 × 10 ¹² pieces / cm ⁻³ or less, and the density of BMD deposited when two-stage heat treatment is performed at 800 ° C. for 4 hours and 1000 ° C. for 16 hours is 5 × 10 ⁷ pieces / cm 3. It is preferably ⁻³ or less, and the recombination lifetime when the two-stage heat treatment is performed is preferably 100 μsec or more.
Furthermore, in the silicon single crystal wafer for IGBT of the present invention, phosphorus and a p-type dopant having a segregation coefficient smaller than that of phosphorus are 1 × 10 ¹³ atoms / cm ³ or more and 1 × 10 ¹⁵ atoms / cm ^{3, respectively.} It is preferably contained at the following concentrations.
Furthermore, in the silicon single crystal wafer for IGBT of the present invention, the LPD density on the wafer surface is 0.1 piece / cm ² or less, and the light etching defect density is 1 × 10 ³ pieces / cm ² or less. Is preferred.

  In the present invention, the variation in resistivity is measured at a total of three locations: the wafer center, a position between the wafer center and the periphery, and a position 5 mm from the wafer periphery. The maximum value and the minimum value are selected, and the value is obtained by the formula of (maximum value−minimum value) × 100 / minimum value.

Further, in the present invention, “Grown-in defect-free” means that all defects that may occur with crystal growth such as COP defects and dislocation clusters are eliminated.
Further, in the present invention, the OSF region means that the temperature is raised from 900 ° C. to 1000 ° C. in a dry oxygen atmosphere at a rate of temperature rise of 5 ° C./min, then in a dry oxygen atmosphere at 1000 ° C. for 1 hour, and then in a wet oxygen atmosphere After heating at 1000 ° C. to 1150 ° C. at a rate of temperature increase of 3 ° C./min, heat treatment is performed at 1150 ° C. for 2 hours in a wet oxygen atmosphere and then to 900 ° C., and then 2 μm light etching is performed to form the OSF region. This means a region where the OSF density is 10 / cm ² when the OSF density is measured and the distribution of the OSF density in the wafer is measured.

  The Pv region and the Pi region are silicon single crystal ingots grown by the Czochralski method, and a region where interstitial silicon type point defects exist predominantly in the ingot is defined as an I region, When a region in which defects exist predominantly is a V region, and a region in which no interstitial silicon type point defect aggregates and no vacancy type point defect aggregates exist is a P region, The region below the lowest interstitial silicon concentration that belongs to the P region and can form interstitial dislocations is defined as the Pi region, and the region that is adjacent to the OSF region and that is below the vacancy concentration that can belong to the P region and form COP is defined as Pv. This is an area.

  A silicon wafer is produced by pulling up an ingot from a silicon melt in a furnace by a CZ method with a predetermined pulling speed profile based on Boronkov theory, and then cutting out the ingot. In general, when an ingot of a silicon single crystal is pulled from a silicon melt in a furnace by the CZ method, point defects and agglomerates of point defects (agglomerates: three-dimensional defects) are generated as defects in the silicon single crystal. Will occur. There are two general forms of point defects: vacancies and interstitial silicon. A vacancy is one in which one silicon atom leaves one of its normal positions in the silicon crystal lattice. On the other hand, silicon atoms existing at positions (interstitial sites) other than the lattice points of the silicon crystal are interstitial silicon atoms.

  Point defects are generally formed at the contact surface between a silicon melt (molten silicon) and an ingot (solid silicon). However, by continuously pulling up the ingot, the portion that was the contact surface begins to cool as it is pulled up. During cooling, vacancies or interstitial silicon atoms diffuse to form dislocation clusters that are COPs that are vacancy aggregates or interstitial agglomerates. In other words, the aggregate is a three-dimensional structure generated due to the merge of point defects. The agglomerates of vacancy-type point defects include defects called LSTD (Laser Scattering Tomography Defects) or FPD (Flow Pattern Defects) in addition to the above-mentioned COP. Including defects. FPD is a unique flow that appears when a silicon wafer produced by cutting out an ingot is subjected to Secco etching (Secco etching, HF: K2 Cr2O7 (0.15 mol / l) = 2: 1 mixed solution) for 30 minutes. LSTD is a source that generates a scattered light having a refractive index different from that of silicon when an infrared ray is irradiated into a silicon single crystal.

Boronkov's theory is that in order to grow a high purity ingot with a small number of defects, the ingot pulling speed is V (mm / min), and the temperature gradient in the vertical direction of the ingot near the interface between the ingot and the silicon melt is G (° C. / Mm) is to control V / G (mm ² / min · ° C.).

  Corresponding to the change of the V / G value from a high value to a low value, the above-described V region, OSF region, Pv region, Pi region, and I region are arranged in this order. For this reason, G (° C./mm) specific to the pulling apparatus is calculated by electrothermal analysis software, a pulling experiment in which the pulling speed is gradually reduced is carried out, and the single crystal pulling length defect obtained thereby By examining the distribution in advance, the pulling speed V (mm / min) necessary for obtaining the Pv region, the Pi region, and the I region can be calculated. Alternatively, the value of V / G varies depending on each actual machine, such as the structure of the hot zone in the upper part of the pulling furnace, but by measuring the COP density, OSF density, BMD density, LSTD density or FPD, light etching defect density, etc. It can be determined.

“Light etching defects” means that an As-Grown silicon single crystal wafer is immersed in an aqueous copper sulfate solution and then air-dried, and then subjected to Cu decoration for about 20 minutes at 900 ° C. in a nitrogen atmosphere. In order to remove the Cu silicide layer on the surface of the specimen, it was immersed in a HF / HNO ₃ mixed solution, and the surface layer was etched and removed by several tens of microns, and then the wafer surface was etched by 2 μm light etching (chromic acid etching). And defects detected using an optical microscope. According to this evaluation method, the dislocation clusters formed at the time of crystal growth can be revealed by Cu decoration, and the dislocation clusters can be detected with high sensitivity. That is, the light etching defect includes a dislocation cluster.
In the present invention, the “LPD density” is a density of defects of 0.1 μm size or more detected using a laser light scattering particle counter (SP1 (surfscan SP1): manufactured by KLA-Tencor).

Further, TZDB is an abbreviation for Time Zero Dielectric Breakdown, and is one of the indexes representing GOI. The pass rate of TZDB in the present invention was determined by measuring the current-voltage curve at about 416 locations across the wafer under the conditions that the electrode area of the measurement electrode was 8 mm ² and the judgment current was 1 mA. The probability of not having occurred is taken as the pass rate of TZDB. This pass rate is also called a C-mode pass rate.

  According to the silicon single crystal wafer of the present invention, a gettering region which is homogeneous and has sufficient gettering capability over the entire region in the wafer surface direction, and is uniform over the entire region in the wafer surface direction and after the IGBT device process during and after the IGBT device process. It has a device region in which the characteristics are not deteriorated, and COP defects and dislocation clusters are eliminated in the entire crystal diameter direction, so that it is suitable as a wafer for IGBT which is an element that uses the wafer in the vertical direction. That is, since COP defects and dislocation clusters are eliminated in the entire crystal diameter direction, the COP defects are not taken into the gate oxide film when the gate oxide film is formed on the wafer surface in the IGBT manufacturing process, and the GOI is deteriorated. I will not let you. Moreover, since dislocation clusters are eliminated and oxygen precipitates (BMD) are reduced, leakage current at the p / n junction can be prevented.

Further, since the interstitial oxygen concentration is 8.5 × 10 ¹⁷ atoms / cm ³ or less, the concentration of oxygen donor generated after the heat treatment of the wafer can be suppressed to 9.8 × 10 ¹² atoms / cm ³ or less. Thus, the change in the resistivity of the wafer can be prevented, and the quality of the silicon single crystal wafer can be stabilized.
The reason why the oxygen donor concentration is 9.8 × 10 ¹² atoms / cm ³ or less is as follows. An n-type wafer having a resistivity of 40 to 70 Ω · cm is used for the high voltage IGBT. For example, when the resistivity specification of the substrate is 50 ± 5 Ω · cm, the allowable donor concentration is 9.8 × 10 ¹² ions / cm ³ or less. Here, the temperature at which oxygen donors due to oxygen are most likely to be generated is 450 ° C. For example, in the device process, sintering of Al wiring is performed around this temperature. FIG. 1 shows the results of examining the oxygen concentration dependence of the oxygen donor concentration generated when heat treatment is performed at 450 ° C. for 1 hour. From FIG. 1, in order to suppress the oxygen donor concentration to 9.8 × 10 ¹² atoms / cm ³ or less, the interstitial oxygen concentration of the wafer must be controlled to 8.5 × 10 ¹⁷ atoms / cm ³ or less. I understand that. For these reasons, in the present invention, the interstitial oxygen concentration can be 8.5 × 10 ¹⁷ atoms / cm ³ or less.

In addition, in the normal CZ method, it may be difficult to reduce the interstitial oxygen concentration to 8.5 × 10 ¹⁷ atoms / cm ³ or less. In this case, the MCZ method is used to grow a single crystal by applying a magnetic field. The interstitial oxygen concentration can be 8.5 × 10 ¹⁷ atoms / cm ³ or less. The interstitial oxygen concentration can also be reduced by reducing the rotation speed of the quartz crucible and the single crystal to be pulled up.
Specifically, as shown in FIG. 10, the quartz crucible rotation speed R1 (rpm) and the crystal rotation speed R2 (rpm)
As shown by each point (R1, R2) in FIG.
Point A (0.1,1), Point B (0.1,7), Point C (0.5,7), Point D (0.7,6), Point E (1,6), Point F It can be set to a value within a range surrounded by (2, 2) and point G (2, 1). Thereby, a single crystal having an interstitial oxygen concentration of 4 × 10 ¹⁷ atoms / cm ³ or less can be grown. Substantially, when the rotation speed of the quartz crucible is R1 (rpm) and the rotation speed of the crystal is R2 (rpm), the range is R1: 0.1 or more and 2 or less, R2: 1 or more and 7 or less, When R1: 0.5 or more and 0.7 or less, R2 <7-5 (R1-0.5) is satisfied, and when R1: 0.7 or more and 1 or less, R2 <6 is satisfied, and R1: 1 In the case of 2 or less, it can be set in a range satisfying R2 <6-4 (R1-1). In this case, a silicon single crystal having a low oxygen concentration can be grown by setting the interstitial oxygen concentration in the single crystal to 4.0 × 10 ¹⁷ atoms / cm ³ or less.
For this reason, when this low oxygen single crystal is subjected to a low temperature heat treatment of about 450 ° C. with a small variation in resistivity and an extremely small density of oxygen precipitates even after the IGBT manufacturing process, an oxygen donor is generated, It is possible to provide a silicon single crystal wafer for IGBT that can prevent the resistivity of the substrate from changing.

Further, the quartz crucible rotation speed R1 (rpm) and the crystal rotation speed R2 (rpm)
As shown by each point (R1, R2) in FIG.
Point A (0.1,1), point B (0.1,7), point L (0.2,7), point K (0.3,7), point J (0.5,6), Pulling up the silicon single crystal by setting the value within the range surrounded by point I (0.7,6), point H (1,5), point N (1,3), and point M (1,1) Thus, a silicon single crystal having a lower oxygen concentration can be grown by setting the interstitial oxygen concentration in the single crystal to 3.5 × 10 ¹⁷ atoms / cm ³ or less. Substantially, the quartz crucible rotation speed R1 (rpm) and the crystal rotation speed R2 (rpm) are in the range of R1: 0.1 or more and 2 or less, R2: 1 or more and 7 or less, provided that R1: 0. In the case of 3 or more and 0.5 or less, R2 <7-5 (R1-0.3) is satisfied, and in the case of R1: 0.5 or more and 0.7 or less, R2 <6 is satisfied, and R1: 0. In the case of 7 or more and 1 or less, it may be set in a range satisfying R2 <6-3.4 (R1-0.7). In this case, a silicon single crystal having a low oxygen concentration can be provided by setting the interstitial oxygen concentration in the single crystal to 3.5 × 10 ¹⁷ atoms / cm ³ or less.

Further, the quartz crucible rotation speed R1 (rpm) and the crystal rotation speed R2 (rpm)
As shown by each point (R1, R2) in FIG.
Point A (0.1,1), point B (0.1,7), point L (0.2,7), point Q (0.3,6), point J (0.5,6), The silicon single crystal may be pulled up by setting a value within a range surrounded by the points P (0.7, 5), N (1, 3), and M (1, 1). Substantially, the quartz crucible rotation speed R1 (rpm) and the crystal rotation speed R2 (rpm) are in the range of R1: 0.1 or more and 1 or less, R2: 1 or more and 7 or less, provided that R1: 0. When 2 or more and 0.3 or less, R2 <7-10 (R1-0.2) is satisfied, and when R1: 0.3 or more and 0.5 or less, R2 <6 is satisfied, and R1: 0.5 In the case of 0.7 or more and 0.7 or less, R2 <6-5 (R1-0.5) is satisfied, and in the case of R1: 0.7 or more and 1 or less, R2 <5-6.7 (R1-0.7) Can be set in a range that satisfies the above. In this case, a silicon single crystal having an interstitial oxygen concentration of 3.0 × 10 ¹⁷ atoms / cm ³ or less in the single crystal can be grown, and a silicon single crystal having a lower oxygen concentration can be grown.
Table 5 shows the relationship among the quartz crucible rotation speed R1 (rpm), the crystal rotation speed R2 (rpm), and the interstitial oxygen concentration.

In the present invention, the magnetic field applied to the silicon melt can be a horizontal magnetic field, a cusp magnetic field, or the like. For example, the intensity of the horizontal magnetic field is 3000 to 5000 G (0.3 T to 0.5 T). it can. If the magnetic field strength is not more than the above range, the effect of suppressing convection of the silicon melt is not sufficient, and the shape of the solid-liquid interface cannot be made preferable, and the oxygen concentration cannot be lowered sufficiently, which is not preferable. Further, if the magnetic field strength is increased beyond the above range, convection is suppressed too much, and the high temperature silicon melt advances the deterioration of the inner surface of the quartz crucible, and the dislocation-free rate of the crystal is lowered.
In the present invention, the magnetic field center position and the melt surface position during crystal pulling are preferably −75 to +50 mm, more preferably 20 to 45 mm. Here, the magnetic field center position means a height position where the center of the magnetic field generating coil is located in a horizontal magnetic field, and −75 mm means 75 mm above the melt surface. ing.

The manufacturing method of the silicon single crystal wafer for IGBT of the present invention realizes an unprecedented level of oxygen concentration of 4 × 10 ¹⁷ atoms / cm ³ (oldASTM) or less in CZ silicon single crystal of φ8 inch or more We were able to. A silicon single crystal that is COP-free and has an oxygen concentration of 4 × 10 ¹⁷ atoms / cm ³ or less is a crystal located between the CZ crystal and the FZ crystal, which is a conventional crystal. By growing the COP-free crystal by the MCZ method, an oxide film breakdown voltage equivalent to the FZ crystal can be obtained. Further, by setting the oxygen concentration to 4 × 10 ¹⁷ atoms / cm ³ or less, it is possible to dispel the concern about the generation of oxygen donors in the heat treatment in the device manufacturing process, and furthermore, almost no oxygen-induced defects peculiar to CZ crystals are observed. In the pulling by the MCZ method, the convection of the silicon melt is suppressed, the amount of dissolution of the quartz crucible is reduced, and the impurity concentration in the quartz crucible is reduced by using the synthetic quartz crucible, so that a CZ crystal having a quality closer to that of the FZ crystal can be grown. .
Here, the synthetic quartz crucible means that at least the inner surface in contact with the raw material melt is formed of the following synthetic quartz.

Synthetic quartz is a chemically synthesized and manufactured raw material, and synthetic quartz glass powder is amorphous. Since the raw material of synthetic quartz is gas or liquid, it can be easily purified, and synthetic quartz powder can have a higher purity than natural quartz powder. Synthetic quartz glass raw materials are derived from gaseous raw materials such as carbon tetrachloride and liquid raw materials such as silicon alkoxide. In synthetic quartz powder glass, all impurities can be made 0.1 ppm or less.
In the glass obtained by melting synthetic quartz glass powder, when the light transmittance is measured, the synthetic quartz glass is made of carbon tetrachloride, which is used for ultraviolet optical applications as a raw material, and transmits ultraviolet rays up to a wavelength of about 200 nm. It is considered that the characteristics are close to.
In a glass obtained by melting synthetic quartz glass powder, when a fluorescence spectrum obtained by excitation with ultraviolet rays having a wavelength of 245 nm is measured, a fluorescence peak like a melted product of natural quartz powder is not observed.

    Whether the glass material was natural quartz by measuring the concentration of impurities contained, measuring the amount of silanol, or measuring the light transmittance, or measuring the fluorescence spectrum obtained by excitation with ultraviolet light having a wavelength of 245 nm. It can be determined whether it was quartz.

  In addition, the MCZ method makes it easier to grow an 8-inch φ silicon single crystal than the FZ method, and the use of a quartz crucible makes it possible to increase the charge, thereby reducing the raw material cost compared to the FZ method. At the same time, the yield can be improved.

  In the present invention, in order to control the gas flow state on the surface of the silicon melt, the pressure in the furnace is 1333 Pa or more, preferably 4000 Pa to 26660 Pa. The upper limit of the pressure in the furnace is that when the pressure in the furnace increases, the gas flow rate on the melt of inert gas such as Ar decreases, so that it is difficult to exhaust the reactant gas such as SiO evaporated from the melt. As a result, the oxygen concentration in the crystal becomes higher, and SiO aggregates in the upper part of the melt in the furnace at about 1100 ° C. or at a temperature lower than this, thereby generating dust and dropping into the melt. In order to prevent the occurrence of dislocation, the upper limit of the pressure is defined in order to prevent these.

In the present invention, the pressure in the furnace is 10 torr (1.3 kPa) or more, preferably 30 to 200 torr (4.0 to 27 kPa), more preferably, in order to control the gas flow state on the surface of the silicon melt. 30 to 70 torr (4.0 to 9.3 kPa) is desirable. The upper limit of the pressure in the furnace is that when the pressure in the furnace increases, the gas flow rate on the melt of inert gas such as Ar decreases, so that it is difficult to exhaust the reactant gas such as SiO evaporated from the melt. As a result, the oxygen concentration in the crystal increases, and SiO aggregates in the upper part of the melt in the furnace at about 1100 ° C. or at a lower temperature, thereby generating dust and dropping into the melt. In order to prevent dislocations, the upper limit of the pressure was specified to prevent them.
In the present invention, the atmospheric gas flow rate supplied to the CZ furnace is set to 100 to 200 liters / min or more, the pressure in the CZ furnace is set to 6700 pa or less, and SiO evaporated from the melt surface is effectively discharged out of the apparatus. At the same time, foreign matter drifting on the surface of the melt can be driven to the crucible wall, and the oxygen concentration in the crystal can be prevented from increasing.

Further, according to the silicon single crystal wafer of the present invention, the variation in resistivity within the wafer surface is 5% or less, so that the quality of the IGBT can be stabilized.
By the way, the resistivity of a silicon single crystal wafer manufactured by the CZ method can be controlled by the amount of dopant contained in the silicon single crystal, but phosphorus often used as a dopant for an IGBT substrate has a small segregation coefficient, so that the silicon single crystal The concentration varies greatly over the length direction. Therefore, the range in which a wafer having a resistivity that meets the design specifications in one single crystal is obtained is narrow. Therefore, in the present invention, as described above, neutron irradiation, addition of an n-type dopant to the silicon melt, addition of a predetermined amount of p-type dopant having a segregation coefficient smaller than phosphorus and phosphorus, and various other means are employed. In any case, it is important to grow a single crystal using a synthetic quartz crucible with a low impurity concentration as a raw material and a low impurity elution. By using these means, the yield of the silicon single crystal can be improved.

For neutron irradiation, first, a silicon single crystal is grown without adding a dopant for adjusting the resistivity to the silicon melt, and irradiating this non-doped silicon single crystal with neutrons results in ³⁰ Si in the crystal. Phosphorus can be doped by utilizing the phenomenon that is converted to ³¹ P. ^{Since 30} Si is uniformly contained in a single crystal at a concentration of about 3%, this neutron irradiation is a method in which phosphorus can be doped most uniformly in both the radial and axial directions of the crystal.
The resistivity can also be controlled by adding an n-type dopant to the silicon melt. At this time, it is desirable to apply a so-called DLCZ method (Double Layered Czochralski). The DLCZ method is a method for suppressing a change in concentration in the crystal axis direction of a dopant having a small segregation coefficient such as phosphorus. This method is disclosed in, for example, Japanese Patent Laid-Open No. 5-43384. In the CZ method, all the polycrystalline silicon is once dissolved in a crucible to form a silicon melt, phosphorus is added, and the temperature at the bottom of the crucible is lowered. Dopant concentration incorporated into the single crystal by solidifying the silicon melt upward from the bottom to form a silicon solidified layer and growing the crystal while gradually dissolving the silicon solidified layer from the top toward the bottom Is a method of keeping the constant almost constant.
In the present invention, the change in resistivity in the crystal axis direction of the silicon single crystal can also be suppressed by adopting the DLCZ method.

Moreover, the resistivity change in the crystal axis direction of the silicon single crystal can also be suppressed by adding a predetermined amount of phosphorus and a p-type dopant having a segregation coefficient smaller than that of phosphorus. This is called a so-called double doping method and is disclosed in, for example, Japanese Patent Application Laid-Open No. 2002-128591, and is a method for suppressing a change in resistivity in the axial direction of a crystal doped with a dopant having a small segregation coefficient such as phosphorus. . The phosphorus concentration change is compensated for by doping p-type dopant (for example, Al, Ga, In) having a segregation coefficient smaller than that of phosphorus as a counter dopant. FIG. 2 shows a change in resistivity in the crystal axis direction when only phosphorus is doped and when phosphorus and aluminum are simultaneously doped. When the resistivity specification of the wafer is 50 ± 5 Ω · cm, the yield is improved about three times by simultaneously doping with phosphorus and aluminum. The yield is the highest when the concentration ratio of aluminum to phosphorus at the upper end of the single crystal is about 50%. In the present invention, phosphorous and a p-type dopant having a segregation coefficient smaller than that of phosphorous are contained in concentrations of 1 × 10 ¹³ atoms / cm ³ or more and 1 × 10 ¹⁵ atoms / cm ³ or less, respectively. The change in resistivity in the crystal axis direction can be suppressed.

Furthermore, in the present invention, a so-called CCZ method can also be applied. This method is disclosed in, for example, Japanese Patent Application Laid-Open No. 61-36197, and by adding polycrystalline silicon containing no dopant to a silicon melt containing phosphorus during single crystal growth, In this method, the concentration of the incorporated dopant is kept almost constant.
Furthermore, in the case of single crystal growth in which a dopant is added to a silicon melt as in the DLCZ method or CCZ method, the crystal rotation speed during crystal growth is rotated fast in order to suppress resistivity variation in the wafer surface. In the case of growing a single crystal having a diameter of 200 mm or less, it is desirable to rotate the crystal rotation speed in the range of 15 to 30 rpm, and in the case of a diameter of 300 mm or more, in the range of 8 to 15 rpm. Normally, when the crystal rotation speed is increased, the pulling speed margin width for obtaining a grow-in defect-free crystal is narrowed, and it becomes difficult to grow a single crystal itself. By growing the silicon single crystal in the contained gas atmosphere, a sufficient pulling speed margin for obtaining a grow-in defect free crystal can be secured.

Next, 5 × 10 ¹² atoms / cm ³ or more and 5 × 10 ¹⁵ atoms / cm ³ or less, or 1 × 10 ¹³ atoms / cm ³ or more and 2 × 10 ¹⁵ atoms / cm ³ or less are more preferable. Is doped with nitrogen of 5 × 10 ¹³ atoms / cm ³ or more and 9 × 10 ¹⁴ atoms / cm ³ or less, thereby facilitating elimination of COP defects and dislocation clusters. If the doping amount of nitrogen is less than the above range, the controllable range of V / G is narrow, and there is a possibility that COP defects and dislocation clusters will not be completely eliminated. This is not preferable because crystals cannot be grown.
Further, it is preferable that the silicon single crystal is 1 × 10 ¹³ atoms / cm ³ or more and 5 × 10 ¹⁵ atoms / cm ³ or less, or 1 × 10 ¹⁴ atoms / cm ³ or more and 5 × 10 ¹⁵ atoms / cm ³ or less, more preferably COP by doping nitrogen of 1 × 10 ¹⁴ atoms / cm ³ or more and 9 × 10 ¹⁴ atoms / cm ³ or less, or 1 × 10 ¹⁴ atoms / cm ³ or more and 5 × 10 ¹⁴ atoms / cm ³ or less. Elimination of defects and dislocation clusters is facilitated. If the doping amount of nitrogen is less than the above range, the controllable range of V / G is narrow, and there is a possibility that COP defects and dislocation clusters will not be completely eliminated. This is not preferable because crystals cannot be grown. In addition, by making it above the above range, the effect of promoting oxygen precipitation by doping nitrogen is clear, and if it is below the above range, it may hinder single crystallization at the time of single crystal pulling, It does not cause instability of continuous operation.

Moreover, according to the silicon single crystal wafer of the present invention, the pass rate of TZDB is 90% or more, and the concentration of oxygen donors generated when heat treatment is performed at 450 ° C. for 1 hour is 9.8 × 10 ¹² pieces. / cm ³ or less, and a density of BMD that occurs when performing a two-stage heat treatment of 16 hours at 4 hours and 1000 ° C. at 800 ° C. is 5 × 10 ⁷ / cm ³ or less, were two-stage heat treatment Since the recombination lifetime in this case is 100 μsec or more, the characteristics required for a silicon single crystal wafer for IGBT can be satisfied.

The recombination lifetime is deteriorated by interstitial oxygen contained in the silicon single crystal being precipitated as SiO ₂ through a device formation process. According to the wafer of the present invention, since the interstitial oxygen concentration is 8.5 × 10 ¹⁷ atoms / cm ³ or less as described above, the recombination lifetime can be 100 μsec or more.

The method for producing a silicon single crystal wafer for IGBT of the present invention is a method for producing a silicon single crystal wafer for IGBT obtained by growing a silicon single crystal by the Czochralski method,
A pulling step of growing a single crystal having a growth rate of the silicon single crystal at a speed at which a grown-in defect-free silicon single crystal can be pulled and an interstitial oxygen concentration of 8.5 × 10 ¹⁷ atoms / cm ³ or less;
A hole injection step of performing RTA treatment of a wafer sliced from the single crystal at 1175 ° C. or higher;
After the hole injecting step, heat treatment is performed at a temperature range of 1000 ° C. to 1100 ° C. for a processing time of 1 to 16 hours to form an IGBT device having a thickness direction dimension of 100 to 200 μm on the surface side of the entire wafer surface. A hole-control heat treatment step for forming a device region and a gettering region to be removed after device formation on the back side of the device region;
In a wafer subjected to RTA treatment in an atmosphere containing nitrogen or an atmosphere containing a nitrogen-containing gas such as ammonia as a vacancy injecting step, the initial temperature of the device process for IGBT is 600 ° C. to 900 ° C. Even when the low-temperature heat treatment is performed for a long time, vacancies existing on the wafer surface layer side are not stabilized. As a result, a BMD (oxygen precipitate) of 20 nm or more is formed at a high density of 5 × 10 ³ pieces / cm ³ or more in a device region having a thickness of 100 to 200 μm or 150 μm from the surface layer in a subsequent heat treatment step in the device process. Thus, it is possible to prevent the deterioration of the IGBT characteristics.
Here, it is preferable that the temperature increase rate and the temperature decrease rate of the heat treatment in the hole control heat treatment step are 3 to 50 ° C./min and 3 to 20 ° C./min, respectively. Therefore, a lamp annealing furnace can be used, but can be processed by a horizontal furnace.
Here, if the temperature increase / decrease rate is less than 3 ° C., nucleation occurs and density control is difficult. On the other hand, if the rate of temperature rise exceeds 50 ° C./min, a large thermal stress may be applied to the wafer and it may break. On the other hand, if the temperature lowering rate exceeds 20 ° C./min, holes are injected into the wafer by the hole control heat treatment, which makes it difficult to control the density.

That is, in the present invention, the vacancies near the surface layer injected by the vacancy injection RTA treatment are subjected to a heat treatment at a temperature of 1000 ° C. to 1100 ° C. for about 1 to 16 hours after the RTA treatment, for example, Even after going through the IGBT device process having a heat treatment condition of 4 hr + 1000 ° C. for 16 hr, oxygen precipitation does not occur in the device region of about 150 μm from the wafer outermost surface, and the oxygen precipitate density is 5 × 10 ³ pieces / cm ³ or less. It is possible to provide an IGBT silicon single crystal wafer in which oxygen precipitation occurs at a deeper position and the density of oxygen precipitates is 5 × 10 ⁴ pieces / cm ³ or more and 1 × 10 ⁷ pieces / cm ³ or less.

  If an IGBT is manufactured using such a wafer through an IGBT device process, after the device is formed, the portion on the back side deeper than the device region is removed and the thickness is reduced before the thinning step (back grinding step). The device region (device active region) can be protected from metal contamination by the gettering (IG) effect of BMD included in a deep position of 150 μm or more from the outermost surface. Since the portion of the deep region including the BMD is removed by the back grinding, the completed IGBT element does not include the BMD, and hence the IGBT characteristics are not deteriorated by the BMD. Moreover, since the silicon single crystal wafer for IGBT according to the present invention has IG capability in the wafer from the beginning in the device process, the manufacturing cost can be reduced by omitting the EG processing such as polysilicon film formation processing (PBS) on the back surface. Is also possible.

In the hole control heat treatment process of the present invention, the relationship between the treatment time and temperature is shown in FIG. In this case, it is preferable to set the Z region above the straight line connecting the point at 700 ° C. and 8 (hr) time and the point at 1000 ° C. for 1 hour. That is, the relationship between the processing time t (hr) and the processing temperature d (° C.) is
t ≧ −7d / 300 + 73/3
It becomes.
In FIG. 8, in the Y region below the Z region and above the straight line connecting the point at 700 ° C. for 3 hours and the point at 1000 ° C. for 1 hour, BMD is also deposited in the device region, which is not preferable. In FIG. 8, the X region below the Y region is not preferable because BMD is deposited only in the device region.

The method for producing a silicon single crystal wafer for IGBT of the present invention is a method for producing a silicon single crystal wafer for IGBT obtained by growing a silicon single crystal by the Czochralski method, and in an atmosphere gas in a CZ furnace. Introducing a hydrogen atom-containing substance with a hydrogen gas equivalent partial pressure in the range of 40 Pa or more and 400 Pa or less, and the silicon single crystal pulling rate is such that the grown-in defect-free silicon single crystal can be pulled at an interstitial oxygen concentration. Is grown to a single crystal of 8.5 × 10 ¹⁷ atoms / cm ³ or less, and the silicon single crystal after pulling can be irradiated with neutrons to be doped with phosphorus.
Moreover, the manufacturing method of the silicon single crystal wafer for IGBT of this invention is a manufacturing method of the silicon single crystal wafer for IGBT obtained by growing a silicon single crystal by the Czochralski method, Comprising: An n-type dopant is added to a silicon melt. A hydrogen atom-containing substance having a hydrogen gas equivalent partial pressure in the range of 40 Pa or more and 400 Pa or less is introduced into the atmosphere gas in the CZ furnace, and the pulling rate of the silicon single crystal is reduced to a grown-in defect-free silicon single crystal Can grow a single crystal having an interstitial oxygen concentration of 8.5 × 10 ¹⁷ atoms / cm ³ or less.
The method for producing a silicon single crystal wafer for IGBT of the present invention is a method for producing a silicon single crystal wafer for IGBT obtained by growing a silicon single crystal by the Czochralski method, wherein phosphorus is added to the silicon melt. 2.9 × 10 ¹³ atoms / cm ³ or more and 2.9 × 10 ¹⁵ atoms / cm ³ or less, a p-type dopant having a segregation coefficient smaller than that of phosphorus, and the concentration in the crystal is 1 × 10 according to the segregation coefficient Hydrogen atoms containing material that is added in the range of ¹³ atoms / cm ³ or more and 1 × 10 ¹⁵ atoms / cm ³ or less and that is in the range of 40 Pa or more and 400 Pa or less in terms of hydrogen gas partial pressure is introduced into the atmosphere gas in the CZ furnace. The rate of pulling of the silicon single crystal is such that the grown-in defect-free silicon single crystal can be pulled, and the interstitial oxygen Degrees can be grown to 8.5 × ¹⁰ 17 atoms / cm ³ or less of a single crystal.
Furthermore, in the manufacturing method of the silicon single crystal wafer for IGBT of the present invention, nitrogen is 5 × 10 ¹² atoms / cm ³ or more and 5 × 10 ¹⁵ atoms / cm ³ or less with respect to the silicon single crystal by the Czochralski method. It is preferable to add at a concentration.

Here, the hydrogen-containing substance is a substance containing hydrogen atoms in its molecule, and is a gaseous substance that generates hydrogen gas by being thermally decomposed when dissolved in the silicon melt. This hydrogen-containing substance includes hydrogen gas itself. By mixing this hydrogen-containing substance with an inert gas and introducing it into the atmosphere at the time of forming the necking portion, the hydrogen concentration in the silicon melt can be improved. Specific examples of the hydrogen-containing substance include inorganic compounds containing hydrogen atoms such as hydrogen gas, H ₂ O, and HCl, hydrocarbon atoms such as silane gas, CH ₄ , and C ₂ H _2, and hydrogen atoms such as alcohol and carboxylic acid. Examples of the organic compound include, but it is particularly preferable to use hydrogen gas. In addition, as the atmospheric gas in the CZ furnace, inexpensive argon gas is preferable, and various rare gases such as helium, neon, krypton, and xenon, or a mixed gas thereof can be used.

Moreover, in this invention, the density | concentration of the hydrogen containing substance in hydrogen containing atmosphere is made into the range of 40 Pa or more and 400 Pa or less in hydrogen gas conversion partial pressure. Here, the hydrogen gas equivalent partial pressure is because the amount of hydrogen atoms obtained by thermal decomposition of the hydrogen-containing material depends on the number of hydrogen atoms originally contained in the hydrogen-containing material. . For example, 1 mole of H ₂ O contains 1 mole of H _2, but 1 mole of HCl contains only 0.5 mole of H ₂ . Therefore, in the present invention, the hydrogen-containing substance is used so that an atmosphere equivalent to this reference atmosphere can be obtained on the basis of a hydrogen-containing atmosphere in which hydrogen gas is introduced into the inert gas at a partial pressure of 40 to 400 Pa. It is desirable to determine the concentration of hydrogen, and the preferable pressure of the hydrogen-containing substance at this time is defined as a partial pressure in terms of hydrogen gas.
That is, in the present invention, it is assumed that a hydrogen-containing substance is dissolved in a silicon melt and is thermally decomposed in a high-temperature silicon melt to be converted into hydrogen atoms. What is necessary is just to adjust the addition amount of a hydrogen-containing substance so that a pressure may be in the range of 40-400 Pa.

According to the above method for manufacturing a silicon single crystal wafer for IGBT, by introducing a hydrogen atom-containing substance having a hydrogen gas equivalent partial pressure of 40 Pa or more and 400 Pa or less, a grown-in defect-free silicon single crystal is obtained. The allowable range of the pullable speed can be widened, whereby a wafer from which COP defects and dislocation clusters are eliminated in the entire crystal diameter direction can be easily manufactured. Further, the non-doped silicon single crystal after the pulling is irradiated with neutrons to dope phosphorus, or an n-type dopant such as phosphorus is added to the silicon melt, thereby reducing the variation in resistivity in the plane of the wafer. % Or less. The reduction in resistivity variation can also be achieved by adding phosphorus and a p-type dopant having a smaller segregation coefficient than phosphorus to the silicon melt.
Moreover, by adding nitrogen to the silicon melt, the allowable range of the speed at which the grown-in defect-free silicon single crystal can be pulled can be further increased, and the elimination of COP defects and dislocation clusters in the wafer is facilitated. .

  According to the present invention, the pulling speed margin can be increased, EG processing is not required, the DZ layer has a sufficient thickness as an IGBT wafer, has IG capability, and has a resistivity. It is possible to provide a method for manufacturing a silicon single crystal wafer for IGBT and a silicon single crystal wafer for IGBT, which can manufacture a wafer with small variations.

FIG. 1 is a graph showing the relationship between interstitial oxygen concentration and oxygen donor concentration after heat treatment. FIG. 2 is a graph showing the relationship between the solidification rate and the resistivity. FIG. 3 is a schematic vertical cross-sectional view of a CZ furnace used in carrying out the method for producing a silicon single crystal wafer according to the embodiment of the present invention. FIG. 4 is a schematic cross-sectional view showing the peripheral portion of the silicon single crystal wafer according to the embodiment of the present invention. FIG. 5A is a schematic cross-sectional view showing an IGBT. FIG. 5B is a schematic cross-sectional view showing the IGBT. FIG. 5C is a schematic cross-sectional view showing the IGBT. FIG. 6 is a flowchart showing the manufacturing method and IGBT manufacturing process of the present invention. FIG. 7A is a process diagram in the production method of the present invention. FIG. 7B is a process diagram in the production method of the present invention. FIG. 7C is a process diagram in the production method of the present invention. FIG. 7D is a process diagram in the manufacturing method of the present invention. FIG. 8 is a graph showing the relationship between the treatment time and the treatment temperature in the pore control heat treatment step. FIG. 9 is a graph showing the relationship between the wafer depth and the BMD density in the example of the present invention. FIG. 10 is a graph showing the relationship among the quartz crucible rotation speed, crystal rotation speed, and interstitial oxygen concentration.

Explanation of symbols

3 ... Silicon melt 6 ... Silicon single crystal T ... Seed crystal

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Configuration of CZ furnace)
FIG. 3 is a longitudinal sectional view of a CZ furnace suitable for carrying out the method for manufacturing a silicon single crystal wafer for IGBT in the embodiment of the present invention.
The CZ furnace shown in FIG. 3 includes a crucible 1 disposed in the center of the chamber, a heater 2 disposed outside the crucible 1, and a magnetic field supply device 9 disposed outside the heater 2. . The crucible 1 has a double structure in which a quartz crucible 1a containing a silicon melt 3 inside is held by an outer graphite crucible 1b, and is rotated and moved up and down by a support shaft 1c called a pedestal.
A cylindrical heat shield 7 is provided above the crucible 1. The heat shield 7 has a structure in which an outer shell is made of graphite and the inside thereof is filled with graphite felt. The inner surface of the heat shield 7 is a tapered surface whose inner diameter gradually decreases from the upper end to the lower end. The upper outer surface of the heat shield 7 is a tapered surface corresponding to the inner surface, and the lower outer surface is formed in a substantially straight surface so as to gradually increase the thickness of the heat shield 7 downward.
Then, the silicon single crystal 6 can be formed by immersing the seed crystal T attached to the seed chuck 5 in the silicon melt 3 and pulling up the seed crystal T while rotating the crucible 1 and the pulling shaft 4. .

The heat shield 7 blocks the radiation heat from the heater 2 and the silicon melt 3 surface to the side surface of the silicon single crystal 6, surrounds the side surface of the growing silicon single crystal 6, and the silicon melt 3. It surrounds the surface. An example of the specification of the heat shield 7 is as follows.
The radial width W is, for example, 50 mm, the inclination θ of the inner surface of the inverted truncated cone surface with respect to the vertical direction is, for example, 21 °, and the height H1 of the lower end of the heat shield 7 from the melt surface is, for example, 60 mm.

  The magnetic field supplied from the magnetic field supply device 9 may be a horizontal magnetic field or a cusp magnetic field. For example, the strength of the horizontal magnetic field is 2000 to 4000 G (0.2 T to 0.4 T), more preferably 2500. -3500G (0.25T-0.35T), and the magnetic field center height is set to be within a range of -150 to +100 mm, more preferably -75 to +50 mm with respect to the melt surface.

(Manufacturing method of silicon single crystal wafer for IGBT)
Next, a method for manufacturing a silicon single crystal wafer for IGBT using the CZ furnace shown in FIG. 3 will be described.

FIG. 6 is a flowchart showing a method of manufacturing a silicon single crystal wafer for IGBT and a manufacturing process of IGBT, and FIGS. 7A to 7D are a method of manufacturing a silicon single crystal wafer for IGBT and manufacturing of IGBT. It is process drawing which shows a process.
In this embodiment, as shown in FIG. 6, as a method for manufacturing a silicon single crystal wafer for IGBT, a pulling step S01 for pulling a single crystal by a CZ method, and slicing, etching, grinding, and slicing the wafer from the pulled single crystal. A slicing step S02 in which a wafer is formed by performing surface treatment such as polishing, a hole injection step S03 in which the wafer W is RTA processed at 1175 ° C. or higher, a temperature range of 1000 ° C. to 1100 ° C. after the hole injection step S03, And a hole control heat treatment step S04 in which a device region and a gettering region are formed on the wafer by heat treatment at a treatment time of 1 to 16 hours. Furthermore, as the IGBT manufacturing process, the IGBT device process SD1, the back grinding process SD2, and the device finishing process SD3 complete the IGBT.

First, as a pulling step S01 shown in FIG. 6, for example, 100 kg of high-purity silicon polycrystal is charged into the crucible 1, and a silicon wafer having a CVD film made of, for example, silicon nitride is introduced as a nitrogen source. It is preferable to adjust the nitrogen concentration in the silicon melt so that the nitrogen concentration in the silicon crystal is 5 × 10 ¹² atoms / cm ³ or more and 5 × 10 ¹⁵ atoms / cm ³ or less.

Next, the inside of the CZ furnace is a hydrogen-containing atmosphere composed of a mixed gas of a hydrogen-containing substance and an inert gas, the atmosphere pressure is 1333 Pa to 13330 Pa (10 to 100 torr), and the concentration of the hydrogen-containing substance in the atmosphere gas is hydrogen gas. It adjusts so that it may become about 40-400 Pa by conversion partial pressure. When hydrogen gas is selected as the hydrogen-containing substance, the hydrogen gas partial pressure may be set to 40 to 400 Pa. The concentration of hydrogen gas at this time is in the range of 0.3% to 31%.
In addition, it can also be set as the atmosphere only of the inert gas which does not contain hydrogen gas.

  If the hydrogen gas equivalent partial pressure of the hydrogen-containing material is less than 40 Pa, the allowable range of the pulling rate is reduced, and generation of COP defects and dislocation clusters cannot be suppressed. Further, the higher the hydrogen gas equivalent concentration (hydrogen concentration) of the hydrogen-containing substance, the greater the effect of suppressing dislocation generation. However, if the hydrogen gas equivalent partial pressure exceeds 400 Pa, the risk of explosion or the like increases when an oxygen leak occurs in the CZ furnace, which is not preferable for safety. The hydrogen gas equivalent partial pressure of the hydrogen-containing substance is more preferably in the range of 40 Pa to 250 Pa, and particularly preferably the hydrogen gas equivalent partial pressure is in the range of 40 Pa to 135 Pa.

Next, a horizontal magnetic field of, for example, 3000 G (0.3 T) is supplied from the magnetic field supply device 9 so that the magnetic field center height is −75 to +50 mm with respect to the melt liquid surface, and silicon polycrystalline is formed by the heater 2. Heat to make silicon melt 3.
Next, the seed crystal T attached to the seed chuck 5 is immersed in the silicon melt 3, and the crystal is pulled up while rotating the crucible 1 and the pulling shaft 4. As the pulling conditions in this case, the growth rate of the single crystal is V (mm / min), and the ratio V / G (mm) when the temperature gradient G (° C./mm) is 1350 ° C. from the melting point during single crystal growth. ² / min · ° C.) is controlled to about 0.22 to 0.15, and V is controlled to 0.42 to 0.33 mm / min, which is a speed at which the grown-in defect-free silicon single crystal can be pulled up. The following conditions can be exemplified. As other conditions, the rotation speed of the quartz crucible is 5 to 0.2 rpm, the rotation speed of the single crystal is 20 to 10 rpm, the pressure of the argon atmosphere is 1333 to 26660 Pa or 30 Torr, and the magnetic field strength is 3000 to 3000. A condition such as 5000 Gauss can be exemplified. In particular, by setting the rotation speed of the quartz crucible to 5 rpm or less, diffusion of oxygen atoms contained in the quartz crucible into the silicon melt can be prevented, and the interstitial oxygen concentration in the silicon single crystal can be reduced. it can. Moreover, the variation in resistivity within the silicon single crystal can be reduced by setting the rotation speed of the single crystal to 5 rpm or more.
By setting the above pulling conditions, the interstitial oxygen concentration in the silicon single crystal can be 8.5 × 10 ¹⁷ atoms / cm ³ or less, more preferably 4 × 10 ¹⁷ atoms / cm ³ or less. As a result, generation of oxygen donors in the IGBT manufacturing process can be prevented. If the interstitial oxygen concentration exceeds the above range, oxygen precipitates and oxygen donors are generated in the IGBT manufacturing process, and the characteristics of the IGBT are changed.

Next, a neutron beam is irradiated to the formed single crystal silicon to which a dopant for adjusting the resistivity is not added. By this neutron beam irradiation, a part of silicon atoms is converted into phosphorus, whereby the single crystal silicon can be uniformly doped with phosphorus, and single crystal silicon with a uniform resistivity can be obtained. The irradiation conditions of the neutron beam may be, for example, irradiation for about 80 hours at a crystal rotation of about 2 rpm at a position where the neutron beam flux is 3.0 × 10 ¹² pieces / cm ² / s ⁻¹ . The silicon ingot thus irradiated with the neutron beam has a resistivity of about 48 Ω · cm to 52 Ω · cm.

  Instead of neutron irradiation, n-type (P, As, Sb, etc.) dopant may be added to the silicon melt in advance. However, since the segregation coefficient is small, the length direction of the silicon single crystal The resistivity changes greatly. In order to prevent such a change in n-type dopant concentration, for example, the above-described DLCZ method, double doping method, or CCZ method may be employed.

Next, as a slicing step S02 shown in FIG. 6, a wafer is cut out from the pulled single crystal silicon, and lapping, etching, or the like is performed as necessary.
When lapping, in order to prevent the wafer from cracking, it is preferable to form a front side chamfered portion at the peripheral portion of the front surface of the wafer and a back side chamfered portion at the peripheral portion of the rear surface of the wafer. FIG. 4 shows a cross section of the peripheral edge of the wafer after completion of the wafer processing.

As shown in FIG. 4, the front surface 22 of the wafer is provided with a main surface 23 that is a flat surface and a surface chamfered portion 24 formed at the peripheral edge. Further, the back surface 26 is provided with a main surface 27 which is a flat surface and a back surface side chamfered portion 28 formed at the peripheral edge. The front side chamfered portion 24 has a width A1 in the direction from the peripheral edge 29 inward in the wafer radial direction, and a width A2 in the direction from the peripheral edge 29 in the backside chamfered portion 28 inward in the wafer radial direction. It is narrowed. The width A1 of the surface chamfer 24 is preferably in the range of 50 μm to 200 μm. Further, the width A2 of the back side chamfer 28 is preferably in the range of 200 μm to 300 μm.
Further, the front side chamfer 24 has the first inclined surface 11 that is inclined with respect to the main surface 23 of the front surface 22, and the back side chamfered portion 28 is the first inclined surface 11 that is inclined with respect to the main surface 27 of the rear surface 26. Two inclined surfaces 12 are provided. The inclination angle θ1 of the first inclined surface 11 is preferably in the range of 10 ° to 50 °, the inclination angle θ2 of the second inclined surface 12 is preferably in the range of 10 ° to 30 °, and θ1 ≦ θ2 is satisfied. preferable.
A first curved surface 13 is provided between the first inclined surface 11 and the peripheral edge 29 to connect them. A second curved surface 14 is provided between the second inclined surface 12 and the peripheral edge 29 to connect them. The range of the radius of curvature R1 of the first curved surface 13 is preferably in the range of 80 μm to 250 μm, and the range of the radius of curvature R2 of the second curved surface 14 is preferably in the range of 100 μm to 300 μm.

As described above, the RTA process is performed as the hole injection step S03 on the wafer W0 after the slicing step S02 shown in FIG. 7A.
In this vacancy injection step S03, 1150 to 1250 ° C., or 1100 to 1200 ° C., more preferably 1170 to 1180 ° C., 5 to 60 seconds, and both the temperature increase / decrease rate are 50 to 100 ° C./min, and Nitrogen or ammonia is used in a single wafer annealing furnace such as lamp annealing as a gas atmosphere having a hole injection effect. Here, when vacancy injection is performed by nitriding the surface in a gas atmosphere having a low decomposition temperature such as ammonia at a low temperature of about 1050 to 1150 ° C., only injection of vacancies from the wafer surface by surface nitridation is performed. Predominate. This is because when a nitride film is formed, silicon atoms are taken away from the crystal lattice of the silicon single crystal on the wafer surface and a silicon nitride film is formed outside the single crystal. Only the holes are formed, which expands from the wafer surface toward the inside, and only the outermost (surface side) vacancies are reduced during cooling, and vacancy concentration peaks are formed near the front and back surfaces in the wafer thickness direction. It is considered that the vacancy concentration distribution of the mold is realized. In this low temperature range, surface nitridation hardly occurs in a nitrogen gas atmosphere, so a gas atmosphere such as ammonia having a decomposition temperature lower than that of nitrogen is required.

On the other hand, in the N ₂ atmosphere high-temperature treatment at about 1150 to 1250 ° C. and about 1170 to 1180 ° C. as in the present invention, not only the vacancy injection from the wafer surface by nitriding but also the bulk region (wafer In the central portion in the thickness direction, vacancies are formed by the generation of Frenkel pairs between vacancies and interstitial silicon. In this temperature range, not only the N ₂ atmosphere but also an atmosphere such as ammonia can be used.
In the formation of holes due to the generation of Frenkel pairs, the diffusion coefficient of interstitial silicon is faster than the diffusion coefficient of holes, so only the interstitial silicon diffuses to the wafer surface side among the Frenkel pairs generated throughout the wafer thickness direction. As a result, only vacancies are formed in the bulk region. The formation of vacancies due to the generation of the Frenkel pair was performed by RTA treatment in the state where vacancies were formed when RTA treatment was performed without performing surface nitridation, or when an oxide film having a thickness greater than that of a natural oxide film was present on the surface. This is recognized as the formation of holes at the time.
Therefore, in the above high temperature treatment of about 1150 to 1250 ° C. and 1170 to 1180 ° C., both vacancy injection from the surface by treatment at a low temperature and vacancy formation by Frenkel pairs occur in the bulk region. As a result, it is possible to realize a state in which the vacancy concentration in the bulk region at the central portion in the wafer thickness direction is uniform in the wafer thickness direction and in-plane direction and higher than in the low temperature treatment.

After the hole injection step S03, a hole control heat treatment step S04 is performed.
In this hole control heat treatment step S04, the heat treatment is performed at a temperature range of 1000 ° C. to 1100 ° C. and a treatment time of 1 to 16 hours, satisfying the relationship between the treatment temperature to be the Z region shown in FIG. As shown in FIG. 7B, a device region W1 where an IGBT device having a thickness direction dimension of 100 to 200 μm is formed on the front surface WS1 side of the entire surface of the wafer W and the device region W1 is removed after the device is formed on the back surface side. Gettering regions W2 and W3 are formed.
The gettering regions W2 and W3 are substantially the same as the device region W1 on the wafer W rear surface WS2 side, and the center region W2 in which the vacancy concentration is distributed at a high concentration in a substantially uniform state in the thickness direction at the center in the wafer thickness direction. And the rear surface side region W3.
The device region W1 has a thickness of about 100 to 200 μm, preferably about 140 to 160 μm, more preferably about 150 μm from the surface WS1. The heat treatment of the hole control heat treatment step S04 causes the holes to be diffused outward and interstitial silicon. It is reduced to such an extent that it can be considered that it has almost disappeared. For this reason, it is in the state which can suppress the oxygen precipitation by the heat processing in a post process.
Among the gettering regions, in the central region W2, the high concentration state of the vacancies is maintained, and oxygen precipitation is sufficiently possible in the heat treatment in the subsequent process.
The back side region W3 is in the same state as the device region.

  Thus, the silicon single crystal wafer for IGBT of this embodiment can be manufactured.

According to the manufacturing method described above, by introducing a hydrogen atom-containing substance having a hydrogen gas equivalent partial pressure in the range of 40 Pa or more and 400 Pa or less, an allowable width of a speed at which a grown-in defect-free silicon single crystal can be pulled is increased. Thus, a wafer from which COP defects and dislocation clusters are eliminated in the entire crystal diameter direction can be easily manufactured. Also, the silicon single crystal after pulling is irradiated with neutrons to dope phosphorus, or by adding an n-type dopant such as phosphorus to the silicon melt, the variation in resistivity within the wafer surface is 5% or less. Can be. The reduction in resistivity variation can also be achieved by adding phosphorus and a p-type dopant having a smaller segregation coefficient than phosphorus to the silicon melt.
Moreover, by adding nitrogen to the silicon melt, the allowable range of the speed at which the grown-in defect-free silicon single crystal can be pulled can be further increased, and the elimination of COP defects and dislocation clusters in the wafer is facilitated. .

(Silicon single crystal wafer for IGBT)
The silicon single crystal wafer manufactured as described above has COP defects and dislocation clusters eliminated in the entire crystal diameter direction, and the interstitial oxygen concentration is 8.5 × 10 ¹⁷ atoms / cm ³ or less. In-plane resistivity variation is 5% or less. The resistivity itself is about 48 Ω · cm to 52 Ω · cm. Further, the silicon single crystal wafer is doped with nitrogen of 5 × 10 ¹² atoms / cm ³ or more and 5 × 10 ¹⁵ atoms / cm ³ or less.
Furthermore, in the silicon single crystal wafer of this embodiment, the pass rate of TZDB at a breakdown electric field of 8 MV / cm is 90% or more, and the concentration of oxygen donor that precipitates when heat treatment is performed at 450 ° C. for 1 hour is 9 8 × 10 ¹² pieces / cm ⁻³ or less, and the density of BMD generated when two-stage heat treatment is performed at 800 ° C. for 4 hours and 1000 ° C. for 16 hours is 5 × 10 ⁷ pieces / cm ⁻³ or less. Yes, the recombination lifetime when the two-stage heat treatment is performed is 100 μsec or more.
Furthermore, in the silicon single crystal wafer of this embodiment, the LPD density of 0.1 μm or more on the wafer surface is 0.1 piece / cm ² or less, and the light etching defect density is 1 × 10 ³ pieces / cm ² or less. It has become. Furthermore, in the silicon single crystal wafer of this embodiment, a polycrystalline silicon layer having a thickness of 50 nm or more and 2000 nm or less is formed on the back surface side, and a surface chamfered portion is formed at the peripheral edge of the wafer surface. A back side chamfer may be formed on the peripheral edge of the back side.

(Manufacturing process for IGBT)
As a manufacturing process for the IGBT, as shown in FIG. 7C, an IGBT device process SD1 having the heat treatment conditions as shown in Table 3 for the IGBT silicon single crystal wafer W of the present embodiment, The device D is formed in the region W1.
In the figure, device D is schematically shown.

After the device formation, as shown in FIG. 7D, the back grinding process SD2 thins the back side of the wafer W by a technique such as polishing to remove the back grinding regions W2 and W3.
Thereafter, the IGBT element shown in FIG. 5 is completed by a device finishing process SD3 such as cutting into chips and back surface processing.

In the silicon single crystal wafer W for IGBT of this embodiment, the hole distribution in the wafer W is controlled by the hole control heat treatment step S04, and has the device region W1 and the back grind regions W2, W3. Therefore, even after the device process SD1 for IGBT, oxygen precipitation does not occur in the device region W1 that is 100 to 200 μm, preferably 140 to 160 μm, more preferably about 150 μm from the surface WS1, and BMD (oxygen precipitation of 20 nm or more) A) The density is not formed at a high density of 5 × 10 ³ pieces / cm ³ or more, the BMD density can be 1 × 10 ³ pieces / cm ³ or less, and the IGBT characteristics are not deteriorated. .
At the same time, in the back grind region W2 adjacent to the device region W1 at a depth of 150 μm or more or 200 μm or more from the surface WS1, oxygen deposition occurs after the IGBT device process SD1, and the BMD (oxygen precipitate) density is increased. 5 × 10 ⁴ / cm ³ or more and 1 × 10 ⁷ / cm ³ or less, and the device region W1 can be protected from metal contamination during the IGBT device process SD1 by the gettering (IG) effect of BMD. it can.
In addition, since the back-grind regions W2 and W3 are removed by the back-grinding process SD2, the completed IGBT element does not include BMD in the entire thickness direction (emitter-collector direction). Further, in the present embodiment, since the back-grind region has gettering (IG) capability from the initial stage in the device process, the polysilicon film forming process on the wafer back surface WS2 is performed in this embodiment. The manufacturing cost can be reduced by omitting the EG process.

According to the silicon single crystal wafer for IGBT of this embodiment, COP defects and dislocation clusters are eliminated in the entire crystal diameter direction, and therefore, when the gate oxide film is formed on the wafer surface in the IGBT manufacturing process, COP defects are not generated. The gate oxide film is not taken in, and the GOI is not deteriorated.
Further, since the OSF region is excluded and there is no region where the density of OSF is 10 / cm ² or more, COP defects are taken into the gate oxide film when the gate oxide film is formed on the wafer surface in the IGBT manufacturing process. The GOI is not deteriorated. In addition, leakage current in the integrated circuit can be prevented. Furthermore, the yield rate can be 90% or higher.

Furthermore, since COP defects and dislocation clusters are eliminated in the entire crystal diameter direction, the wafer can be suitably used as an IGBT wafer, which is an element that uses the wafer in the vertical direction. That is, since COP defects and dislocation clusters are eliminated, the quality of the bulk of the wafer becomes excellent, and the recombination lifetime, which is an important characteristic for an IGBT wafer, can be improved.
Furthermore, since the interstitial oxygen concentration is below the above range, the concentration of oxygen donors generated after the heat treatment of the wafer can be suppressed to 9.8 × 10 ¹² ions / cm ³ or less, and the resistivity of the wafer before and after the heat treatment can be reduced. The change can be prevented and the quality of the silicon single crystal wafer can be stabilized.
Moreover, according to the silicon single crystal wafer of the present invention, since the variation in resistivity within the wafer surface is 5% or less, the quality of the silicon single crystal wafer can be stabilized.
Furthermore, by doping the silicon single crystal with nitrogen within the above range, COP defects and dislocation clusters can be easily eliminated. If the doping amount of nitrogen is less than the above range, COP defects and dislocation clusters may not be completely eliminated, and if it exceeds the above range, nitrides are generated and a silicon single crystal cannot be grown.
Further, the pass rate of TZDB is 90% or more, the concentration of oxygen donor generated when heat treatment is performed at 450 ° C. for 1 hour is 9.8 × 10 ¹² ions / cm ³ or less, and 4% at 800 ° C. The density of BMD precipitated when performing a two-stage heat treatment at 1000 ° C. for 16 hours at 5 ° C. is 5 × 10 ⁷ pieces / cm ³ or less, and the recombination lifetime when performing the two-stage heat treatment is 100 μsec or more. Therefore, the characteristics required for a silicon single crystal wafer for IGBT can be satisfied.

(Experimental example 1)
Silicon ingots having various interstitial oxygen concentrations were produced by the CZ method. Specifically, the polycrystalline silicon lump was put into a quartz crucible, and the polycrystalline silicon lump was heated in an argon atmosphere to obtain a silicon melt. Phosphorus was added as a dopant to the silicon melt. The amount of phosphorus added was adjusted so that the resistivity of the silicon single crystal was 65 Ω · cm. Next, the seed crystal is immersed in the silicon melt while supplying a horizontal magnetic field of 3000 G (0.3 T) from the magnetic field supply device so that the magnetic field center height is −75 to +50 mm with respect to the melt surface. Then, while rotating the seed crystal and the quartz crucible, the seed crystal was gradually pulled up to grow a single crystal under the seed crystal. The growth rate (pulling rate) of the single crystal is V (mm / min), and the ratio V / G when the temperature gradient G is 1350 ° C. from the melting point during single crystal growth is 0.185. The V was set to 0.49 mm / min. In this way, an ingot of single crystal silicon that was pulled under the pulling conditions of Conditions 1 to 4 was manufactured. The interstitial oxygen concentration in the silicon ingot was controlled by adjusting the rotation speed of the quartz crucible. In condition 4, a silicon wafer with a silicon nitride film was introduced into the silicon melt, thereby doping the silicon single crystal with 4.1 × 10 ¹⁴ atoms / cm ³ of nitrogen.

  Next, the pulled single crystal silicon ingot was sliced to cut out the wafer. The cut wafer was subjected to surface treatment such as lapping and etching. In this way, a silicon single crystal wafer having a diameter of 200 mm and a thickness of 0.75 mm was manufactured.

For the obtained silicon single crystal wafer, the interstitial oxygen concentration was measured, and the variation in resistivity within the wafer surface was evaluated. The interstitial oxygen concentration was measured according to the Fourier transform infrared spectrophotometry standardized by ASTM F-121 (1979). In addition, the resistivity variation is measured at a total of three locations, the wafer center, the middle position between the wafer center and outer periphery, and the position 5 mm from the wafer outer periphery, and the maximum and minimum values are selected from the three resistivities. A value was selected and calculated according to the formula “(maximum value−minimum value) × 100 / minimum value”. The results are shown in Table 1.
Further, Table 1 shows the allowable range of the pulling speed. This allowable width is obtained by gradually reducing the pulling rate of the crystal, vertically slicing the crystal in the growth direction, and observing the Grown-in defect distribution by Cu-decoration after X-ray topography. In addition, the pulling speed margin is such that COP defects and dislocation clusters can be eliminated in the entire crystal diameter direction in which dislocation cluster regions are determined by measuring light etching defects.

As shown in Table 1, it was found that the interstitial oxygen concentration can actually be reduced by reducing the crucible rotation speed from 7 rpm to 1 rpm (condition 1 → conditions 2 to 4). However, in conditions 1 and 2, although the crystal rotation speed was slow, the allowable range of the pulling speed could be secured to some extent, but the variation in resistivity was very large.
Further, comparing conditions 2 and 3, in condition 3, the variation in resistivity was reduced by increasing the rotation speed of the crystal, but the allowable range of the pulling speed was greatly reduced. This is presumably because the solid-liquid interface shape between the silicon melt and the single crystal changed due to the increase in the rotation speed of the single crystal.
Furthermore, with respect to the condition 4, the allowable range of the pulling rate was increased by doping nitrogen with respect to the condition 3, but the variation in resistivity was also increased. This is presumably because the convection state of the silicon melt was changed by nitrogen doping.

  From the above, under the pulling conditions of Conditions 1 to 4, it was difficult to simultaneously achieve reduction in interstitial oxygen concentration, reduction in variation in resistivity, and increase in the allowable range of pulling speed.

(Experimental example 2)
Silicon ingots having various interstitial oxygen concentrations were produced by the CZ method. Specifically, the polycrystalline silicon lump was put into a quartz crucible, and the polycrystalline silicon lump was heated in an argon atmosphere to obtain a silicon melt. The seed crystal was immersed in the silicon melt, and then the seed crystal was gradually pulled up while rotating the seed crystal and the quartz crucible to grow a single crystal under the seed crystal. The growth rate (pulling rate) of the single crystal is V (mm / min), and the ratio V / G when the temperature gradient G is 1350 ° C. from the melting point during single crystal growth is 0.185. The V was set to 0.49 mm / min. In this manner, single crystal silicon ingots pulled under the pulling conditions 5 to 14 were manufactured.

In conditions 5 and 6, a silicon wafer with a silicon nitride film was introduced into the silicon melt, and nitrogen was doped into the silicon single crystal. Moreover, in conditions 7-11, hydrogen gas was introduce | transduced into argon gas atmosphere and it pulled up on the conditions of hydrogen partial pressure 30-400 Pa. Further, under conditions 12 to 14, nitrogen doping and hydrogen gas introduction were performed simultaneously. Furthermore, in conditions 7-10 and 12-13, the resistivity is adjusted by adding phosphorus to the silicon melt, and in other conditions, neutrons are applied to the single crystal silicon pulled up in the same manner as in Experimental Example 1. Irradiated with rays and doped with phosphorus. Irradiation with neutrons was performed under the condition of irradiation with a bundle of 3.0 × 10 ¹² particles / cm ² / s for 80 hours. In this way, the resistivity of the silicon single crystal was adjusted to 50 Ω · cm.

  Thereafter, a single crystal silicon ingot was sliced to cut out a wafer. The cut wafer was subjected to surface treatment such as lapping and etching. In this way, a silicon single crystal wafer having a diameter of 200 mm and a thickness of 0.75 mm was manufactured.

  For the obtained silicon single crystal wafer, the interstitial oxygen concentration was measured in the same manner as in Experimental Example 1, and the variation in resistivity within the wafer surface was evaluated. The results are shown in Table 2. Table 2 also shows the nitrogen concentration in the wafer, the hydrogen partial pressure in the atmosphere of the CZ furnace, and the conditions for the dopant introduction method. Further, similarly to Experimental Example 1, the allowable range of the pulling speed is shown at the same time.

As shown in Tables 1 and 2, the variation in resistivity deteriorated by nitrogen doping in condition 4 was improved by performing phosphorous doping by neutron irradiation as shown in conditions 5 and 6, but the allowable range of pulling rate Was not enough.
In addition, the allowable range of the pulling rate that was reduced by increasing the rotation speed of the crystal in Condition 3 was improved by introducing hydrogen into the atmosphere as shown in Conditions 8-10. As in conditions 8 to 10, while introducing a predetermined amount of hydrogen and controlling the crucible rotation speed and the single crystal rotation speed, the interstitial oxygen concentration is reduced, the variation in resistivity is reduced, and the pulling speed is increased. It has been found that an increase in the allowable range can be realized at the same time.
Also, the variation in resistivity increased by nitrogen doping in condition 4 was improved by introducing hydrogen into the atmosphere as shown in conditions 12 and 13. This is considered to be because the change in the convection state of the silicon melt caused by nitrogen doping was suppressed by introducing hydrogen. Moreover, in conditions 12 and 13, the allowable range of the pulling rate could be expanded as compared with the case of nitrogen doping alone (conditions 5 to 6) and hydrogen introduction alone (conditions 7 to 11).
Furthermore, with respect to these conditions 12 and 13, in the condition 14 in which phosphorus was introduced by neutron irradiation, the variation in resistivity was further reduced.

(Experimental example 3)
A wafer cut from a φ300 mm silicon single crystal containing no COP and dislocation and having an oxygen concentration of 11.0 × 10 ¹⁷ atoms / cm ³ (ASTM F121-1979) at the center of the wafer was prepared. This wafer was subjected to RTA treatment (hole injection treatment) in a lamp annealing furnace under conditions of 1200 ° C. and 10 seconds in a mixed gas atmosphere of argon and ammonia. Thereafter, in order to measure the BMD density in the wafer depth direction (thickness direction), as shown in Table 4, heat treatment as a hole control heat treatment step S04 (a heat treatment time of 1000 ° C. in a nitrogen atmosphere is set to 0, 0, 0, 0). 5, 1, 2, hours) and a heat treatment simulating an IGBT manufacturing process was performed at 800 ° C. for 4 hours + 1000 ° C. for 16 hours in a nitrogen atmosphere.

Thereafter, the light etching solution was infiltrated for 3 minutes, and the pits revealed by etching were measured using an optical microscope. Precipitation heat treatment was performed using a horizontal furnace. After the furnace temperature reached a set value, a sample wafer was directly put into the furnace, and after a predetermined time had elapsed, the sample was taken out of the furnace.
The BMD density measurement results are shown in FIG.

From this result, the BMD density distribution of the wafer that has been subjected only to the IGBT device process heat treatment at a level (standard 1) where the hole control heat treatment set at 1000 ° C. is not performed, that is, 800 ° C. for 4 hours and 1000 ° C. for 16 hours is And an M-shaped distribution with a higher density at the bulk center. At level 2 to which a hole control heat treatment at 1000 ° C. for 30 minutes is added, the BMD density of the surface layer decreases, but precipitates remain in the vicinity of a depth of 50 μm. Furthermore, at the level (levels 3 and 4) to which 1 hour and 2 hours and pore control heat treatment were added (surfaces 3 and 4), the precipitates on the surface layer disappeared, and a BMD density of 5 × 10 ⁴ / cm ² or more could be secured in a depth region of 150 μm or more from the surface layer. I can see that Therefore, before the IGBT device process heat treatment, the surface layer precipitates disappear, and the pore control heat treatment for forming the precipitates in the bulk has a temperature of 1000 ° C. for 1 hour or equivalent to the condition of the Z region shown in FIG. It was confirmed that it was necessary.

  It is possible to increase the pulling speed margin, and no EG treatment is required, and there is a DZ layer having a sufficient thickness as an IGBT wafer and has an IG capability and a small variation in resistivity. The manufacturing method of the silicon single crystal wafer for IGBT which can be manufactured, and the silicon single crystal wafer for IGBT can be provided.

Claims (3)

A method for producing a silicon single crystal wafer for IGBT obtained by growing a silicon single crystal by the Czochralski method,
A pulling step of growing a single crystal having a growth rate of the silicon single crystal at a speed at which a grown-in defect-free silicon single crystal can be pulled and an interstitial oxygen concentration of 8.5 × 10 ¹⁷ atoms / cm ³ or less;
A hole injection step of performing RTA treatment of a wafer sliced from the single crystal at 1175 ° C. or higher;
After the hole injecting step, heat treatment is performed at a temperature range of 1000 ° C. to 1100 ° C. for a processing time of 1 to 16 hours to form an IGBT device having a thickness direction dimension of 100 to 200 μm on the surface side of the entire wafer surface. A hole-control heat treatment step for forming a device region and a gettering region to be removed after device formation on the back side of the device region;
Have
When a silicon single crystal is grown by the Czochralski method, an n-type dopant is added to the silicon melt, or phosphorus is added to the silicon melt at 2.9 × 10 ¹³ atoms / cm ³ or more to 2.9 × 10 ¹⁵ atoms. / cm ³ or less, the Do p-type dopant small segregation coefficient than the phosphorus, so that the concentration in the crystal in accordance with the segregation coefficient becomes 1 × ¹⁰ 15 atoms / cm ³ or less 1 × ¹⁰ 13 atoms / cm ³ or more A method for producing a silicon single crystal wafer for IGBT, characterized by doping phosphorus by adding neutron to the silicon single crystal after being pulled or by neutron irradiation. 2. The method for producing a silicon single crystal wafer for IGBT according to claim 1, wherein the silicon single crystal is doped with nitrogen of 5 × 10 ¹² atoms / cm ³ or more and 5 × 10 ¹⁵ atoms / cm ³ or less.   3. The production of a silicon single crystal wafer for IGBT according to claim 1, wherein a hydrogen atom-containing material having a partial pressure of hydrogen gas equivalent to 40 Pa or more and 400 Pa or less is introduced into the atmosphere gas in the CZ furnace. Method.

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