JP2010222241A - Silicon single crystal wafer for igbt and method for manufacturing silicon single crystal wafer for igbt - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To manufacture a wafer which has little variation in resistivity and in which the occurrence of oxygen deposits is extremely suppressed even after it is allowed to pass through an IGBT (Insulated Gate Bipolar Transistor) manufacturing process. <P>SOLUTION: In a method for manufacturing a silicon single crystal wafer for IGBT, obtained by growing a silicon single crystal by a Czochralski method, the single crystal having interstitial oxygen concentration of ≤6×10<SP>17</SP>atoms/cm<SP>3</SP>is grown under such conditions that the magnetic field intensity is ≥2,000 gauss, the number of revolutions of a quarts crucible is ≤1.5 rpm, the number of revolutions of the crystal is ≤7.0 rpm, and the pulling speed of the silicon single crystal is set to a pulling speed at which the silicon single crystal free from dislocation cluster defects can be pulled. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an IGBT silicon single crystal wafer used for manufacturing an insulated gate bipolar transistor (IGBT) and a method for manufacturing an IGBT silicon single crystal wafer.

Insulated Gate Bipolar Transistor (hereinafter referred to as IGBT) is a gate voltage-driven switching element suitable for controlling high power, and is used for inverters in trains, hybrid cars, air conditioners, refrigerators, etc. It has been. As shown in FIGS. 5A to 5C, the IGBT is provided with three electrodes, ie, an emitter E, a collector C, and a gate G, and is applied to the gate formed on the surface side of the element through the insulating oxide film SiO2. The current between the emitter E on the device surface side and the collector C on the back surface side is controlled by the applied voltage.
As described above, since the IGBT is an element that controls current with a gate insulated by an oxide film, the quality of the gate oxide film (Gate Oxide Integrity, hereinafter referred to as GOI) is important. If a defect is included in the silicon single crystal wafer, the defect is taken into the gate oxide film and causes a dielectric breakdown of the oxide film.

Further, the IGBT is not an element that uses only the vicinity of the wafer surface in the horizontal direction like an LSI such as a memory, but is an element that uses the wafer in the vertical direction (thickness direction) as shown in FIGS. 5A to 5C. Properties are affected by the bulk quality of the wafer. In particular, recombination lifetime and resistivity are important qualities. Since the recombination lifetime is reduced by crystal defects in the substrate, it is necessary to control so that no crystal defects occur even after the device process. Regarding the resistivity, uniformity and stability are required. It is important that it is uniform not only in the plane of the wafer but also between the wafers, that is, in the length direction of the silicon ingot, and does not change even after the device thermal process.
If multiple elements are provided in parallel on the wafer plane, if the resistivity differs between these elements, a large current will be concentrated on the low resistivity element, resulting in damage. And stability is important. As described above, when a plurality of elements are miniaturized in parallel, a large current is concentrated due to the difference in resistivity, and the current is concentrated on a specific element, resulting in damage. It is important that the process does not change.

Further, as shown in FIG. 5A, as a substrate for a so-called punch through (hereinafter referred to as PT) type IGBT in which the depletion layer contacts the collector side when the current is turned off, an epitaxial wafer (hereinafter referred to as an epi wafer) is used. Is used. However, the PT type IGBT has a problem of high cost because it uses an epi-wafer. In addition, switching loss increases at high temperatures for lifetime control. For this reason, the ON voltage decreases at a high temperature, and current may concentrate on a specific element during parallel use, causing damage.
In order to overcome the drawbacks of the PT-type substrate, a non-punch through (hereinafter referred to as NPT) type IGBT in which the depletion layer does not contact the collector side at the time of OFF has been developed. More recently, a FS-IGBT having a trench gate structure and a field stop (hereinafter referred to as FS) layer formed on the collector side as shown in FIG. It has come to be manufactured. As a substrate for an NPT type or FS type IGBT, a wafer having a diameter of 150 mm or less (hereinafter referred to as an FZ wafer) cut out from a silicon single crystal conventionally grown by a floating zone method (hereinafter referred to as FZ method). ) Is used.

Although the FZ wafer is cheaper than the epi wafer, it is necessary to increase the diameter of the wafer in order to further reduce the manufacturing cost of the IGBT. However, it is extremely difficult to grow a single crystal having a diameter larger than 150 mm by the FZ method, and even if it can be produced, it is difficult to stably supply it at a low price.
Therefore, we tried to manufacture a silicon single crystal wafer for IGBT by the Czochralski method (CZ method) that can easily grow a large diameter crystal having a diameter of 200 mm or more, preferably 300 mm or more.

The techniques described in Patent Documents 1 to 3 described below are all aimed at reducing defects in the wafer. In Patent Document 1, the entire surface is grown by the CZ method and doped with nitrogen. A silicon single crystal comprising an N-region, having an interstitial oxygen concentration of 8 ppma or less, or doped with nitrogen, excluding at least void type defects and dislocation clusters from the entire surface, and having an interstitial oxygen concentration of 8 ppma or less A wafer is disclosed.
Patent Document 2 discloses a method for producing a silicon single crystal that is pulled up using the Czochralski method while being doped with oxygen and nitrogen, and is 6.5 × 10 ¹⁷ atoms / A method for producing a silicon single crystal doped with oxygen at a concentration of less than cm ³ and nitrogen at a concentration of more than 5 × 10 ¹³ atoms / cm ³ is disclosed.
Further, in Patent Document 3, a nitrogen concentration of 2 × 10 ¹⁴ atoms / cm ³ or more and 2 × 10 ¹⁶ atoms / cm ³ or less grown from a melt added with nitrogen by the Czochralski method, and 7 × 10 ¹⁷ atoms is used. Containing oxygen concentration of / cm ³ or less, various surface defect densities are FPD ≦ 0.1 / cm ² , SEPD ≦ 0.1 / cm ² , and OSF ≦ 0.1 / cm ² , A silicon semiconductor substrate is disclosed in which the defect density is LSTD ≦ 1 × 10 ⁵ pieces / cm ³ and the oxide film breakdown voltage characteristics are TZDB high C mode pass rate ≧ 90% and TDDB pass rate ≧ 90%.

JP 2001-146498 A JP 2000-7486 A JP 2002-29891 A

However, although Patent Documents 1 to 3 disclose a method for manufacturing a wafer that is free of crystal defects, the wafer characteristics necessary for the IGBT are not clarified. Moreover, in order to shorten the manufacturing time, reduce the manufacturing cost, and efficiently and inexpensively manufacture the wafer for IGBT, it is necessary to increase the pulling speed. The wafer characteristics for IGBT in a wafer sliced from a single crystal pulled at a pulling speed at which defects exist are not clear. In particular, nothing has been elucidated about the problem of resistivity fluctuation due to oxygen donors and the problem of leakage failure due to oxygen precipitates in the IGBT manufacturing process as described later. In order to grow a crystal having such an interstitial oxygen concentration of 6 × 10 ¹⁷ atoms / cm ³ or less and a variation in resistivity within the wafer surface of 8% or less with such CZ silicon, The rotational speed and the rotational speed of the crystal need to be significantly changed from the conventional conditions, and the pulling speed margin at which defect-free crystals can be grown becomes small, resulting in a decrease in yield.

  The present invention has been made in view of the above circumstances, and it is possible to expand the pulling rate margin, improve the oxide film breakdown voltage characteristics, reduce the variation in resistivity, and reduce the oxygen in the IGBT manufacturing process. It is an object of the present invention to provide a method for producing a silicon single crystal wafer for IGBT and a silicon single crystal wafer for IGBT, which are capable of producing a wafer with very few precipitates at a low cost in a short time.

When a silicon single crystal wafer is manufactured by the Czochralski method (hereinafter sometimes referred to as CZ method), a wafer having a large diameter of about 300 mm can be manufactured. The wafer manufactured by the CZ method is as follows. For this reason, it is not suitable for an IGBT wafer.
(1) In the CZ method, excessive vacancies at the time of growing a single crystal are aggregated to generate COP defects (Crystal Originated Particles) of about 0.2 to 0.3 μm. When manufacturing an IGBT, a gate oxide film is formed on the wafer surface. When a COP defect formed by exposing a COP defect to the wafer surface or a COP defect existing in the vicinity of the wafer surface is taken into the gate oxide film. , To deteriorate the GOI (Gate Oxide Integrity). Therefore, a wafer with reduced influence of COP defects is required so that the GOI does not deteriorate, but it is difficult to manufacture such a wafer by the CZ method.
(2) The silicon single crystal wafer manufactured by the CZ method contains excess oxygen of about 1 × 10 ¹⁸ atoms / cm ³ , and such a wafer has a low temperature of about 1 hour at 450 ° C. When heat treatment (heat treatment corresponding to the sintering process in the IGBT manufacturing process) is performed, oxygen donors are generated, and the resistivity of the wafer changes before and after the heat treatment.
(3) The resistivity of a silicon single crystal wafer manufactured by the CZ method can be controlled by the amount of dopant added to the silicon melt, and phosphorus is added to the IGBT wafer as a dopant, but phosphorus has a segregation coefficient. Since it is small, the concentration greatly changes along the length direction of the silicon single crystal. Therefore, within a single silicon single crystal, the range of wafers having a resistivity that matches the design specifications is narrow.
The silicon single crystal wafer produced by (4) CZ ^{method, 1 × 10 18 atoms / cm} 3 of about contains excess oxygen, when a device formation process on such wafers, the excess Oxygen becomes SiO ₂ and precipitates oxygen, which causes deterioration of recombination lifetime and leakage failure, and degrades IGBT characteristics.

(5) CZ silicon contains about 10 × 10 ¹⁷ atoms / cm ³ of oxygen, and when subjected to a low temperature heat treatment of about 450 ° C., oxygen donors are generated and the resistivity of the substrate changes. Therefore, there has been a demand for eliminating the resulting deterioration in breakdown voltage characteristics and variations in resistivity. In particular, in the conventional method, even if a silicon single crystal having a diameter of 200 mm or more, that is, a silicon single crystal having a diameter of 200 mm or more is grown, an oxygen concentration of 6 × 10 ¹⁷ atoms / cm ^{3 is produced.} (ASTM F121, 1979) is the limit, and it is difficult to stably grow a silicon single crystal having this oxygen concentration or less over a wide range in the crystal axis direction of the single crystal straight body portion. An IGBT silicon single crystal wafer having an oxygen concentration of 6 × 10 ¹⁷ atoms / cm ³ or less in the entire in-plane region could not be realized while maintaining the uniformity of resistivity.

  In order to solve the above problems (1) to (5), the present inventors have conducted intensive research. As a result, by adopting the following configuration, a wafer having the wafer characteristics necessary for the IGBT is obtained as CZ. It was found that it can be manufactured using the method.

The method for producing a silicon single crystal wafer for IGBT of the present invention is a method for producing a silicon single crystal wafer for IGBT obtained by growing a silicon single crystal by the Czochralski method,
The magnetic field strength is 2000 gauss or more, the quartz crucible rotation speed is 1.5 rpm or less, the crystal rotation speed is 7.0 rpm or less,
A single crystal having an interstitial oxygen concentration of 6 × 10 ¹⁷ atoms / cm ³ or less is grown at a speed at which the silicon single crystal can be pulled up by a transition cluster defect-free silicon single crystal.
The method for producing a silicon single crystal wafer for IGBT of the present invention is a method for producing a silicon single crystal wafer for IGBT obtained by growing a silicon single crystal by the Czochralski method,
The magnetic field strength is 2000 gauss or more,
Quartz crucible rotation speed R1 (rpm) and crystal rotation speed R2 (rpm)
As shown by each point (R1, R2) in FIG.
Point A (0.1,1), Point B (0.1,7), Point C (0.5,7), Point I (0.7,6), Point E (1,6), Point F (2, 2), set to a value within the range surrounded by point G (2, 1),
A single crystal having an interstitial oxygen concentration of 6 × 10 ¹⁷ atoms / cm ³ or less is grown at a speed at which the silicon single crystal can be pulled up by a transition cluster defect-free silicon single crystal.
In the present invention, it is preferable that the silicon wafer sliced from the silicon single crystal is subjected to COP influence exclusion heat treatment that is performed at 1050 ° C. or higher and below the melting point of silicon for 1 to 10 hours.
In the method for producing a silicon single crystal wafer for IGBT of the present invention, when growing a silicon single crystal by the Czochralski method, an n-type dopant is added to the silicon melt, or phosphorus is added to the silicon melt at 2.9 ×. 10 ¹³ atoms / cm ³ or more and 2.9 × 10 ¹⁵ atoms / cm ³ or less, a p-type dopant having a segregation coefficient smaller than that of phosphorus, and the concentration in the crystal is 1 × 10 ¹³ atoms / cm 3 depending on the segregation coefficient. Phosphorus can be doped by adding ^{3 to} 1 × 10 ¹⁵ atoms / cm ³ or less, or irradiating the pulled silicon single crystal with neutrons.
The method for producing a silicon single crystal wafer for IGBT of the present invention is a method for producing a silicon single crystal wafer for IGBT obtained by growing a silicon single crystal by the Czochralski method,
A magnetic field having a magnetic field strength of 2000 Gauss or more is applied to a quartz crucible containing a silicon melt to which a dopant for adjusting electrical resistivity in a silicon single crystal is not added, and the rotation speed of the quartz crucible is 1.5 rpm or less and The growth rate of the silicon single crystal being grown was set to 7.0 rpm or less, and the silicon single crystal having an oxygen concentration of 6 × 10 ¹⁷ atoms / cm ³ or less was grown. It is characterized by doping with phosphorus.
In the present invention, the pulling speed of the silicon single crystal can be set to a pulling speed capable of eliminating COP defects and dislocation clusters in the entire crystal diameter direction.
In the present invention, nitrogen may be added to the silicon single crystal at a concentration of 6 × 10 ¹² atoms / cm ³ or more and 5 × 10 ¹⁵ atoms / cm ³ or less.
In the present invention, a polycrystalline silicon layer of 50 nm or more and 1000 nm or less can be formed on the back side of the silicon single crystal wafer.
The silicon single crystal wafer for IGBT of the present invention is manufactured by any of the manufacturing methods described above,
Dislocation clusters are eliminated in the entire crystal diameter direction, the interstitial oxygen concentration is 6 × 10 ¹⁷ atoms / cm ³ or less, and the variation in resistivity within the wafer surface can be 8% or less.
When the silicon single crystal of the present invention is grown by the Czochralski method, it is grown at a pulling speed capable of pulling up a transition cluster defect-free silicon single crystal, and the silicon single crystal after pulling The material may be doped with neutrons and doped with phosphorus.
When the silicon single crystal of the present invention is grown by the Czochralski method, it is grown at a pulling speed capable of pulling a transition cluster defect-free silicon single crystal from a silicon melt doped with an n-type dopant. Can be.
In the silicon single crystal wafer for IGBT of the present invention, phosphorus and a p-type dopant having a segregation coefficient smaller than that of phosphorus are 1 × 10 ¹³ atoms / cm ³ or more and 1 × 10 ¹⁵ atoms / cm ³ or less, respectively. Can be included.
The silicon single crystal wafer for IGBT of the present invention has an LPD density on the wafer surface of 0.1 piece / cm ² or less and a light etching defect density of 1 × 10 ³ pieces / cm ² or less.
The silicon single crystal wafer for IGBT of the present invention can have a polycrystalline silicon layer of 50 nm or more and 1000 nm or less formed on the back side.

The present invention is such that the silicon single crystal is grown at a pulling speed capable of pulling a dislocation cluster defect-free silicon single crystal when grown by the Czochralski method, and the silicon single crystal after the pulling is grown. Means in which the crystal is irradiated with neutrons and doped with phosphorus, or when the silicon single crystal is grown by the Czochralski method, dislocation from a silicon melt doped with an n-type dopant Either means grown by a pulling speed capable of pulling up a cluster defect-free silicon single crystal, or phosphorus and a p-type dopant having a segregation coefficient smaller than that of phosphorus are 1 × 10 ¹² atoms / cm ³ , respectively. It is possible to employ means that is contained at a concentration of 1 × 10 ¹⁵ atoms / cm ³ or less.
In the present invention, the LPD density of 0.1 μm or more on the wafer surface can be 0.1 pieces / cm ² or less, and the light etching defect density can be 1 × 10 ² pieces / cm ² or less.
In the present invention, a polycrystalline silicon layer having a thickness of 50 nm to 1000 nm can be formed on the back surface side.

Conventionally, when a silicon single crystal is pulled up from a silicon melt to which a dopant is added, the oxygen concentration distribution and the dopant concentration distribution in the crystal diameter direction (in-plane) become non-uniform as the crystal rotation speed slows down. It is known that the variation in resistivity increases. For this reason, single crystal growth has been carried out by reducing the in-plane oxygen concentration and resistivity variation by increasing the crystal rotation speed to 10 rpm or higher.
However, according to the experiments by the present inventors, in a situation where the rotation speed of the quartz crucible is 1.5 rpm or less, the crystal rotation speed is a control factor that can reduce the oxygen concentration in the single crystal, and the crystal crucible It has been found that the oxygen concentration in the single crystal can be further reduced by lowering the rotation speed. Although the in-plane oxygen concentration distribution is deteriorated by slowing down the crystal rotation speed, if the silicon single crystal has an oxygen concentration of 6 × 10 ¹⁷ atoms / cm ³ or less, the variation in the oxygen concentration distribution becomes an IGBT characteristic. Was also found to have no effect.

In the present invention, the resistivity variation can be surely made 8% or less.
In the present invention, nitrogen can be added to the silicon single crystal at a concentration of 6 × 10 ¹² atoms / cm ³ or more and 5 × 10 ¹⁵ atoms / cm ³ or less.
In the present invention, when the dopant is not added at the stage of growing the silicon single crystal, even if the crystal rotation speed is reduced, the resistivity distribution in the silicon single crystal is not affected. It is possible to reduce resistivity variation by doping phosphorus with neutron irradiation.

The method for producing a silicon single crystal wafer for IGBT of the present invention is a method for producing a silicon single crystal wafer for IGBT obtained by growing a silicon single crystal by the Czochralski method,
A magnetic field is applied to the silicon melt stored in the quartz crucible in the furnace (inside the CZ furnace), the quartz crucible is rotated, and the silicon single crystal is pulled up from the silicon melt while rotating in the opposite direction to the quartz crucible. While growing the silicon single crystal while growing,
Cutting a silicon wafer from the silicon single crystal,
In the silicon single crystal growth step, the intensity of the magnetic field applied to the silicon melt is 2000 gauss or more, the rotation speed of the quartz crucible is 1.5 rpm or less, and the rotation speed of the silicon single crystal is 7.0 rpm or less. ,
The first stage silicon single crystal is pulled at a speed capable of pulling a dislocation cluster defect-free silicon single crystal, and a silicon single crystal having an interstitial oxygen concentration of 6 × 10 ¹⁷ atoms / cm ³ or less is grown. It is a manufacturing method of a silicon single crystal wafer.
In the method for producing a silicon single crystal wafer, in the silicon single crystal growing step, the rotation speed R1 (rpm) of the quartz crucible and the rotation speed R2 (rpm) of the silicon single crystal are shown in FIG. As indicated by each point (R1, R2), point A (0.1, 1), point B (0.1, 7), point C (0.5, 7), point I (0.7, 6) ), E (1, 6), F (2, 2), and G (2, 1).

In the above method for producing a silicon single crystal wafer for IGBT, when a silicon single crystal is grown by the Czochralski method, an n-type dopant may be added to the silicon melt.
Further, in the above method for producing a silicon single crystal wafer for IGBT, when a silicon single crystal is grown by the Czochralski method, the concentration of phosphorus in the silicon melt is 2.9 × 10 ¹³ atoms / cm ^3. The p-type dopant having a segregation coefficient smaller than that of phosphorus is added so as to be 2.9 × 10 ¹⁵ atoms / cm ³ or less, and the concentration in the crystal is 1 × 10 ¹³ atoms / cm according to the segregation coefficient. ³ to 1 × ¹⁰ 15 atoms / cm ³ may be added to become less.
Or the manufacturing method of the said silicon single crystal wafer for IGBT may have a process which further irradiates neutron to the silicon single crystal after raising, and dopes phosphorus to the silicon single crystal.
In the silicon single crystal growth step, the strength of the magnetic field applied to the silicon melt may be 3000 gauss or more.
In the silicon single crystal growth step, the magnetic field applied to the silicon melt may be a horizontal magnetic field, a vertical magnetic field, or a cusp magnetic field.
In the above method for manufacturing a silicon single crystal wafer for IGBT, it is preferable that the pressure of the atmospheric gas in the furnace in the silicon single crystal growth step is 1333 Pa to 26660 Pa. Preferably, the pressure of the atmospheric gas in the furnace may be 4000 Pa to 9333 Pa.

The method for producing a silicon single crystal wafer for IGBT of the present invention is a method for producing a silicon single crystal wafer for IGBT obtained by growing a silicon single crystal by the Czochralski method, and is stored in a quartz crucible in a furnace. A silicon single crystal growth step (Non-Dopped and Non-Doped) is performed by applying a magnetic field to the silicon melt, rotating the quartz crucible, and pulling up the silicon single crystal from the silicon melt while rotating in a direction opposite to the quartz crucible. Doped)
A step of doping the grown silicon single crystal with neutron irradiation to dope phosphorus; and a step of cutting a silicon wafer from the silicon single crystal. In the silicon single crystal growth step, a magnetic field applied to the silicon melt Silicon whose strength is 2000 gauss or more, the rotation speed of the quartz crucible is 1.5 rpm or less, the rotation speed of the silicon single crystal is 7.0 rpm or less, and the interstitial oxygen concentration is 6 × 10 ¹⁷ atoms / cm ³ or less. It may be a method for producing a silicon single crystal wafer characterized by growing a single crystal.
In the above-described method for manufacturing a silicon single crystal wafer for IGBT, the silicon melt may not be added with a dopant for adjusting electric resistivity in the silicon single crystal.
The IGBT silicon single crystal wafer of the present invention is an IGBT silicon single crystal wafer made of a silicon single crystal grown by the Czochralski method, and dislocation clusters are eliminated in the entire region in the crystal diameter direction. The oxygen concentration is 6 × 10 ¹⁷ atoms / cm ³ or less, and the variation in resistivity within the wafer surface is 8% or less.
The silicon single crystal wafer for IGBT may be a silicon single crystal wafer manufactured by any one of the manufacturing methods described above.

The silicon single crystal wafer is grown at a pulling speed capable of pulling up a transition cluster defect-free silicon single crystal when the silicon single crystal is grown by the Czochralski method, and after the pulling The silicon single crystal may be irradiated with neutron and doped with phosphorus.
The silicon wafer of the present invention has a pulling speed capable of pulling a silicon single crystal free of transition cluster defects from a silicon melt doped with an n-type dopant when the silicon single crystal is grown by the Czochralski method. It may be cultivated in
In the silicon single crystal wafer, silicon containing phosphorus and a p-type dopant having a segregation coefficient smaller than that of phosphorus at a concentration of 1 × 10 ¹³ atoms / cm ³ or more and 1 × 10 ¹⁵ atoms / cm ³ or less, respectively. It may be a single crystal wafer.
The silicon single crystal wafer may have an LPD density of 0.1 μm or more on the wafer surface of 0.1 piece / cm ² or less and a light etching defect density of 1 × 10 ³ pieces / cm ² or less.

In the IGBT silicon single crystal wafer, the silicon single crystal is preferably doped with nitrogen of 6 × 10 ¹² atoms / cm ³ or more and 5 × 10 ¹⁵ atoms / cm ³ or less.
In the silicon wafer of the present invention, a polycrystalline silicon layer of 50 nm or more and 1000 nm or less may be formed on the back surface side.
In the above-mentioned IGBT silicon single crystal wafer of the present invention, the pass rate of TZDB (time zero dielectric breakdown) at a breakdown electric field of 8 MV / cm is 90% or more, and when heat treatment is performed at 450 ° C. for 1 hour. The density of the generated oxygen donor is 9.8 × 10 ¹² ions / cm ³ or less, and the density of BMD precipitated when two-stage heat treatment is performed at 800 ° C. for 4 hours and 1000 ° C. for 16 hours is 1 × 10 It is preferably ⁵ pieces / cm ³ or less, and the recombination lifetime when the two-stage heat treatment is performed is preferably 100 μsec or more.

The manufacturing method of the silicon single crystal wafer for IGBT of the present invention has a magnetic field strength of 2000 Gauss or more,
Quartz crucible rotation speed R1 (rpm) and crystal rotation speed R2 (rpm)
As shown by each point (R1, R2) in FIG.
Point A (0.1,1), Point B (0.1,7), Point C (0.5,7), Point I (0.7,6), Point E (1,6), Point F It can be set to a value within a range surrounded by (2, 2) and point G (2, 1). Thereby, a single crystal having an interstitial oxygen concentration of 4 × 10 ¹⁷ atoms / cm ³ or less can be grown. Substantially, when the rotation speed of the quartz crucible is R1 (rpm) and the rotation speed of the crystal is R2 (rpm), the range is R1: 0.1 or more and 2 or less, R2: 1 or more and 7 or less, When R1: 0.5 or more and 0.7 or less, R2 <7-5 (R1-0.5) is satisfied, and when R1: 0.7 or more and 1 or less, R2 <6 is satisfied, and R1: 1 In the case of 2 or less, it can be set in a range satisfying R2 <6-4 (R1-1). In this case, a silicon single crystal having a low oxygen concentration can be grown by setting the interstitial oxygen concentration in the single crystal to 4.0 × 10 ¹⁷ atoms / cm ³ or less.
For this reason, oxygen donors are generated from this low oxygen single crystal when subjected to low temperature heat treatment at about 450 ° C. with low variation in resistivity and extremely low density of oxygen precipitates even after the IGBT manufacturing process. It is possible to provide a silicon single crystal wafer for IGBT that can prevent the resistivity of the substrate from changing.

Further, the quartz crucible rotation speed R1 (rpm) and the crystal rotation speed R2 (rpm)
As shown by each point (R1, R2) in FIG.
Point A (0.1,1), point B (0.1,7), point L (0.2,7), point K (0.3,7), point J (0.5,6), Pulling up the silicon single crystal by setting the value within the range surrounded by point I (0.7,6), point H (1,5), point N (1,3), and point M (1,1) Thus, a silicon single crystal having a lower oxygen concentration can be grown by setting the interstitial oxygen concentration in the single crystal to 3.5 × 10 ¹⁷ atoms / cm ³ or less. Substantially, the quartz crucible rotation speed R1 (rpm) and the crystal rotation speed R2 (rpm) are in the range of R1: 0.1 or more and 1 or less, R2: 1 or more and 7 or less, provided that R1: 0. In the case of 3 or more and 0.5 or less, R2 <7-5 (R1-0.3) is satisfied, and in the case of R1: 0.5 or more and 0.7 or less, R2 <6 is satisfied, and R1: 0. In the case of 7 or more and 1 or less, it may be set in a range satisfying R2 <6-3.4 (R1-0.7). In this case, a silicon single crystal having a low oxygen concentration can be provided by setting the interstitial oxygen concentration in the single crystal to 3.5 × 10 ¹⁷ atoms / cm ³ or less.

Further, the quartz crucible rotation speed R1 (rpm) and the crystal rotation speed R2 (rpm)
As shown by each point (R1, R2) in FIG.
Point A (0.1,1), point B (0.1,7), point L (0.2,7), point Q (0.3,6), point J (0.5,6), The silicon single crystal may be pulled up by setting a value within a range surrounded by the points P (0.7, 5), N (1, 3), and M (1, 1). Substantially, the quartz crucible rotation speed R1 (rpm) and the crystal rotation speed R2 (rpm) are in the range of R1: 0.1 or more and 1 or less, R2: 1 or more and 7 or less, provided that R1: 0. When 2 or more and 0.3 or less, R2 <7-10 (R1-0.2) is satisfied, and when R1: 0.3 or more and 0.5 or less, R2 <6 is satisfied, and R1: 0.5 In the case of 0.7 or more and 0.7 or less, R2 <6-5 (R1-0.5) is satisfied, and in the case of R1: 0.7 or more and 1 or less, R2 <5-6.7 (R1-0.7) is satisfied. It can be set to a satisfactory range. In this case, a silicon single crystal having an interstitial oxygen concentration of 3.0 × 10 ¹⁷ atoms / cm ³ or less in the single crystal can be grown, and a silicon single crystal having a lower oxygen concentration can be grown.

In the present invention, the magnetic field applied to the silicon melt can be a horizontal magnetic field, a cusp magnetic field, or the like. For example, the strength of the horizontal magnetic field is 2000 to 5000 G (0.2 T to 0.5 T). it can. If the magnetic field strength is not more than the above range, the effect of suppressing convection of the silicon melt is not sufficient, and the shape of the solid-liquid interface cannot be made preferable, and the oxygen concentration cannot be lowered sufficiently, which is not preferable. Further, if the magnetic field strength is increased beyond the above range, convection is suppressed too much, and the high temperature silicon melt advances the deterioration of the inner surface of the quartz crucible, and the dislocation-free rate of the crystal is lowered.
In the present invention, the magnetic field center position and the melt surface position during crystal pulling are preferably −75 to +50 mm, more preferably 20 to 45 mm. Here, the magnetic field center position means the height position where the center of the magnetic field generating coil is located in the horizontal magnetic field, and -75 mm means 75 mm above the melt surface. .

The method for producing a silicon single crystal wafer for IGBT of the present invention has a level of oxygen concentration of 6 × 10 ¹⁷ atoms / cm ³ (oldASTM) or less in a CZ silicon single crystal having a diameter of 200 mm (8 inches) or more. I was able to realize a level that I did not see. A silicon single crystal having an oxygen concentration of 6 × 10 ¹⁷ atoms / cm ³ or less is a crystal located between the CZ crystal and the FZ crystal, which is a conventional crystal. By growing the transition cluster defect-free crystal by the MCZ method, an oxide film breakdown voltage equivalent to that of the FZ crystal can be obtained. Moreover, by setting the oxygen concentration to 6 × 10 ¹⁷ atoms / cm ³ or less, it is possible to dispel the concern about the generation of oxygen donors during the heat treatment in the device manufacturing process, and furthermore, almost no oxygen-induced defects peculiar to CZ crystals are seen. Disappear. In the pulling by the MCZ method, the convection of the silicon melt is suppressed, the amount of dissolution of the quartz crucible is reduced, and the impurity concentration in the quartz crucible is reduced by using a synthetic quartz crucible. Can be nurtured.
Here, the synthetic quartz crucible means that at least the inner surface in contact with the raw material melt is formed of the following synthetic quartz.

Synthetic quartz is a chemically synthesized and manufactured raw material, and synthetic quartz glass powder is amorphous. Since the raw material of synthetic quartz is gas or liquid, it can be easily purified, and synthetic quartz powder can have a higher purity than natural quartz powder. Synthetic quartz glass raw materials are derived from gaseous raw materials such as carbon tetrachloride and liquid raw materials such as silicon alkoxide. In synthetic quartz powder glass, all impurities can be made 0.1 ppm or less.
In the glass obtained by melting synthetic quartz glass powder, when the light transmittance is measured, the synthetic quartz glass is made of carbon tetrachloride, which is used for ultraviolet optical applications as a raw material, and transmits ultraviolet rays up to a wavelength of about 200 nm. It is considered that the characteristics are close to.
In a glass obtained by melting synthetic quartz glass powder, when a fluorescence spectrum obtained by excitation with ultraviolet rays having a wavelength of 245 nm is measured, a fluorescence peak like a melted product of natural quartz powder is not observed.

  Whether the glass material was natural quartz by measuring the concentration of impurities contained, measuring the amount of silanol, or measuring the light transmittance, or measuring the fluorescence spectrum obtained by excitation with ultraviolet light having a wavelength of 245 nm. It can be determined whether it was quartz.

  In addition, the MCZ method makes it easier to grow an 8-inch diameter silicon single crystal compared to the FZ method, and allows the use of a quartz crucible to increase the charge, which enables a reduction in raw material costs compared to the FZ method. At the same time, the yield can be improved.

  In the present invention, in order to control the gas flow state on the surface of the silicon melt, the pressure in the furnace is 1333 Pa or more, preferably 4000 Pa to 26660 Pa. The upper limit of the pressure in the furnace is that when the pressure in the furnace increases, the gas flow rate on the melt of inert gas such as Ar decreases, so that it is difficult to exhaust the reactant gas such as SiO evaporated from the melt. As a result, the oxygen concentration in the crystal becomes higher, and SiO aggregates in the upper part of the melt in the furnace at about 1100 ° C. or at a temperature lower than this, thereby generating dust and dropping into the melt. In order to prevent the occurrence of dislocation, the upper limit of the pressure is defined in order to prevent these.

In the present invention, in order to control the gas flow state on the surface of the silicon melt, the furnace pressure is 1.3 kPa or more, preferably 4.0 to 27 kPa, and more preferably 4.0 to 9.3 kPa. Is desirable. The upper limit of the pressure in the furnace is that when the pressure in the furnace increases, the gas flow rate on the melt of inert gas such as Ar decreases, so that it is difficult to exhaust the reactant gas such as SiO evaporated from the melt. As a result, the oxygen concentration in the crystal increases, and SiO aggregates in the upper part of the melt in the furnace at about 1100 ° C. or at a lower temperature, thereby generating dust and dropping into the melt. In order to prevent dislocations, the upper limit of the pressure was specified to prevent these.
In the present invention, the atmospheric gas flow rate supplied into the CZ furnace is set to 100 to 200 liters / min or more, the pressure in the CZ furnace is set to 6700 pa or less, and SiO evaporated from the melt surface is effectively discharged out of the apparatus. At the same time, foreign matter drifting on the surface of the melt can be driven to the crucible wall, and the oxygen concentration in the crystal can be prevented from increasing.

Further, the silicon single crystal wafer for IGBT of the present invention is an IGBT silicon single crystal wafer made of silicon single crystal grown by the Czochralski method, and COP defects and dislocation clusters are eliminated in the entire crystal diameter direction. The interstitial oxygen concentration is 4 × 10 ¹⁷ atoms / cm ³ or less, and the variation in resistivity within the wafer surface can be 5% or less.
Furthermore, in the silicon single crystal wafer for IGBT of the present invention, the silicon single crystal was grown at a pulling speed capable of pulling up the silicon single crystal free of transition cluster defects when grown by the Czochralski method. It is preferable that the silicon single crystal after being pulled is irradiated with neutrons and doped with phosphorus.
Moreover, in the silicon single crystal wafer for IGBT of the present invention, when the silicon single crystal is grown by the Czochralski method, silicon free from transition cluster defects is obtained from a silicon melt doped with an n-type dopant. It is preferable that the single crystal is grown at a pulling speed capable of pulling up.
Furthermore, in the silicon single crystal wafer for IGBT of the present invention, it is preferable that the silicon single crystal is doped with nitrogen of 6 × 10 ¹² atoms / cm ³ or more and 5 × 10 ¹⁵ atoms / cm ³ or less.

Furthermore, in the silicon single crystal wafer for IGBT of the present invention, the pass rate of TZDB at a breakdown electric field of 8 MV / cm is 90% or more, and the concentration of oxygen donor generated when heat treatment is performed at 450 ° C. for 1 hour. in There is a 9.8 × ¹⁰ 12 ^{cm -3} or less, the density of BMD precipitating when performing two-stage heat treatment for 4 hours and 1000 ° C. in 16 hours 1 × 10 ⁵ cells at 800 ° C. / cm ³ or less In addition, it is preferable that the recombination lifetime when the two-stage heat treatment is performed is 100 μsec or more.
Furthermore, in the silicon single crystal wafer for IGBT of the present invention, phosphorus and a p-type dopant having a segregation coefficient smaller than that of phosphorus are 1 × 10 ¹³ atoms / cm ³ or more and 1 × 10 ¹⁵ atoms / cm ^{3, respectively.} It is preferably contained in the following concentrations.
Furthermore, in the silicon single crystal wafer for IGBT of the present invention, the LPD density on the wafer surface is 0.1 piece / cm ² or less, and the light etching defect density is 1 × 10 ³ pieces / cm ² or less. Is preferred.
Moreover, in the silicon single crystal wafer for IGBT of the present invention, it is preferable that a polycrystalline silicon layer of 50 nm or more and 1000 nm or less is formed on the back surface side.

  In the present invention, the resistivity variation (%) is measured at a total of three locations at the wafer center, a position between the wafer center and the outer periphery, and a position 5 mm from the wafer outer periphery. The maximum value and the minimum value are selected from among the values, and the values are obtained by the formula (maximum value−minimum value) × 100 / minimum value.

Further, in the present invention, “dislocation cluster defect free” means that dislocation cluster defects are excluded from all grown-in defects that may occur with crystal growth such as COP defects and dislocation clusters. A COP defect means a possessed state.
Further, in the present invention, the OSF region means that the temperature is raised from 900 ° C. to 1000 ° C. in a dry oxygen atmosphere at a heating rate of 5 ° C./min, then 1000 ° C. for 1 hour in a dry oxygen atmosphere, and then a wet oxygen atmosphere After heating at 1000 ° C. to 1150 ° C. at a rate of temperature increase of 3 ° C./min, heat treatment is performed at 1150 ° C. for 2 hours in a wet oxygen atmosphere and then to 900 ° C., and then 2 μm light etching is performed to form the OSF region. This means a region where the OSF density is 10 / cm ² when the OSF density is measured and the distribution of the OSF density in the wafer is measured.

  The Pv region and the Pi region are silicon single crystal ingots grown by the Czochralski method, and a region where interstitial silicon type point defects exist predominantly in the ingot is defined as an I region, When a region in which defects exist predominantly is a V region, and a region in which no interstitial silicon type point defect aggregates and no vacancy type point defect aggregates exist is a P region, The region below the lowest interstitial silicon concentration that belongs to the P region and can form interstitial dislocations is defined as the Pi region, and the region that is adjacent to the OSF region and that is below the vacancy concentration that can belong to the P region and form COP is defined as Pv. This is an area.

  A silicon wafer is produced by pulling up an ingot from a silicon melt in a furnace with a predetermined pulling speed profile based on the Boronkov theory by the CZ method, and then cutting out the ingot. In general, when a silicon single crystal ingot is pulled from the silicon melt in the furnace by the CZ method, point defects and agglomerates (agglomerates: three-dimensional defects) Will occur. There are two general forms of point defects: vacancies and interstitial silicon. A vacancy is one in which one silicon atom leaves one of its normal positions in the silicon crystal lattice. On the other hand, silicon atoms existing at positions (interstitial sites) other than the lattice points of the silicon crystal are interstitial silicon atoms.

Point defects are generally formed at the contact surface between a silicon melt (molten silicon) and an ingot (solid silicon). However, by continuously pulling up the ingot, the portion that was the contact surface begins to cool as it is pulled up. During cooling, vacancies or interstitial silicon atoms diffuse to form dislocation clusters that are COPs or interstitial agglomerates of vacancy agglomerates. In other words, the aggregate is a three-dimensional structure generated due to the merge of point defects. The agglomerates of vacancy-type point defects include defects called LSTD (Laser Scattering Tomograph Defects) or FPD (Flow Pattern Defects) in addition to the above-mentioned COP. Loop: a defect called a pit-like defect formed by etching dislocations. When FPD is a silicon wafer produced by cutting out an ingot for 30 minutes (Secco etching, etching with a mixed solution of HF: K ₂ Cr ₂ O ₇ (0.15 mol / l) = 2: 1) LSTD is a source that generates a scattered light having a refractive index different from that of silicon when an infrared ray is irradiated into a silicon single crystal.

Boronkov's theory is that, in order to grow an ingot with a small number of defects, the pulling speed of the ingot is V (mm / min), and the temperature gradient in the vertical direction of the ingot near the interface between the ingot and the silicon melt is G (° C./mm ), V / G (mm ² / min · ° C.) is controlled.

  Corresponding to the change of the V / G value from a high value to a low value, the above-described V region, OSF region, Pv region, Pi region, and I region are arranged in this order. For this reason, G (° C./mm) specific to the pulling apparatus is calculated by electrothermal analysis software, a pulling experiment in which the pulling speed is gradually reduced is carried out, and the single crystal pulling length defect obtained thereby By examining the distribution in advance, the pulling speed V (mm / min) necessary for obtaining the Pv region, the Pi region, and the I region can be calculated. Alternatively, the value of V / G varies depending on each actual machine, such as the structure of the hot zone in the upper part of the pulling furnace, but by measuring the COP density, OSF density, BMD density, LSTD density or FPD, light etching defect density, etc. It can be determined.

“Light etching defects” means that an As-grown silicon single crystal wafer is immersed in an aqueous copper sulfate solution and then air-dried, and then subjected to Cu decoration for about 20 minutes at 900 ° C. in a nitrogen atmosphere. In order to remove the Cu silicide layer on the surface of the specimen, it was immersed in a HF / HNO ₃ mixed solution, and the surface layer was etched and removed by about several tens of microns. And defects detected using an optical microscope. According to this evaluation method, the dislocation clusters formed at the time of crystal growth can be revealed by Cu decoration, and the dislocation clusters can be detected with high sensitivity. That is, the light etching defect includes a dislocation cluster.
In the present invention, the “LPD density” is a density of defects of 0.1 μm size or more detected using a laser light scattering particle counter (SP1 (surfscan SP1): manufactured by KLA-Tencor).

TZDB is an abbreviation for Time Zero Dielectric Breakdown, and is one of the indexes representing GOI. The pass rate of TZDB in the present invention is that the electrode area of the measurement electrode is 8 mm ² and the determination current is 1 mA, and the current-voltage curve is measured at about 416 locations on the entire wafer, causing electrostatic breakdown. The probability that there was no is taken as the pass rate of TZDB. This pass rate is also called a C-mode pass rate.

According to the silicon single crystal wafer of the present invention, dislocation clusters are excluded in the entire crystal diameter direction, and the silicon wafer sliced from the silicon single crystal is set to 1050 ° C. or higher and below the melting point of silicon for 1 to 10 hours. Since the COP can be eliminated by performing the COP influence exclusion heat treatment, it is suitable for use in an IGBT wafer which is an element that uses the wafer in the vertical direction. That is, since dislocation cluster defects and COP defects are eliminated in the entire wafer radial direction after the heat treatment for eliminating COP influence, COP defects are taken into the gate oxide film when the gate oxide film is formed on the wafer surface in the IGBT manufacturing process. And GOI is not degraded. Further, by eliminating dislocation clusters, leakage current in the integrated circuit can be prevented.
Further, since the OSF region is excluded, COP defects are not taken into the gate oxide film when the gate oxide film is formed on the wafer surface in the IGBT manufacturing process, and the GOI is not deteriorated. In addition, leakage current in the integrated circuit can be prevented. Furthermore, the yield rate can be 90% or more.

Further, since the interstitial oxygen concentration is 6 × 10 ¹⁷ atoms / cm ³ or less, the concentration of oxygen donors generated after the heat treatment of the wafer can be suppressed to 9.8 × 10 ¹² atoms / cm ³ or less. The change in the resistivity of the wafer can be prevented, and the quality of the silicon single crystal wafer can be stabilized.
The reason for setting the oxygen donor concentration to 9.8 × 10 ¹² atoms / cm ³ or less is as follows. An n-type wafer having a resistivity of 30 to 120 Ω · cm is used for the high voltage IGBT. For example, when the resistivity specification of the substrate is 50 ± 5 Ω · cm, the allowable donor concentration is 9.8 × 10 ¹² ions / cm ³ or less. Here, the temperature at which oxygen donors due to oxygen are most likely to be generated is 450 ° C. For example, in the device process, the Al wiring sintering process is performed around this temperature. FIG. 1 shows the results of examining the oxygen concentration dependence of the oxygen donor concentration generated when heat treatment is performed at 450 ° C. for 1 hour. From FIG. 1, in order to suppress the oxygen donor concentration to 9.8 × 10 ¹² atoms / cm ³ or less, the interstitial oxygen concentration of the wafer must be controlled to 8.5 × 10 ¹⁷ atoms / cm ³ or less. I understand that. In the present invention, since the interstitial oxygen concentration after the pulling is 6 × 10 ¹⁷ atoms / cm ³ or less, the influence of the oxygen donor can be surely eliminated.
Since in a normal CZ method for the interstitial oxygen concentration to 8.5 × ¹⁰ 17 atoms / cm ³ or less may be difficult, the MCZ method case of growing a single crystal by applying a magnetic field The interstitial oxygen concentration can be 8.5 × 10 ¹⁷ atoms / cm ³ or less. The interstitial oxygen concentration can also be reduced by reducing the rotation speed of the quartz crucible.

Moreover, according to the silicon single crystal wafer of the present invention, the variation in resistivity within the wafer surface is 8% or less, so that the quality of the IGBT can be stabilized.
By the way, the resistivity of a silicon single crystal wafer manufactured by the CZ method can be controlled by the amount of dopant contained in the silicon single crystal. However, since phosphorus, which is often used as a dopant for an IGBT substrate, has a small segregation coefficient, The concentration varies greatly over the length direction. Therefore, the range in which a wafer having a resistivity that meets the design specifications in one single crystal is obtained is narrow. Therefore, in the present invention, as described above, neutron irradiation, addition of an n-type dopant to the silicon melt, addition of a predetermined amount of p-type dopant having a segregation coefficient smaller than phosphorus and phosphorus, and various other means are employed. In either case, it is important to grow a single crystal using a synthetic quartz crucible with a low impurity concentration as a raw material and a low impurity elution. By using these means, the yield of the silicon single crystal can be improved.

For neutron irradiation, first, a silicon single crystal is grown without adding a dopant for adjusting the resistivity to the silicon melt, and irradiating this non-doped silicon single crystal with neutrons results in ³⁰ Si in the crystal. There can be utilized a phenomenon that is converted to ^{31 P} doped with phosphorus. ^{Since 30} Si is uniformly contained in a single crystal at a concentration of about 3%, this neutron irradiation is a method in which phosphorus can be doped most uniformly in both the radial and axial directions of the crystal.
The resistivity can also be controlled by adding an n-type dopant to the silicon melt. At this time, it is desirable to apply a so-called DLCZ method (Double Layered Czochralski). The DLCZ method is a method for suppressing a change in concentration in the crystal axis direction of a dopant having a small segregation coefficient such as phosphorus. In this method, in the CZ method, all of polycrystalline silicon is once dissolved in a crucible to form a silicon melt, phosphorus is added, the temperature at the bottom of the crucible is lowered, and the silicon melt is solidified upward from the bottom to form silicon. In this method, a solidified layer is formed, and a crystal is grown while the silicon solidified layer is gradually melted from the top toward the bottom, thereby keeping the dopant concentration taken into the single crystal substantially constant.
In the present invention, the change in resistivity in the crystal axis direction of the silicon single crystal can also be suppressed by adopting the DLCZ method.

Moreover, the resistivity change in the crystal axis direction of the silicon single crystal can also be suppressed by adding a predetermined amount of phosphorus and a p-type dopant having a segregation coefficient smaller than that of phosphorus. This is called a so-called double doping method, and is a method for suppressing a change in resistivity in the axial direction of a crystal doped with a dopant having a small segregation coefficient such as phosphorus. The phosphorus concentration change is compensated for by doping p-type dopant (for example, Al, Ga, In) having a segregation coefficient smaller than that of phosphorus as a counter dopant. FIG. 2 shows a change in resistivity in the crystal axis direction when only phosphorus is doped and when phosphorus and aluminum are simultaneously doped. When the resistivity specification of the wafer is 50 ± 5 Ω · cm, the yield is improved about three times by simultaneously doping with phosphorus and aluminum. The yield is the highest when the concentration ratio of aluminum to phosphorus at the upper end of the single crystal is about 50%. In the present invention, phosphorous and a p-type dopant having a segregation coefficient smaller than that of phosphorous are contained in concentrations of 1 × 10 ¹³ atoms / cm ³ or more and 1 × 10 ¹⁵ atoms / cm ³ or less, respectively. The change in resistivity in the crystal axis direction can be suppressed.

Furthermore, in the present invention, a so-called CCZ method can also be applied. This method is a method of keeping the dopant concentration taken into the single crystal substantially constant by adding polycrystalline silicon containing no dopant to the silicon melt containing phosphorus during single crystal growth.
In addition, in the case of single crystal growth in which a dopant is added to a silicon melt as in the DLCZ method or the CCZ method, the crystal rotation speed during crystal growth is rotated fast in order to suppress resistivity variation in the wafer surface. Desirably, the crystal rotation speed is 1.5 to 3 rpm in the case of growing a single crystal having a diameter of 200 mm or less, but it is desirable to rotate the crystal in the range of 0.8 to 1.5 rpm if the diameter is 300 mm or more. Normally, when the crystal rotation speed is increased, the pulling speed margin width for obtaining a grow-in defect-free crystal is narrowed, and it becomes difficult to grow a single crystal free of transition cluster defects. As will be described later, by growing a silicon single crystal by adding nitrogen, a pulling rate margin for obtaining a grow-in defect-free crystal can be secured sufficiently, and a transition crystal defect-free single crystal can be grown.

Next, nitrogen of 6 × 10 ¹² atoms / cm ³ or more and 5 × 10 ¹⁵ atoms / cm ³ or less, or 1 × 10 ¹³ atoms / cm ³ or more and 5 × 10 ¹⁴ atoms / cm ³ or less is added to the silicon single crystal. Doping facilitates the elimination of transition cluster defects. If the doping amount of nitrogen is less than the above range, COP defects, dislocation clusters, OSF regions, and Pv regions may not be completely eliminated. This is not preferable because a silicon single crystal cannot be grown.
Furthermore, the silicon single crystal is doped with nitrogen of 1 × 10 ¹⁴ atoms / cm ³ or more and 5 × 10 ¹⁵ atoms / cm ³ or less, thereby facilitating the elimination of dislocation clusters. Elimination becomes easy. If the doping amount of nitrogen is less than 1 × 10 ¹⁴ atoms / cm ³ , dislocation clusters may not be completely eliminated. If the doping amount exceeds 5 × 10 ¹⁵ atoms / cm ³ , nitrides are formed and silicon single crystals are formed. Can no longer be trained.

Moreover, according to the silicon single crystal wafer of the present invention, the pass rate of TZDB is 90% or more, and the concentration of oxygen donor generated when heat treatment is performed at 450 ° C. for 1 hour is 9.8 × 10 ¹² cm. ^-3 or less, the density of BMD generated when 800 ° C. for 4 hours and 1000 ° C. for 16 hours of two-stage heat treatment is 1 × 10 ⁵ pieces / cm ³ or less, and two-stage heat treatment is performed Since the recombination lifetime in is 100 μsec or more, the characteristics required for a silicon single crystal wafer for IGBT can be satisfied.
The pass rate of TZDB in the present invention is that a current-voltage curve is obtained at about 416 places in the whole wafer under the condition that an oxide film is formed on the wafer, the electrode area of the measurement electrode is 8 mm ² and the judgment current is 1 mA. Measured and the probability of not causing electrostatic breakdown is taken as the pass rate of TZDB. This pass rate is also called a C-mode pass rate.

The recombination lifetime is deteriorated by interstitial oxygen contained in the silicon single crystal being precipitated as SiO ₂ through a device formation process. According to the wafer of the present invention, since the interstitial oxygen concentration is not more than the above range as described above, the recombination lifetime can be 100 μsec or more.

The method for producing a silicon single crystal wafer for IGBT of the present invention is a method for producing a silicon single crystal wafer for IGBT obtained by growing a silicon single crystal by the Czochralski method, wherein the pulling rate of the silicon single crystal is increased. After growing a single crystal having an interstitial oxygen concentration of 6 × 10 ¹⁷ atoms / cm ³ or less, or 4 × 10 ¹⁷ atoms / cm ³ or less at a speed at which a dislocation cluster defect-free silicon single crystal can be pulled up The silicon single crystal can be doped with phosphorus by neutron irradiation.

Moreover, the manufacturing method of the silicon single crystal wafer for IGBT of this invention is a manufacturing method of the silicon single crystal wafer for IGBT obtained by growing a silicon single crystal by the Czochralski method, Comprising: An n-type dopant is added to a silicon melt. Is added at a rate at which the dislocation cluster defect-free silicon single crystal can be pulled up, and the interstitial oxygen concentration is 6 × 10 ¹⁷ atoms / cm ³ or less, or 4 × 10 ¹⁷ atoms / cm 3. ^Three or less single crystals can be grown.

The method for producing a silicon single crystal wafer for IGBT of the present invention is a method for producing a silicon single crystal wafer for IGBT obtained by growing a silicon single crystal by the Czochralski method, wherein phosphorus is added to the silicon melt. 2.9 × 10 ¹³ atoms / cm ³ or more and 2.9 × 10 ¹⁵ atoms / cm ³ or less, a p-type dopant having a segregation coefficient smaller than that of phosphorus, and the concentration in the crystal is 1 × 10 according to the segregation coefficient Addition of ¹³ atoms / cm ³ or more and 1 × 10 ¹⁵ atoms / cm ³ or less, and the pulling speed of the silicon single crystal including dislocation cluster defect free including the speed at which a grown-in defect free silicon single crystal can be pulled The interstitial oxygen concentration is 8.5 × 10 ¹⁷ atoms / cm ^{3 or} more at a speed at which the silicon single crystal can be pulled up. The lower single crystal can be grown.

Furthermore, in the method for producing a silicon single crystal wafer for IGBT of the present invention, nitrogen is 5 × 10 ¹² atoms / cm ³ or more to 5 × 10 ¹⁵ with respect to the silicon melt for growing the silicon single crystal by the Czochralski method. It is preferable to add at a concentration of atoms / cm ³ or less, or 1 × 10 ¹⁴ atoms / cm ³ or more and 5 × 10 ¹⁵ atoms / cm ³ or less.

  Here, as the atmospheric gas in the CZ furnace, inexpensive Ar gas is preferable, and various rare gases such as He, Ne, Kr, and Xe alone or a mixed gas thereof can be used.

  Moreover, in this invention, an inert gas can also be pulled up as atmospheric gas.

Further, the non-doped silicon single crystal after pulling is irradiated with neutrons to dope phosphorus, or an n-type dopant such as phosphorus is added to the silicon melt, thereby reducing the resistivity variation in the plane of the wafer. % Or less, preferably 5% or less. The reduction in resistivity variation can also be achieved by adding phosphorus and a p-type dopant having a segregation coefficient smaller than that of phosphorus to the silicon melt.
Further, by adding nitrogen to the silicon melt, the allowable range of the rate at which dislocation cluster defect-free silicon single crystals can be pulled can be further increased, and the dislocation clusters of the wafer can be easily eliminated.

    According to the present invention, the resistivity variation is small, and even when the IGBT manufacturing process is performed, the generation of oxygen precipitates is extremely small, the pulling time can be reduced, and the resistivity variation is small. The manufacturing method of the silicon single crystal wafer for IGBT which can be manufactured, and the silicon single crystal wafer for IGBT can be provided.

FIG. 1 is a graph showing the relationship between interstitial oxygen concentration and oxygen donor concentration after heat treatment. FIG. 2 is a graph showing the relationship between the solidification rate and the resistivity. FIG. 3 is a schematic vertical cross-sectional view of a CZ furnace used in carrying out the method for producing a silicon single crystal wafer according to the embodiment of the present invention. FIG. 4 is a schematic cross-sectional view showing the peripheral portion of the silicon single crystal wafer according to the embodiment of the present invention. FIG. 5 is a schematic cross-sectional view showing the IGBT. FIG. 6 is a graph showing the relationship among the quartz crucible rotation speed, crystal rotation speed, and interstitial oxygen concentration. FIG. 7 is a graph showing the oxygen concentration distribution in the axial direction of the silicon single crystal in the experimental example of the present invention. FIG. 8 is a graph showing the oxygen concentration distribution in the axial direction of the silicon single crystal in the experimental example of the present invention. FIG. 9 is a graph showing the relationship among the quartz crucible rotation speed, crystal rotation speed, and interstitial oxygen concentration. FIG. 10 is a graph showing the relationship between the maximum temperature, oxygen concentration, and oxygen precipitates. FIG. 11 is a graph showing an example of the COP effect exclusion heat treatment in the present invention. FIG. 12 is a graph showing the oxygen concentration distribution in the axial direction of the silicon single crystal in the experimental example of the present invention.

  Hereinafter, an embodiment of a method for producing a silicon single crystal wafer for IGBT according to the present invention will be described with reference to the drawings.

(Configuration of CZ furnace)
FIG. 3 is a longitudinal sectional view of a CZ furnace suitable for carrying out the method for manufacturing a silicon single crystal wafer for IGBT in the embodiment of the present invention.

The CZ furnace shown in FIG. 3 includes a crucible 1 disposed in the center of the chamber, a heater 2 disposed outside the crucible 1, and a magnetic field supply device 9 disposed outside the heater 2. . The crucible 1 has a double structure in which a quartz crucible 1a containing a silicon melt 3 inside is held by an outer graphite crucible 1b, and is rotated and moved up and down by a support shaft 1c called a pedestal.
A cylindrical heat shield 7 is provided above the crucible 1. The heat shield 7 has a structure in which an outer shell is made of graphite and the inside thereof is filled with graphite felt. The inner surface of the heat shield 7 is a tapered surface whose inner diameter gradually decreases from the upper end to the lower end. The upper outer surface of the heat shield 7 is a tapered surface corresponding to the inner surface, and the lower outer surface is formed in a substantially straight surface so as to gradually increase the thickness of the heat shield 7 downward.
Then, the silicon single crystal 6 can be formed by immersing the seed crystal T attached to the seed chuck 5 in the silicon melt 3 and pulling up the seed crystal T while rotating the crucible 1 and the pulling shaft 4. .

The heat shield 7 blocks the radiant heat from the heater 2 and the silicon melt 3 surface to the side surface of the silicon single crystal 6, surrounds the side surface of the growing silicon single crystal 6, and the silicon melt 3. It surrounds the surface. An example of the specification of the heat shield 7 is as follows.
The width W in the radial direction is, for example, 50 mm, the inclination θ with respect to the vertical direction of the inner surface that is the inverted truncated cone surface is, for example, 21 °, and the height H1 from the melt surface at the lower end of the heat shield 7 is 30-90 mm, for example, 50 mm. .

  Moreover, a horizontal magnetic field, a cusp magnetic field, etc. can be employ | adopted for the magnetic field supplied from the magnetic field supply apparatus 9, For example, as intensity | strength of a horizontal magnetic field, 2000-5000G (0.2T-0.5T), 3000-4000G ( 0.3T to 0.4T), more preferably 3000 to 3500G (0.30T to 0.35T), and the magnetic field center height is -150 to +100 mm, more preferably -75 to the melt surface. It is set to be within the range of +50 mm.

(Manufacturing method of silicon single crystal wafer for IGBT)
Next, a method for manufacturing a silicon single crystal wafer for IGBT using the CZ furnace shown in FIG. 3 will be described.

First, 100 to 400 kg of polycrystal of high purity silicon is charged into the crucible 1, for example, and a silicon wafer having a CVD film made of, for example, silicon nitride is charged as a nitrogen source. The nitrogen concentration in the silicon crystal is 6 × 10 ¹² atoms / cm ³ or more and 5 × 10 ¹⁵ atoms / cm ³ or less, 1 × 10 ¹³ atoms / cm ³ or more and 5 × 10 ¹⁴ atoms / cm ³ or less, or 1 × It is preferable to adjust the nitrogen concentration in the silicon melt so that the concentration is 10 ¹⁴ atoms / cm ³ or more and 5 × 10 ¹⁵ atoms / cm ³ or less. When adding the dopant for adjusting the formed resistivity, it is preferable to set the dopant concentration or not add the dopant.

  Next, the inside of the CZ furnace is made an atmosphere containing only an inert gas, and the atmospheric pressure is adjusted to about 1.3 to 26.6 kPa, or about 1.3 to 13.3 kPa.

Next, a horizontal magnetic field of, for example, 3000 G (0.3 T) is applied from the magnetic field supply device 9 so that the center height of the magnetic field is −75 to +50 mm with respect to the melt liquid surface, and the polycrystalline silicon is formed by the heater 2. Heat to make silicon melt 3.
Next, the seed crystal T attached to the seed chuck 5 is immersed in the silicon melt 3, and the crystal is pulled up while rotating the crucible 1 and the pulling shaft 4.

  Examples of the pulling condition include a pressure of 1333 to 26660 Pa in an argon atmosphere and a magnetic field strength of 3000 to 5000 Gauss. In particular, by setting the rotation speed of the quartz crucible to 1.5 rpm or less, diffusion of oxygen atoms contained in the quartz crucible into the silicon melt can be prevented, and the interstitial oxygen concentration in the silicon single crystal is reduced. be able to. Moreover, variation in resistivity within the silicon single crystal can be reduced by setting the rotation speed of the single crystal to 7.0 rpm or less. Furthermore, by setting the rotation speed of the quartz crucible to 0.2 rpm or less, diffusion of oxygen atoms contained in the quartz crucible into the silicon melt can be prevented, and the interstitial oxygen concentration in the silicon single crystal is reduced. be able to. Moreover, variation in resistivity within the silicon single crystal can be reduced by setting the rotational speed of the single crystal to 5 rpm or less.

Furthermore, quartz crucible rotation speed R1 (rpm) and crystal rotation speed R2 (rpm)
As shown by each point (R1, R2) in FIG.
Point A (0.1,1), Point B (0.1,7), Point C (0.5,7), Point I (0.7,6), Point E (1,6), Point F The silicon single crystal can be pulled up by setting the value within the range surrounded by (2, 2) and the point G (2, 1). Substantially, when the rotation speed of the quartz crucible is R1 (rpm) and the rotation speed of the crystal is R2 (rpm), the range is R1: 0.1 or more and 2 or less, R2: 1 or more and 7 or less, When R1: 0.5 or more and 0.7 or less, R2 <7-5 (R1-0.5) is satisfied, and when R1: 0.7 or more and 1 or less, R2 <6 is satisfied, and R1: 1 In the case of 2 or less, it can be set in a range satisfying R2 <6-4 (R1-1). In this case, the interstitial oxygen concentration in the single crystal can be 6.0 × 10 ¹⁷ atoms / cm ³ or less, and further 4.0 × 10 ¹⁷ atoms / cm ³ or less.
As described above, the interstitial oxygen concentration can be adjusted by rotating the quartz crucible at a predetermined rotational speed and reversely rotating the silicon single crystal at a predetermined rotational speed in the step of growing the silicon single crystal. These rotational speed conditions are obtained by experiments to be described later.

Further, the quartz crucible rotation speed R1 (rpm) and the crystal rotation speed R2 (rpm)
As shown by each point (R1, R2) in FIG.
Point A (0.1,1), point B (0.1,7), point L (0.2,7), point K (0.3,7), point J (0.5,6), Pulling up the silicon single crystal by setting the value within the range surrounded by point I (0.7,6), point H (1,5), point N (1,3), and point M (1,1) In practice, the quartz crucible rotation speed R1 (rpm) and the crystal rotation speed R2 (rpm) are in the range of R1: 0.1 or more and 2 or less, R2: 1 or more and 7 or less, provided that R1: 0. When the ratio is 3 or more and 0.5 or less, R2 <7-5 (R1-0.3) is satisfied, and when R1: 0.5 or more and 0.7 or less, R2 <6 is satisfied, and R1: 0. In the case of 0.7 or more and 1 or less, the interstitial oxygen concentration in the single crystal is set to 6.0 × 10 ¹⁷ atoms / cm by setting R2 <6-3.4 (R1-0.7). ³ or less, and more, 3. × ¹⁰ 17 atoms / cm ³ can grow a silicon single crystal having a low oxygen concentration than as follows.

Further, the quartz crucible rotation speed R1 (rpm) and the crystal rotation speed R2 (rpm)
As shown by each point (R1, R2) in FIG.
Point A (0.1,1), point B (0.1,7), point L (0.2,7), point Q (0.3,6), point J (0.5,6), The silicon single crystal is pulled up by setting the value within the range surrounded by the points P (0.7, 5), N (1, 3), and M (1, 1). The rotation speed R1 (rpm) and the crystal rotation speed R2 (rpm) are in the range of R1: 0.1 to 1 and R2: 1 to 7.0, provided that R1: 0.2 to 0.3. In this case, R2 <7-10 (R1-0.2) is satisfied, and when R1: 0.3 to 0.5, R2 <6 is satisfied, and R1: 0.5 to 0.7. In this case, R2 <6-5 (R1-0.5) is satisfied, and when R1: 0.7 or more and 1 or less, R2 <5-6.7 (R1-0.7) is set in a range satisfying The interstitial oxygen concentration in the single crystal. When the degree is 3.0 × 10 ¹⁷ atoms / cm ³ or less and 0.1 or more, a silicon single crystal having a lower oxygen concentration can be grown.

  By setting the above pulling conditions, the interstitial oxygen concentration in the silicon single crystal can be made smaller than the above range, thereby preventing the generation of oxygen donors in the IGBT manufacturing process. If the interstitial oxygen concentration exceeds the above range, oxygen precipitates and oxygen donors are generated in the IGBT manufacturing process, and the characteristics of the IGBT are changed.

Next, the formed single crystal silicon to which the dopant for adjusting the resistivity is not added is irradiated with a neutron beam. By irradiation with this neutron beam, a part of silicon atoms is converted into phosphorus, whereby the single crystal silicon can be uniformly doped with phosphorus, and single crystal silicon with a uniform resistivity can be obtained. The irradiation conditions of the neutron beam may be, for example, irradiation for about 80 hours while rotating the crystal at about 2 rpm at a position where the neutron beam flux is 3.0 × 10 ¹² pieces / cm ² / s ⁻¹ . The silicon ingot thus irradiated with the neutron beam has a resistivity of about 48 Ωcm to 52 Ωcm.

  Instead of neutron irradiation, n-type (P, As, Sb, etc.) dopant may be added to the silicon melt in advance. However, since the segregation coefficient is small, the length direction of the silicon single crystal The resistivity changes greatly. In order to prevent such a change in n-type dopant concentration, for example, the above-described DLCZ method, double doping method, or CCZ method may be employed. Furthermore, in order to suppress variation in resistivity within the wafer plane, the crystal rotation speed during single crystal growth may be set to 5.0 rpm or more and 7.0 rpm or less.

Next, a wafer is cut out from the single crystal silicon, and lapping, etching, grinding, polishing, etc. are performed as necessary, and heat treatment such as RTA is performed as necessary.
When lapping, in order to prevent cracking of the wafer, beveling is performed to form a surface chamfered portion on the peripheral portion of the wafer surface, and a backside chamfered portion is formed on the peripheral portion of the back surface of the wafer. It is preferable. FIG. 4 shows a cross section of the wafer peripheral portion after completion of wafer processing.

As shown in FIG. 4, the front surface 22 of the wafer is provided with a main surface 23 that is a flat surface and a surface chamfered portion 24 formed at the peripheral edge. Further, the back surface 26 is provided with a main surface 27 which is a flat surface and a back surface side chamfered portion 28 formed at the peripheral edge. The front side chamfered portion 24 has a width A1 in the direction from the peripheral edge 29 inward in the wafer radial direction, and a width A2 in the direction from the peripheral edge 29 in the backside chamfered portion 28 inward in the wafer radial direction. It is narrowed. The width A1 of the surface chamfer 24 is preferably in the range of 50 μm to 200 μm. Further, the width A2 of the back side chamfer 28 is preferably in the range of 200 μm to 300 μm.
Further, the front side chamfer 24 has the first inclined surface 11 that is inclined with respect to the main surface 23 of the front surface 22, and the back side chamfered portion 28 is the first inclined surface 11 that is inclined with respect to the main surface 27 of the rear surface 26. Two inclined surfaces 12 are provided. The inclination angle θ1 of the first inclined surface 11 is preferably in the range of 10 ° to 50 °, the inclination angle θ2 of the second inclined surface 12 is preferably in the range of 10 ° to 30 °, and θ1 ≦ θ2 is satisfied. preferable.
A first curved surface 13 is provided between the first inclined surface 11 and the peripheral edge 29 to connect them. A second curved surface 14 is provided between the second inclined surface 12 and the peripheral edge 29 to connect them. The range of the radius of curvature R1 of the first curved surface 13 is preferably in the range of 80 μm to 250 μm, and the range of the radius of curvature R2 of the second curved surface 14 is preferably in the range of 100 μm to 300 μm.

  Furthermore, COP influence exclusion heat treatment is performed on such a wafer at a temperature lowering rate of 1 to 5 ° C./min for 1 to 10 hours at a temperature of 1050 ° C. or more and below the melting point of silicon. Before and after the heat treatment, dislocation clusters are excluded in the entire crystal diameter direction, and COP is eliminated by this COP influence exclusion heat treatment, or the size and density are set so as not to affect the device. Is possible. The COP influence exclusion heat treatment may be performed under any temperature condition that can eliminate COP. However, it is preferable that the treatment temperature and treatment time that affect the diffusion rate of pores, and the temperature lowering rate are set in the above ranges. In particular, it is more preferable to set the temperature conditions, the processing time, and the heating / cooling rate as shown in FIG. Specifically, it is charged into a furnace heated to 700 ° C. at an entry speed of 1 to 3 cm / min, preferably at an entry speed of 2 cm / min, from which the oxygen concentration is 1 to 5%, preferably 3%. In this state, the temperature is increased from 1050 to 1120 ° C., preferably up to 1100 ° C. at a temperature increase rate of 3 to 7 ° C./min, preferably 5 ° C./min, and further, the processing temperature is 1130 to 1200 ° C., preferably up to 1150 ° C. The temperature is raised at 1 ° C./min. After the treatment temperature reaches 1150 ° C., the oxygen concentration is set to 50% or more, preferably 100%, and kept in this state for 2 to 10 hours, preferably 3.5 hours. The temperature can be lowered to 900 ° C. at 2 ° C./min, preferably 2 ° C./min, and taken out at a take-out speed of 1 to 3 cm / min, preferably 2 cm / min. As the heat treatment furnace, it is preferable to use a batch furnace capable of processing a plurality of sheets simultaneously for processing efficiency, but a single wafer furnace is also possible. Further, the treatment atmosphere may be an oxidation atmosphere, and an atmosphere containing not only oxygen but also other inert gas, nitrogen, or the like may be used. Further, the COP effect eliminating heat treatment can be not performed on a wafer having a Pv / Pi region, a wafer having a low oxygen concentration, or the like in which the influence of COP is not a concern due to process conditions in device processing.

Next, a polysilicon layer is formed on one side of the wafer. Since the silicon single crystal wafer of this embodiment has an extremely low interstitial oxygen concentration, the gettering effect due to oxygen precipitates cannot be expected. Therefore, it is necessary to form a polycrystalline silicon layer as a gettering layer on the back surface side to remove heavy metal contamination in the IGBT manufacturing process. Further, by forming the polycrystalline silicon layer on the back surface side, it is possible to prevent the occurrence of slip or the like and prevent the propagation of the slip to the wafer surface side. The thickness of the polysilicon layer is preferably in the range of 50 nm to 2000 nm. If the thickness is 50 nm or more, the gettering effect and the effect of suppressing the occurrence of slip can be sufficiently exerted, and if the thickness is 2000 nm or less, warpage of the wafer can be prevented.
Thus, the silicon single crystal wafer for IGBT of this embodiment can be manufactured.

According to the above manufacturing method, the variation in resistivity within the surface of the wafer can be 8% or less or 5% or less, and the oxygen concentration is 6 × 10 ¹⁷ atoms / cm ³ or less or 4 × 10 ¹⁷ atoms / cm. Since the oxygen concentration is limited to a low oxygen concentration of ³ cm ³ or less, it is possible to reliably prevent the occurrence of leakage defects due to the variation in resistivity due to oxygen donors and the formation of oxygen precipitates.

Also, the silicon single crystal after pulling is irradiated with neutrons to dope phosphorus, or an n-type dopant such as phosphorus is added to the silicon melt to reduce the resistivity variation within 5% of the wafer surface. Can be. The reduction in resistivity variation can also be achieved by adding phosphorus and a p-type dopant having a segregation coefficient smaller than that of phosphorus to the silicon melt.
Further, by adding nitrogen to the silicon melt, the allowable range of the speed at which dislocation cluster defect-free silicon single crystals can be pulled can be further increased, and the elimination of COP defects and dislocation clusters in the wafer is facilitated.

(Silicon single crystal wafer for IGBT)
In the silicon single crystal wafer manufactured as described above, COP defects and dislocation clusters are eliminated in the entire crystal diameter direction, and the interstitial oxygen concentration is 6 × 10 ¹⁷ atoms / cm ³ or less. The variation in resistivity is 8% or less. The resistivity itself is about 48 Ω · cm to 52 Ω · cm. Further, the silicon single crystal wafer is doped with 6 × 10 ^{12 to} 5 × 10 ¹⁵ atoms / cm ³ of nitrogen.
Furthermore, in the silicon single crystal wafer for IGBT of this embodiment, the pass rate of TZDB at a breakdown electric field of 8 MV / cm is 90% or more, and the concentration of oxygen donor that precipitates when heat treatment is performed at 450 ° C. for 1 hour. Is 9.8 × 10 ¹² cm ⁻³ or less, and the density of BMD generated when two-stage heat treatment is performed at 800 ° C. for 4 hours and 1000 ° C. for 16 hours is 1 × 10 ⁵ pieces / cm ³ or less. The recombination lifetime when the two-step heat treatment is performed is 100 μsec or more.
Furthermore, in the silicon single crystal wafer of this embodiment, the LPD density of 0.1 μm size or more on the wafer surface is 0.1 piece / cm ² or less, and the light etching defect density is 1 × 10 ³ pieces / cm ^2. It is as follows. Furthermore, in the silicon single crystal wafer of this embodiment, a polycrystalline silicon layer having a thickness of 50 nm or more and 2000 nm or less is formed on the back surface side, and a surface chamfered portion is formed on the peripheral edge of the wafer surface. A back side chamfer is formed on the peripheral edge of the back side.

According to the silicon single crystal wafer for IGBT of the present embodiment, COP defects and dislocation clusters are eliminated in the entire crystal diameter direction. Therefore, when the gate oxide film is formed on the wafer surface in the IGBT manufacturing process, COP defects are not generated. The gate oxide film is not taken in, and the GOI is not deteriorated.
Furthermore, since the OSF region is eliminated and there is no region where the density of OSF is 10 / cm ² or more, COP defects are taken into the gate oxide film when the gate oxide film is formed on the wafer surface in the IGBT manufacturing process. The GOI is not deteriorated. In addition, leakage current in the integrated circuit can be prevented. Furthermore, the yield rate can be 90% or more.

Furthermore, since COP defects and dislocation clusters are eliminated in the entire crystal diameter direction, the wafer can be suitably used as an IGBT wafer, which is an element that uses the wafer in the vertical direction. That is, since COP defects and dislocation clusters are eliminated, the quality of the bulk of the wafer becomes excellent, and the recombination lifetime, which is an important characteristic for an IGBT wafer, can be improved.
Furthermore, since the interstitial oxygen concentration is below the above range, the concentration of oxygen donors generated after the heat treatment of the wafer can be suppressed to 9.8 × 10 ¹² ions / cm ³ or less, and the resistivity of the wafer before and after the heat treatment can be reduced. The change can be prevented and the quality of the silicon single crystal wafer can be stabilized.
Moreover, according to the silicon single crystal wafer of the present invention, since the variation in resistivity within the wafer surface is 5% or less, the quality of the silicon single crystal wafer can be stabilized.
Furthermore, 6 × 10 ^{12 to} 5 × 10 ¹⁵ atoms / cm ³ , or 1 × 10 ^{14 to} 5 × 10 ¹⁵ atoms / cm ³ , 1 × 10 ^{13 to} 5 × 10 ¹⁴ atoms / cm ^{3 are formed on} the silicon single crystal. Doping with nitrogen facilitates the elimination of COP defects and dislocation clusters. If the nitrogen doping amount is less than the above range, COP defects and dislocation clusters may not be completely eliminated. If the nitrogen doping amount exceeds the above range, nitrides are generated and a silicon single crystal cannot be grown.
In addition, the pass rate of TZDB is 90% or more, the concentration of oxygen donor generated when heat treatment is performed at 450 ° C. for 1 hour, is 9.8 × 10 ¹² cm ⁻³ or less, and 4 hours at 800 ° C. The density of BMD deposited when performing a two-step heat treatment at 1000 ° C. for 16 hours is 1 × 10 ⁵ pieces / cm ³ or less, and the recombination lifetime when performing the two-step heat treatment is 100 μsec or more. Therefore, the characteristics required for a silicon single crystal wafer for IGBT can be satisfied.

(Experimental example 1)
Silicon ingots having various interstitial oxygen concentrations were produced by the CZ method. Specifically, the polycrystalline silicon lump was put into a quartz crucible, and the polycrystalline silicon lump was heated in an argon atmosphere to obtain a silicon melt. Phosphorus was added as a dopant to the silicon melt. The amount of phosphorus added was adjusted so that the resistivity of the silicon single crystal was 65 Ω · cm. Next, the seed crystal is immersed in the silicon melt while supplying a horizontal magnetic field of 3000 G (0.3 T) from the magnetic field supply device so that the magnetic field center height is −75 to +50 mm with respect to the melt surface. Then, while rotating the seed crystal and the quartz crucible, the seed crystal was gradually pulled up to grow a single crystal under the seed crystal. Note that the ratio V / G when the growth rate (pulling rate) of the single crystal is V (mm / min) and the temperature gradient of 1350 ° C. from the melting point during single crystal growth is G (° C./min) is 0.00. It set to about 185 and V was set to 0.49 mm / min. Thus, the single crystal silicon ingot pulled up under the pulling conditions of Conditions 1 to 4 was manufactured. The interstitial oxygen concentration in the silicon ingot was controlled by adjusting the rotation speed of the quartz crucible. In condition 4, a silicon wafer with a silicon nitride film was introduced into the silicon melt, so that 4.1 × 10 ¹⁴ atoms / cm ³ of nitrogen was doped into the silicon single crystal.

  Next, the pulled single crystal silicon ingot was sliced to cut out the wafer. The cut wafer was subjected to surface treatment such as lapping and etching. In this way, a silicon single crystal wafer having a diameter of 200 mm and a thickness of 0.75 mm was manufactured.

The obtained silicon single crystal wafer was measured for interstitial oxygen concentration and evaluated for variations in resistivity within the wafer surface. The interstitial oxygen concentration was measured according to the Fourier transform infrared spectrophotometry standardized by ASTM F-121 (1979). In addition, the resistivity variation is measured at a total of three locations, the wafer center, the middle position between the wafer center and outer periphery, and the position 5 mm from the wafer outer periphery. A value was selected and calculated according to the formula “(maximum value−minimum value) × 100 / minimum value”. The results are shown in Table 1.
Further, Table 1 shows the allowable range of the pulling speed. This allowable width is obtained by gradually reducing the pulling rate of the crystal and vertically dividing the grown crystal in the growth direction and observing the Grown-in defect distribution including dislocation cluster defects by the X-ray topography method after Cu decoration. This is a pulling-up speed margin that can determine the dislocation cluster region by measuring the COP region and the light etching defect and can eliminate the dislocation cluster in the entire crystal diameter direction.

As shown in Table 1, it was found that the interstitial oxygen concentration can actually be reduced by reducing the crucible rotation speed from 7 rpm to 1 rpm (condition 1 → conditions 2 to 4). However, in conditions 1 and 2, although the crystal rotation speed was slow, the allowable range of the pulling speed could be secured to some extent, but the variation in resistivity was very large.
Further, comparing conditions 2 and 3, in condition 3, the variation in resistivity was reduced by increasing the rotation speed of the crystal, but the allowable range of the pulling speed was greatly reduced. This is presumably because the solid-liquid interface shape between the silicon melt and the single crystal changed due to the increase in the rotation speed of the single crystal.
Furthermore, with respect to the condition 4, the allowable range of the pulling rate was increased by doping nitrogen with respect to the condition 3, but the variation in resistivity was also increased. This is considered to be because the convection state of the silicon melt was changed by nitrogen doping.

  From the above, under the pulling conditions of Conditions 1 to 4, it was difficult to simultaneously achieve reduction in interstitial oxygen concentration, reduction in variation in resistivity, and increase in the allowable range of pulling speed.

(Experimental example 2)
Silicon ingots having various interstitial oxygen concentrations were produced by the CZ method. Specifically, the polycrystalline silicon lump was put into a quartz crucible, and the polycrystalline silicon lump was heated in an argon atmosphere to obtain a silicon melt. Next, the seed crystal is immersed in the silicon melt while supplying a horizontal magnetic field of 3000 G (0.3 T) from the magnetic field supply device so that the magnetic field center height is −75 to +50 mm with respect to the melt surface. Then, while rotating the seed crystal and the quartz crucible, the seed crystal was gradually pulled up to grow a single crystal under the seed crystal. The growth rate (pulling rate) of the single crystal is V (mm / min), and the ratio V / G when the temperature gradient G (° C./min) is 1350 ° C. from the melting point during single crystal growth is 0.185. The V was set to 0.49 mm / min. In this manner, single crystal silicon ingots pulled under the pulling conditions 5 to 14 were manufactured.

The rotation speed of the quartz crucible was 2 rpm under all conditions, and the rotation speed of the single crystal was 20 rpm under all conditions. Furthermore, in conditions 5 and 6, a silicon wafer with a silicon nitride film was introduced into the silicon melt, and nitrogen was doped into the silicon single crystal. Moreover, in conditions 7-11, hydrogen gas was introduce | transduced into argon gas atmosphere and it pulled up on the conditions of hydrogen partial pressure 30-400 Pa. Further, under conditions 12 to 14, nitrogen doping and hydrogen gas introduction were performed simultaneously. Furthermore, in conditions 7-10 and 12-13, the resistivity is adjusted by adding phosphorus to the silicon melt, and in other conditions, neutrons are applied to the single crystal silicon pulled up in the same manner as in Experimental Example 1. Irradiated with rays and doped with phosphorus. Irradiation with neutron beams was performed under the condition of irradiation with a bundle of 3.0 × 10 ¹² particles / cm ² / s for 80 hours. In this way, the resistivity of the silicon single crystal was adjusted to 65 Ω · cm.

  Thereafter, a single crystal silicon ingot was sliced to cut out a wafer. The cut wafer was subjected to surface treatment such as lapping and etching. In this way, a silicon single crystal wafer having a diameter of 200 mm and a thickness of 0.75 mm was manufactured.

  For the obtained silicon single crystal wafer, the interstitial oxygen concentration was measured in the same manner as in Experimental Example 1, and the variation in resistivity within the wafer surface was evaluated. The results are shown in Table 2. Table 2 also shows the nitrogen concentration in the wafer, the hydrogen partial pressure in the atmosphere of the CZ furnace, and the conditions for the dopant introduction method. Further, similarly to Experimental Example 1, the allowable range of the pulling speed is shown at the same time.

As shown in Tables 1 and 2, the variation in resistivity deteriorated by nitrogen doping in condition 4 was improved by performing phosphorous doping by neutron irradiation as shown in conditions 5 and 6, but the allowable range of pulling rate Was not enough.
In addition, the allowable range of the pulling rate that was reduced by increasing the rotation speed of the crystal in Condition 3 was improved by introducing hydrogen into the atmosphere as shown in Conditions 8-10. As in Conditions 8 to 10, while introducing a predetermined amount of hydrogen and controlling the crucible rotation speed and the single crystal rotation speed, the interstitial oxygen concentration is reduced, the resistivity variation is reduced, and the pulling speed is increased. It has been found that an increase in the allowable range can be realized simultaneously.
Also, the variation in resistivity increased by nitrogen doping in condition 4 was improved by introducing hydrogen into the atmosphere as shown in conditions 12 and 13. This is considered to be because the change in the convection state of the silicon melt caused by nitrogen doping was suppressed by introducing hydrogen. Moreover, in conditions 12 and 13, the allowable range of the pulling rate could be expanded as compared with the case of nitrogen doping alone (conditions 5 to 6) and hydrogen introduction alone (conditions 7 to 11).
Furthermore, with respect to these conditions 12 and 13, in the condition 14 in which phosphorus was introduced by neutron irradiation, the variation in resistivity was further reduced.

(Experimental example 3)
A silicon ingot having an interstitial oxygen concentration was produced by the CZ method. Specifically, after a wafer with a nitride film is introduced into a quartz crucible so that the nitrogen concentration is 8 × 10 ¹³ atoms / cm ³ at the top of the single crystal straight body, 110 kg of polycrystalline silicon lump is placed in the quartz crucible. The polycrystalline silicon lump was heated in an argon atmosphere to obtain a silicon melt.
Next, a dopant for adjusting electric resistivity was not added to the silicon melt, and a horizontal magnetic field of 3500 G (0.35 T) was applied to the silicon melt from a magnetic field supply device.
Next, the seed crystal is immersed in the silicon melt, and the seed crystal is gradually rotated while rotating the seed crystal (single crystal) at a rotational speed of 5 rpm and the quartz crucible at a rotational speed of 0.1 rpm in opposite directions. A silicon single crystal having a diameter of 8 inches and a straight body portion of 1200 mm was grown under the seed crystal. Note that the ratio V / G when the single crystal growth rate (pulling rate) is V (mm / min) and the temperature gradient G (° C./min) is 1350 ° C. from the melting point during single crystal growth is 0.185. The V was set to 0.49 mm / min.
In the silicon single crystal grown as described above, the change in oxygen concentration at the crystal center in the single crystal pulling axis direction was measured. The result is shown in FIG.

From this result, in the silicon single crystal grown as described above, the portion having an oxygen concentration of 1.4 × 10 ¹⁷ to 4 × 10 ¹⁷ atoms / cm ³ (oldASTM) or less and containing neither COP nor dislocation clusters is 800 mm. A low-oxygen silicon single crystal of 4 × 10 ¹⁷ atoms / cm ³ or less could be obtained over a wide range.

(Experimental example 4)
Growing a single crystal of silicon under the same conditions as in Example 3 except that nitrogen was not added and the gas atmosphere in the furnace was changed to a mixed gas atmosphere of 94% argon gas and 6% hydrogen gas under the conditions of Experimental Example 3. Went. FIG. 8 shows the result of measuring the change in oxygen concentration at the center of the crystal in the single crystal pulling axis direction.

From this result, the portion of the silicon single crystal grown above having an oxygen concentration of 1.4 × 10 ^{17 to} 4.0 × 10 ¹⁷ atoms / cm ³ and containing neither COP nor dislocation clusters is 1050 mm, and it is 4 × A low-oxygen silicon single crystal of 10 ¹⁷ atoms / cm ³ or less was obtained.

(Experimental example 5)
Next, each single crystal silicon pulled up in the same manner as in Experimental Example 3 and Experimental Example 4 was irradiated with neutrons to be doped with phosphorus. Irradiation with neutron beams was performed under the condition of irradiation with a bundle of 3.0 × 10 ¹² particles / cm ² / s for 80 hours. In this way, the resistivity of each silicon single crystal was adjusted to 65 Ω · cm.
Thereafter, each single crystal silicon ingot was sliced to cut out the wafer. The cut wafer was subjected to surface treatment such as lapping and etching. In this way, a silicon single crystal wafer having a diameter of 200 mm was manufactured.
About each obtained silicon single crystal wafer, the dispersion | variation in the resistivity in the surface of a wafer surface was evaluated. For resistivity variations, measure the resistivity at a total of three locations, the wafer center, the middle position between the wafer center and the circumference, and the position 5 mm from the wafer circumference. The value was selected and calculated by the formula “(maximum value−minimum value) × 100 / minimum value”.
As a result, it was confirmed that the variation in resistivity of each silicon wafer was 8% or less (5% or less). This is because, in this example, no dopant was added at the stage of silicon single crystal growth, so even if the crystal rotation speed was lowered, the resistivity distribution in the silicon single crystal was not affected and the growth was completed. This is because the silicon single crystal is doped with phosphorus by neutron irradiation.

(Experimental example 6)
Next, investigation was made on the condition range of the crucible rotation speed and the crystal rotation speed in which the oxygen concentration in the wafer was 4 × 10 ¹⁷ atoms / cm ³ or less.
Specifically, under the conditions of Example 1, the number of revolutions of the crucible is set to six levels of 0.1 rpm, 0.2 rpm, 0.3 rpm, 0.7 rpm, 1.0 rpm, and 2.0 rpm, and the number of revolutions of the crystal is set. The silicon single crystal was grown at 8 levels of 1 to 8 rpm, and the oxygen concentration of the wafer cut out from a position of 200 mm from the top of the straight body portion of each silicon single crystal was measured. The interstitial oxygen concentration was measured according to the Fourier transform infrared spectrophotometry standardized by ASTM F-121 (1979). The results are shown in Table 3 and FIG.

As is clear from Table 3 and FIG. 9, when the crucible rotation speed is 0.2 rpm or less and the crystal rotation speed is 5 rpm or less, the oxygen concentration in the wafer is 6 × 10 ¹⁷ atoms / cm ³ or less ( Or 4 × 10 ¹⁷ atoms / cm ³ or less).

(Experimental example 7)
Next, the relationship between the maximum temperature of the heat treatment performed in the IGBT device process, the oxygen concentration in the wafer, and the density of oxygen precipitates (BMD: Bulk Micro Defect) formed in the wafer was investigated.
First, an n-type (50 Ω · cm) wafer having a diameter of 200 mm, which does not include COP and dislocation clusters and has an oxygen concentration in the range of 1.5 to 7.6 × 10 ¹⁷ atoms / cm ³ near the center of the wafer Used, heat treatment simulating IGBT device process heat treatment as shown in Table 4 was performed. At this time, the maximum temperature was changed from 1100 ° C to 1225 ° C.

Then, the wafer was cleaved, and the BMD density in the wafer was measured with an infrared tomograph (Mitsui Metal Mining MO441). From the comparison with a transmission electron microscope (TEM), the lower limit of the BMD size detectable by MO441 is 20 nm.
When a volume of 10 μm (beam diameter) × 260 μm (depth range) × 4000 μm (radial scan distance) is measured near the center of the wafer and no BMD is detected, that is, a BMD density of 20 nm or more the case was less than 1 × 10 ⁵ cells / cm ³ OK, the case above BMD density 20nm seemed 1 × 10 ⁵ / cm ³ or more was judged as NG. The result is shown in FIG.
As is clear from the figure, if the oxygen concentration in the wafer is 6 × 10 ¹⁷ atoms / cm ³ or less, the BMD density of 20 nm or more after the heat treatment simulating the heat treatment in the IGBT manufacturing process is 1 × 10 ⁵ pieces / cm 3. It can be controlled to be less than ³ . As a result, it is possible to reduce leakage defects caused by BMD.

(Experimental example 8)
A silicon ingot having an interstitial oxygen concentration was produced by changing the conditions from C1 to C5 as shown in Table 5 by the CZ method. Specifically, after selecting a wafer with a nitride film and no nitrogen input so that the nitrogen concentration is 8 × 10 ¹³ atoms / cm ³ at the top of the single crystal straight body in a quartz crucible, polycrystalline silicon is selected. 110 kg of lump was put into a quartz crucible, and the polycrystalline silicon lump was heated in an argon atmosphere to obtain a silicon melt.
Next, without adding a dopant for adjusting the electrical resistivity to the silicon melt, the center position of the horizontal magnetic field of 3500 G (0.35 T) from the magnetic field supply device is −3 with respect to the silicon melt. To +153 mm, that is, the magnetic field center position was applied above the silicon melt surface.
Next, the seed crystal is immersed in the silicon melt, and the seed crystal (single crystal) is rotated at a rotation speed of 5 to 8 rpm and the rotation speed of the quartz crucible at a rotation speed of 0.1 rpm in the opposite directions. The silicon single crystal having a diameter of 8 inches and a straight body length of 1200 mm was grown under the seed crystal. Note that the ratio V / G when the single crystal growth rate (pulling rate) is V (mm / min) and the temperature gradient of 1350 ° C. from the melting point during single crystal growth is G (° C./min) is 0.00. It was set to about 2, and V was set to 0.52 mm / min.
In the silicon single crystal grown as described above, the change in oxygen concentration at the crystal center in the single crystal pulling axis direction was measured. The results are shown in FIG. 12 as C1 to C5.

From this result, among the silicon single crystals grown as described above, a low oxygen silicon single crystal having an oxygen concentration of 6 × 10 ¹⁷ atoms / cm ³ (oldASTM) or less and containing no dislocation clusters and capable of eliminating the influence of COP by annealing is obtained. I was able to.

3 ... Silicon melt 6 ... Silicon single crystal T ... Seed crystal

Claims (14)

A method for producing a silicon single crystal wafer for IGBT obtained by growing a silicon single crystal by the Czochralski method,
The magnetic field strength is 2000 gauss or more, the quartz crucible rotation speed is 1.5 rpm or less, the crystal rotation speed is 7.0 rpm or less,
The silicon for IGBT is characterized by growing a single crystal having an interstitial oxygen concentration of 6 × 10 ¹⁷ atoms / cm ³ or less at a speed at which a silicon single crystal free from transition cluster defects can be pulled up. Manufacturing method of single crystal wafer. A method for producing a silicon single crystal wafer for IGBT obtained by growing a silicon single crystal by the Czochralski method,
The magnetic field strength is 2000 gauss or more,
Quartz crucible rotation speed R1 (rpm) and crystal rotation speed R2 (rpm)
As shown by each point (R1, R2) in FIG.
Point A (0.1,1), Point B (0.1,7), Point C (0.5,7), Point I (0.7,6), Point E (1,6), Point F (2, 2), set to a value within the range surrounded by point G (2, 1),
A silicon for IGBT characterized by growing a single crystal having an interstitial oxygen concentration of 6 × 10 ¹⁷ atoms / cm ³ or less at a speed at which a silicon single crystal free from dislocation cluster defects can be pulled up. Manufacturing method of single crystal wafer. When a silicon single crystal is grown by the Czochralski method, an n-type dopant is added to the silicon melt, or phosphorus is added to the silicon melt at 2.9 × 10 ¹³ atoms / cm ³ or more to 2.9 × 10 ¹⁵ atoms. / cm ³ or less, the Do p-type dopant small segregation coefficient than the phosphorus, so that the concentration in the crystal in accordance with the segregation coefficient becomes 1 × ¹⁰ 15 atoms / cm ³ or less 1 × ¹⁰ 13 atoms / cm ³ or more 3. The method for manufacturing a silicon single crystal wafer for IGBT according to claim 1, wherein phosphorus is doped by adding neutron to the silicon single crystal after being pulled or by neutron irradiation. A method for producing a silicon single crystal wafer for IGBT obtained by growing a silicon single crystal by the Czochralski method,
A magnetic field having a magnetic field strength of 2000 Gauss or more is applied to a quartz crucible containing a silicon melt to which a dopant for adjusting electrical resistivity in a silicon single crystal is not added, and the rotation speed of the quartz crucible is 1.5 rpm or less and The growth rate of the silicon single crystal under growth was set to 7.0 rpm or less, and the silicon single crystal having an oxygen concentration of 6 × 10 ¹⁷ atoms / cm ³ or less was grown. A method for producing a silicon single crystal wafer for IGBT, characterized by doping with phosphorus.   5. The method for producing a silicon single crystal wafer for IGBT according to claim 4, wherein the pulling speed of the silicon single crystal is set to a pulling speed capable of eliminating COP defects and dislocation clusters in the entire crystal diameter direction. 6. The silicon single crystal wafer for IGBT according to claim 1, wherein nitrogen is added to the silicon single crystal at a concentration of 6 × 10 ¹² atoms / cm ³ or more and 5 × 10 ¹⁵ atoms / cm ³ or less. Manufacturing method.   The method for producing a silicon single crystal wafer for IGBT according to claim 1, wherein a polycrystalline silicon layer having a thickness of 50 nm or more and 1000 nm or less is formed on the back side of the silicon single crystal wafer.   8. The silicon single crystal for IGBT according to claim 1, wherein the silicon wafer sliced from the silicon single crystal is subjected to COP effect exclusion heat treatment that is performed at 1050 ° C. or higher and below the melting point of silicon for 1 to 10 hours. Wafer manufacturing method. It is manufactured by the manufacturing method according to any one of claims 1 to 8,
Dislocation clusters are eliminated in the entire crystal diameter direction, the interstitial oxygen concentration is 6 × 10 ¹⁷ atoms / cm ³ or less, and the variation in resistivity within the wafer surface is 8% or less. Silicon single crystal wafer for use.   When the silicon single crystal is grown by the Czochralski method, it is grown at a pulling speed capable of pulling up a silicon single crystal free of transition cluster defects, and the silicon single crystal after pulling is irradiated with neutrons The silicon single crystal wafer for IGBT according to claim 9, wherein the single-crystal wafer for IGBT according to claim 9 is doped with phosphorus.   When the silicon single crystal is grown by the Czochralski method, the silicon single crystal is grown at a pulling speed capable of pulling up a transition cluster defect-free silicon single crystal from a silicon melt doped with an n-type dopant. The silicon single crystal wafer for IGBT according to claim 9, wherein the silicon single crystal wafer is for IGBT. The phosphorus and the p-type dopant having a segregation coefficient smaller than that of the phosphorus are included in a concentration of 1 × 10 ¹³ atoms / cm ³ or more and 1 × 10 ¹⁵ atoms / cm ³ or less, respectively. A silicon single crystal wafer for IGBT as described in 1. above. The IGBT according to claim 9, wherein the LPD density on the wafer surface is 0.1 piece / cm ² or less and the light etching defect density is 1 × 10 ³ pieces / cm ² or less. Silicon single crystal wafer for use.   14. The silicon single crystal wafer for IGBT according to claim 9, wherein a polycrystalline silicon layer having a thickness of 50 nm or more and 1000 nm or less is formed on the back surface side.

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