JPWO2009025339A1 - Silicon single crystal wafer for IGBT and manufacturing method of silicon single crystal wafer for IGBT - Google Patents

Abstract

It is possible to expand the pulling speed margin, improve the leakage current, and manufacture a wafer with a small variation in resistivity. A silicon single crystal for IGBT composed of a silicon single crystal grown by the Czochralski method In the wafer, COP defects, dislocation clusters, and OSF regions are eliminated in the entire crystal diameter direction, the interstitial oxygen concentration is 8.5 × 10 17 atoms / cm 3 or less, and the resistivity variation within the wafer surface is 5 An IGBT silicon single crystal wafer characterized by being% or less is employed.

Description

The present invention relates to an IGBT silicon single crystal wafer used for manufacturing an insulated gate bipolar transistor (IGBT) and a method for manufacturing an IGBT silicon single crystal wafer.
This application claims priority on August 21, 2007 based on Japanese Patent Application No. 2007-215334 for which it applied to Japan, and uses the content for it here.

Insulated Gate Bipolar Transistor (hereinafter referred to as IGBT) is a gate voltage-driven switching element suitable for controlling high power, and is used for inverters in trains, hybrid vehicles, air conditioners, refrigerators, etc. It has been. As shown in FIGS. 5A to 5C, the IGBT is provided with three electrodes, ie, an emitter E, a collector C, and a gate G. The gate is formed on the surface side of the element via an insulating oxide film SiO _2. The current between the emitter E on the device surface side and the collector C on the back surface side is controlled by the applied voltage.
As described above, since the IGBT is an element that controls current with a gate insulated by an oxide film, the quality of the gate oxide film (Gate Oxide Integrity, hereinafter referred to as GOI) is important. If a defect is included in the silicon single crystal wafer, the defect is taken into the gate oxide film and causes a dielectric breakdown of the oxide film.

Further, the IGBT is not an element that uses only the vicinity of the surface of the wafer in the horizontal direction like an LSI such as a memory, but is an element that uses the wafer in the vertical direction (thickness direction) as shown in FIGS. 5A to 5C. Properties are affected by the bulk quality of the wafer. In particular, recombination lifetime and resistivity are important qualities. Since the recombination lifetime is reduced by crystal defects in the substrate, it is necessary to control so that no crystal defects occur even after the device process. Regarding the resistivity, uniformity and stability are required. It is important that it is uniform not only in the plane of the wafer but also between the wafers, that is, in the length direction of the silicon ingot, and does not change even after the device thermal process.
If a plurality of received elements on the wafer plane, that is, a plurality of elements are provided in parallel, if the resistivity differs between these elements, a large current concentrates on the low resistivity element and breaks. Therefore, the uniformity and stability of the resistivity are important. As described above, when a plurality of elements are miniaturized in parallel, a large current is concentrated due to the difference in resistivity, and the current is concentrated on a specific element, resulting in damage. It is important that the process does not change.

Further, as shown in FIG. 5A, as a substrate for a so-called punch through (hereinafter referred to as PT) type IGBT in which the depletion layer contacts the collector side when the current is turned off, an epitaxial wafer (hereinafter referred to as an epi wafer) is used. Is used. However, the PT type IGBT has a problem of high cost because it uses an epi-wafer. Also, switching loss increases at high temperatures for lifetime control. For this reason, the ON voltage decreases at a high temperature, and current may concentrate on a specific element during parallel use, causing damage.
In order to overcome the drawbacks of the PT-type substrate, a non-punch through (hereinafter referred to as NPT) type IGBT in which the depletion layer does not contact the collector side at the time of OFF has been developed. More recently, an FS-IGBT having a trench gate structure and a field stop (hereinafter referred to as FS) layer formed on the collector side as shown in FIG. It has come to be manufactured. As a substrate for an NPT type or FS type IGBT, a wafer having a diameter of 150 mm or less (hereinafter referred to as an FZ wafer) cut from a silicon single crystal grown by the FZ method has been used.

Although the FZ wafer is cheaper than the epi wafer, it is necessary to increase the diameter of the wafer in order to further reduce the manufacturing cost of the IGBT. However, it is extremely difficult to grow a single crystal having a diameter larger than 150 mm by the FZ method, and even if it can be produced, it is difficult to stably supply it at a low price.
Therefore, we tried to manufacture a silicon single crystal wafer for IGBT by the Czochralski method (CZ method) that can easily grow a large diameter crystal of φ200 mm or more, preferably φ300 mm or more.

The techniques described in Patent Documents 1 to 3 described below are all aimed at reducing defects in the wafer. In Patent Document 1, the entire surface is grown by the CZ method and doped with nitrogen. A silicon single crystal consisting of an N-region, having an interstitial oxygen concentration of 8 ppma or less, or doped with nitrogen, excluding at least void-type defects and dislocation clusters from the entire surface, and having an interstitial oxygen concentration of 8 ppma or less A wafer is disclosed.
Patent Document 2 discloses a method for producing a silicon single crystal that is pulled up using the Czochralski method while being doped with oxygen and nitrogen, and 6.5 × 10 ¹⁷ atoms / day while the single crystal is pulled up. A method for producing a silicon single crystal doped with oxygen at a concentration of less than cm ³ and nitrogen at a concentration of more than 5 × 10 ¹³ atoms / cm ³ is disclosed.
Further, in Patent Document 3, a nitrogen concentration of 2 × 10 ¹⁴ atoms / cm ³ or more and 2 × 10 ¹⁶ atoms / cm ³ or less grown from a melt added with nitrogen by the Czochralski method, and 7 × 10 ¹⁷ atoms is used. Containing oxygen concentration of / cm ³ or less, various surface defect densities are FPD ≦ 0.1 / cm ² , SEPD ≦ 0.1 / cm ² , and OSF ≦ 0.1 / cm ² , A silicon semiconductor substrate is disclosed in which the defect density is LSTD ≦ 1 × 10 ⁵ / cm ³ and the oxide film breakdown voltage characteristics are TZDB high C mode pass rate ≧ 90% and TDDB pass rate ≧ 90%.
JP 2001-146498 A JP 2000-7486 A JP 2002-29891 A

However, although Patent Documents 1 to 3 disclose a wafer manufacturing method that is free of crystal defects, the wafer characteristics necessary for the IGBT are not clarified. In order to grow a crystal having defect-free CZ silicon having an interstitial oxygen concentration of 7 × 10 ¹⁷ atoms / cm ³ or less and a variation in resistivity within a wafer surface of 5% or less, a quartz crucible is rotated. The speed and the rotation speed of the crystal need to be significantly changed from the conventional conditions, and the pulling speed margin for growing defect-free crystals is reduced, resulting in a decrease in yield.

  The present invention has been made in view of the above circumstances, and is capable of expanding the pulling speed margin, and manufacturing a wafer having improved oxide film withstand voltage characteristics, improved leakage current, and small variations in resistivity. It is an object to provide a method for manufacturing a silicon single crystal wafer for IGBT and a silicon single crystal wafer for IGBT.

When a silicon single crystal wafer is manufactured by the Czochralski method (hereinafter sometimes referred to as the CZ method), a wafer having a large diameter of about 300 mm can be manufactured. The wafer manufactured by the CZ method is For this reason, it is not suitable for an IGBT wafer.
(1) In the CZ method, excessive vacancies aggregate when a single crystal is grown, and COP defects (Crystal Originated Particles) of about 0.2 to 0.3 μm are generated. When manufacturing an IGBT, a gate oxide film is formed on the wafer surface. When a COP defect is exposed on the wafer surface or a COP defect existing in the vicinity of the wafer surface is taken into the gate oxide film. Degrading GOI (Gate Oxide Integrity). Therefore, a wafer that does not contain COP defects is required so that the GOI does not deteriorate, but it is difficult to manufacture a defect-free wafer by the CZ method.
(2) The silicon single crystal wafer manufactured by the CZ method contains excess oxygen of about 1 × 10 ¹⁸ atoms / cm ³ , and such a wafer has a low temperature of about 1 hour at 450 ° C. When heat treatment (heat treatment corresponding to the sintering process in the IGBT manufacturing process) is performed, oxygen donors are generated, and the resistivity of the wafer changes before and after the heat treatment.
(3) The resistivity of a silicon single crystal wafer manufactured by the CZ method can be controlled by the amount of dopant added to the silicon melt, and phosphorus is added as a dopant to an IGBT wafer, but phosphorus has a segregation coefficient. Since it is small, the concentration greatly changes along the length direction of the silicon single crystal. Therefore, within a single silicon single crystal, the range of wafers having a resistivity that matches the design specifications is narrow.
(4) The silicon single crystal wafer manufactured by the CZ method contains excess oxygen of about 1 × 10 ¹⁸ atoms / cm ^3. Oxygen precipitates as SiO ₂ and degrades the recombination lifetime.

(5) Furthermore, according to a recent study, “a wafer having defect-free CZ silicon with an interstitial oxygen concentration of 8.5 × 10 ¹⁷ atoms / cm ³ or less and a variation in resistivity within the wafer surface of 5% or less. However, when the P / N junction leak was measured after the IGBT thermal process simulation, the junction leak occurred in the OSF region and the Pv region (described later), which are specific crystal regions. Then, infrared scatterer defects (oxygen precipitates) were generated at 1 × 10 ⁵ / cm ³ or more in the infrared tomograph (MO-441 manufactured by Mitsui Mining & Mining). There was a desire to eliminate the variation in resistivity.

  In order to solve the above problems (1) to (5), the present inventors have conducted intensive research. As a result, by adopting the following configuration, a wafer having the wafer characteristics necessary for the IGBT is obtained as CZ. It was found that it can be manufactured by the method.

The IGBT silicon single crystal wafer of the present invention is an IGBT silicon single crystal wafer made of a silicon single crystal grown by the Czochralski method, and eliminates COP defects, dislocation clusters, and OSF regions in the entire crystal diameter direction. The interstitial oxygen concentration is 8.5 × 10 ¹⁷ atoms / cm ³ or less, and the variation in resistivity within the wafer surface is 5% or less.
In the present invention, when the silicon single crystal is grown by the Czochralski method, the silicon single crystal that can eliminate COP defects, dislocation clusters, and OSF regions is grown at a pulling speed capable of eliminating COP defects, dislocation clusters, and OSF regions. In addition, the silicon single crystal after the pulling can be irradiated with neutrons and doped with phosphorus.
The silicon single crystal wafer for IGBT of the present invention is a silicon single crystal wafer for IGBT made of silicon single crystal grown by the Czochralski method, and has COP defects, dislocation clusters, OSF regions and The Pv region is excluded, the interstitial oxygen concentration is 8.5 × 10 ¹⁷ atoms / cm ³ or less, and the variation in resistivity within the wafer surface is 5% or less.
In the present invention, when the silicon single crystal is grown by the Czochralski method, the pulling speed capable of pulling up the silicon single crystal capable of eliminating COP defects, dislocation clusters, OSF regions, and Pv regions in the entire crystal diameter direction. In addition, the silicon single crystal after the pulling can be irradiated with neutrons and doped with phosphorus.
In the present invention, the silicon melt is preferably doped with nitrogen so that the nitrogen concentration in the silicon single crystal is in the range of 5 × 10 ¹² atoms / cm ^{3 to} 5 × 10 ¹⁵ atoms / cm ³ .
The method for producing a silicon single crystal wafer for IGBT of the present invention is a method for producing a silicon single crystal wafer for IGBT obtained by growing a silicon single crystal by the Czochralski method, and in an atmosphere gas in a CZ furnace. A silicon single crystal capable of eliminating a COP defect, a dislocation cluster, and an OSF region by introducing a hydrogen atom-containing substance having a hydrogen gas equivalent partial pressure in the range of 40 Pa or more and 400 Pa or less to a silicon single crystal pulling rate in the entire crystal diameter direction. Is characterized in that a single crystal having an interstitial oxygen concentration of 8.5 × 10 ¹⁷ atoms / cm ³ or less is grown at a speed capable of pulling up, and the silicon single crystal after the pulling is irradiated with neutrons and doped with phosphorus. To do.
The method for producing a silicon single crystal wafer for IGBT of the present invention is a method for producing a silicon single crystal wafer for IGBT obtained by growing a silicon single crystal by the Czochralski method, and in an atmosphere gas in a CZ furnace. A hydrogen atom-containing substance having a hydrogen gas equivalent partial pressure of 40 Pa or more and 400 Pa or less is introduced into the silicon single crystal, and the pulling speed of the silicon single crystal can be eliminated from the COP defects, dislocation clusters, OSF regions, and Pv regions throughout the crystal diameter direction. Growing a single crystal having an interstitial oxygen concentration of 8.5 × 10 ¹⁷ atoms / cm ³ or less at a speed at which the silicon single crystal can be pulled, and irradiating the silicon single crystal after pulling with neutron irradiation to dope phosphorus It is characterized by.
The method for producing a silicon single crystal wafer for IGBT of the present invention is a method for producing a silicon single crystal wafer for IGBT obtained by growing a silicon single crystal by the Czochralski method, wherein the n-type dopant is added to the silicon melt. Is added to the atmosphere gas in the CZ furnace, and a hydrogen atom-containing substance having a hydrogen gas equivalent partial pressure in the range of 40 Pa to 400 Pa is introduced, and the pulling rate of the silicon single crystal is increased in COP defects and dislocations throughout the crystal diameter direction. A single crystal having an interstitial oxygen concentration of 8.5 × 10 ¹⁷ atoms / cm ³ or less is grown at a speed at which a silicon single crystal capable of excluding clusters and OSF regions can be pulled up.
The method for producing a silicon single crystal wafer for IGBT of the present invention is a method for producing a silicon single crystal wafer for IGBT obtained by growing a silicon single crystal by the Czochralski method, wherein the n-type dopant is added to the silicon melt. Is added to the atmosphere gas in the CZ furnace, and a hydrogen atom-containing substance having a hydrogen gas equivalent partial pressure in the range of 40 Pa to 400 Pa is introduced, and the pulling rate of the silicon single crystal is increased in COP defects and dislocations throughout the crystal diameter direction. A single crystal having an interstitial oxygen concentration of 8.5 × 10 ¹⁷ atoms / cm ³ or less is grown at a speed at which a silicon single crystal capable of excluding clusters, OSF regions and Pv regions can be pulled up.
In the present invention, the nitrogen concentration of the silicon single crystal is 5 × 10 ¹² atoms / cm ³ or more and 5 × 10 ¹⁵ atoms / cm ³ or less, or 1 × 10 ¹³ atoms / cm ³ or more and 5 × 10 ¹⁴ atoms / cm ³ or less. It is preferable to add nitrogen to the silicon melt so as to be in the concentration range.

  Furthermore, in the silicon single crystal wafer for IGBT of the present invention, the silicon single crystal is grown at a pulling speed capable of pulling up the grown-in defect-free silicon single crystal when grown by the Czochralski method. It is preferable that the silicon single crystal after being pulled is irradiated with neutrons and doped with phosphorus.

Further, in the silicon single crystal wafer for IGBT of the present invention, when the silicon single crystal is grown by the Czochralski method, the grown-in defect free from the silicon melt doped with the n-type dopant. It is preferable that the silicon single crystal is grown at a pulling speed capable of pulling up.
Furthermore, in the silicon single crystal wafer for IGBT of the present invention, the silicon single crystal may be 1 × 10 ¹⁴ atoms / cm ³ or more and 5 × 10 ¹⁵ atoms / cm ³ or less, or 5 × 10 ¹² atoms / cm ³ or more 5 × 10 ¹⁵ atoms / cm ³ or less of nitrogen is preferably doped.

Furthermore, in the silicon single crystal wafer for IGBT of the present invention, the pass rate of TZDB at a breakdown electric field of 8 MV / cm is 90% or more, and the concentration of oxygen donor generated when heat treatment is performed at 450 ° C. for 1 hour. Is 9.8 × 10 ¹² cm ⁻³ or less, and the density of the BMD deposited when two-stage heat treatment is performed at 800 ° C. for 4 hours and 1000 ° C. for 16 hours is 5 × 10 ⁷ cm ⁻³ or less. The recombination lifetime when the two-stage heat treatment is performed is preferably 100 μsec or more.
Furthermore, in the silicon single crystal wafer for IGBT of the present invention, phosphorus and a p-type dopant having a segregation coefficient smaller than that of phosphorus are 1 × 10 ¹³ atoms / cm ³ or more and 1 × 10 ¹⁵ atoms / cm ^{3, respectively.} It is preferably contained in the following concentrations.
Furthermore, in the silicon single crystal wafer for IGBT of the present invention, the LPD density on the wafer surface is 0.1 piece / cm ² or less, and the light etching defect density is 1 × 10 ³ pieces / cm ² or less. Is preferred.
Moreover, in the silicon single crystal wafer for IGBT of the present invention, it is preferable that a polycrystalline silicon layer of 50 nm or more and 1000 nm or less is formed on the back surface side.

In the present invention, the variation in resistivity is measured at a total of three locations: the wafer center, a position between the wafer center and the periphery, and a position 5 mm from the wafer periphery. The maximum value and the minimum value are selected, and the value is obtained by the formula of (maximum value−minimum value) × 100 / minimum value.
Further, in the present invention, the fact that the OSF region can be excluded means that the temperature is raised from 900 ° C. to 1000 ° C. in a dry oxygen atmosphere at a rate of temperature rise of 5 ° C./min, then 1000 ° C. for 1 hour in a dry oxygen atmosphere, After heating at 1000 ° C. to 1150 ° C. in a wet oxygen atmosphere at a rate of temperature increase of 3 ° C./min, heat treatment was performed in a wet oxygen atmosphere at 1150 ° C. for 2 hours and then to 900 ° C., and then 2 μm light etching was performed. When the OSF area is exposed and the distribution of the OSF density in the wafer surface is measured, if there is no OSF density of 10 / cm ² , the OSF area does not exist, that is, the OSF area can be eliminated. Judgment.

In the present invention, the Pv region can be excluded, as described below, by performing a multi-stage heat treatment simulating the IGBT manufacturing process, cleaving the wafer after the multi-stage heat treatment, and using the infrared tomograph ( When oxygen precipitate (BMD) density is measured with MO441 manufactured by Mitsui Mining & Smelting Co., Ltd., if there is no area of 1E7 / cm3 or more in the infrared tomograph, the Pv area does not exist, that is, the Pv area is excluded. Judgment is possible.
<Multi-stage heat treatment>
950 ° C., 4 hours 1100 ° C., 4 hours 900 ° C., 3 hours 900 ° C., 8 hours 1150 ° C., 2 hours 1100 ° C., 4 hours However, all the input / output temperatures are 800 ° C. and the rate of temperature increase is 8 ° C. / Min, the temperature drop rate is 2.5 ° C./min, and the treatment atmosphere is 3% oxygen + 97% nitrogen.

  The Pv region is a silicon single crystal ingot grown by the Czochralski method, and the region where the interstitial silicon type point defects exist predominantly in the ingot is defined as the I region, and the hole type point defects control. When the region that is present in general is the V region, and the region in which no interstitial silicon type point defect aggregates and no vacancy type point defect aggregates exist is the P region, it is adjacent to the I region and in the P region. A region less than the lowest interstitial silicon concentration capable of forming an interstitial dislocation belongs to the Pi region, and a region adjacent to the OSF region and below the vacancy concentration capable of forming a COP belonging to the P region is defined as a Pv region. .

The silicon wafer is manufactured by pulling up an ingot from a silicon melt in a pulling furnace by a CZ method with a predetermined pulling speed profile based on the Boronkov theory, and then cutting out the ingot. In general, when a silicon single crystal ingot is pulled from the silicon melt in the furnace by the CZ method, point defects and agglomerates (agglomerates: three-dimensional defects) Will occur. There are two general forms of point defects: vacancy-type point defects and interstitial silicon-type point defects. A vacancy is one in which one silicon atom leaves one of its normal positions in the silicon crystal lattice. A defect caused by such a hole is a hole-type point defect. On the other hand, silicon atoms present at positions (interstitial sites) other than the lattice points of the silicon crystal are interstitial silicon. Such defects caused by interstitial silicon are interstitial silicon point defects.

Point defects are generally formed at the contact surface between a silicon melt (molten silicon) and an ingot (solid silicon). However, by continuously pulling up the ingot, the portion that was the contact surface begins to cool as it is pulled up. During cooling, the vacancies or interstitial silicon diffuse to form dislocation clusters that are COP or interstitial agglomerates that are vacancy agglomerates. In other words, the aggregate is a three-dimensional structure generated due to the merge of point defects. The agglomerates of vacancy-type point defects include defects called LSTD (Laser Scattering Tomograph Defects) or FPD (Flow Pattern Defects) in addition to the above-mentioned COP. Contains a defect called. FPD is a unique flow pattern that appears when a silicon wafer produced by cutting out an ingot is subjected to Secco etching (HF: K2 Cr2O7 (0.15 mol / l) = 2: 1 mixture) for 30 minutes. The LSTD is a source that generates scattered light having a refractive index different from that of silicon when an infrared ray is irradiated into a silicon single crystal.

Boronkov's theory is that in order to grow a high purity ingot with a small number of defects, the ingot pulling speed is V (mm / min), and the temperature gradient in the vertical direction of the ingot near the interface between the ingot and the silicon melt is G (° C. / Mm) is to control V / G (mm ² / min · ° C.).

Corresponding to the change of the V / G value from a high value to a low value, the above-described V region, OSF region, Pv region, Pi region, and I region are arranged in this order. For this reason, G (° C./mm) specific to the pulling apparatus is calculated by electrothermal analysis software, a pulling experiment in which the pulling speed is gradually reduced is carried out, and the single crystal pulling length defect obtained thereby By examining the distribution in advance, the pulling speed V (mm / min) necessary for obtaining the Pv region, the Pi region, and the I region can be calculated.
FIG. 6 shows the relationship between the OSF density and the BMD density with respect to the distance from the wafer center of the wafer corresponding to Experimental Example A described later.

Corresponding to the change of the V / G value from a high value to a low value, the above-described V region, OSF region, Pv region, Pi region, and I region are arranged in this order.
The value of V / G serving as the boundary between such regions is the threshold that serves as the boundary between the V region and the OSF region, the threshold that serves as the boundary between the OSF region and the Pv region, and the Pv region and Pi region. The threshold value decreases in the order of the threshold value that becomes the boundary and the threshold value that becomes the boundary between the Pi region and the I region.
This V / G value varies depending on the actual machine, such as the structure of the hot zone at the top of the pulling furnace, but is determined by measuring the COP density, OSF density, BMD density, LSTD density or FPD, light etching defect density, etc. Is possible.

  Further, in the present invention, “Grown-in defect free” means that all defects that may occur with crystal growth such as COP defects and dislocation clusters are eliminated, that is, the above Pv region, PI Means an area.

“Light etching defects” means that an As-Grown silicon single crystal wafer is immersed in an aqueous copper sulfate solution and then air-dried, and then subjected to Cu decoration for about 20 minutes at 900 ° C. in a nitrogen atmosphere. In order to remove the Cu silicide layer on the surface of the specimen, it was immersed in a HF / HNO ₃ mixed solution, and the surface layer was etched and removed by several tens of microns, and then the wafer surface was etched by 2 μm light etching (chromic acid etching). And defects detected using an optical microscope. According to this evaluation method, the dislocation clusters formed at the time of crystal growth can be revealed by Cu decoration, and the dislocation clusters can be detected with high sensitivity. That is, the light etching defect includes a dislocation cluster.
In the present invention, the “LPD density” is a density of defects of 0.1 μm size or more detected using a laser light scattering particle counter (SP1 (surfscan SP1): manufactured by KLA-Tencor).

Further, TZDB is an abbreviation for Time Zero Dielectric Breakdown, and is one of the indexes representing GOI. The pass rate of TZDB in the present invention is a condition where the electrode area of the measurement electrode is 8 mm ² and the determination current is 1 mA. The probability of not causing electrostatic breakdown is taken as the pass rate of TZDB. This pass rate is also called a C-mode pass rate.

  According to the silicon single crystal wafer of the present invention, since COP defects and dislocation clusters are eliminated in the entire crystal diameter direction, it is suitable as a wafer for IGBT which is an element that uses the wafer in the vertical direction. That is, since COP defects and dislocation clusters are eliminated in the entire crystal diameter direction, the COP defects are not taken into the gate oxide film when the gate oxide film is formed on the wafer surface in the IGBT manufacturing process, and the GOI is deteriorated. I will not let you. Further, by eliminating dislocation clusters, leakage current in the integrated circuit can be prevented.

Further, since the OSF region is excluded, in the IGBT manufacturing process, there are no oxygen precipitates stable up to a high temperature, no defect is formed in the device active region, and leakage current in the integrated circuit can be prevented. Furthermore, the yield rate can be 90% or higher. Since the OSF region is excluded, COP defects are not taken into the gate oxide film when the gate oxide film is formed on the wafer surface in the IGBT manufacturing process, and the GOI is not deteriorated.
Further, since the Pv region is eliminated, there is no oxygen precipitation nucleus that is stabilized by the low-temperature heat treatment in the IGBT manufacturing process, no defect is formed in the device active region, and leakage current in the integrated circuit can be prevented. Furthermore, the yield rate can be 95% or more. Since the Pv region is excluded, COP defects are not taken into the gate oxide film when the gate oxide film is formed on the wafer surface in the IGBT manufacturing process, and the GOI is not deteriorated.

Further, since the interstitial oxygen concentration is 8.5 × 10 ¹⁷ atoms / cm ³ or less, the concentration of oxygen donor generated after the heat treatment of the wafer can be suppressed to 9.8 × 10 ¹² atoms / cm ³ or less. Thus, the change in the resistivity of the wafer can be prevented, and the quality of the silicon single crystal wafer can be stabilized.
The reason why the oxygen donor concentration is 9.8 × 10 ¹² atoms / cm ³ or less is as follows. An n-type wafer having a resistivity of 30 to 40 to 70 to 120 Ω · cm is used for the high voltage IGBT. For example, when the resistivity specification of the substrate is 50 ± 5 Ω · cm, the allowable donor concentration is 9.8 × 10 ¹² ions / cm ³ or less. Here, the temperature at which oxygen donors due to oxygen are most likely to be generated is 450 ° C. For example, in the device process, the Al wiring sintering process is performed around this temperature. FIG. 1 shows the results of examining the oxygen concentration dependence of the oxygen donor concentration generated when heat treatment is performed at 450 ° C. for 1 hour. From FIG. 1, in order to suppress the oxygen donor concentration to 9.8 × 10 ¹² atoms / cm ³ or less, the interstitial oxygen concentration of the wafer must be controlled to 8.5 × 10 ¹⁷ atoms / cm ³ or less. I understand that. For this reason, in the present invention, the interstitial oxygen concentration is set to 8.5 × 10 ¹⁷ atoms / cm ³ or less.

In addition, in the normal CZ method, it may be difficult to reduce the interstitial oxygen concentration to 8.5 × 10 ¹⁷ atoms / cm ³ or less. In this case, the MCZ method is used to grow a single crystal by applying a magnetic field. The interstitial oxygen concentration can be 8.5 × 10 ¹⁷ atoms / cm ³ or less. The interstitial oxygen concentration can also be reduced by reducing the rotation speed of the quartz crucible.

Further, according to the silicon single crystal wafer of the present invention, the variation in resistivity within the wafer surface is 5% or less, so that the quality of the IGBT can be stabilized.
By the way, the resistivity of a silicon single crystal wafer manufactured by the CZ method can be controlled by the amount of dopant contained in the silicon single crystal, but phosphorus often used as a dopant for an IGBT substrate has a small segregation coefficient, so that the silicon single crystal The concentration varies greatly over the length direction. Therefore, the range in which a wafer having a resistivity that meets the design specifications in one single crystal is obtained is narrow. Therefore, in the present invention, as described above, neutron irradiation, addition of an n-type dopant to the silicon melt, addition of a predetermined amount of p-type dopant having a segregation coefficient smaller than phosphorus and phosphorus, and various other means are employed. In either case, it is important to grow a single crystal using a synthetic quartz crucible with a low impurity concentration as a raw material and a low impurity elution. By using these means, the yield of the silicon single crystal can be improved.

For neutron irradiation, first, a silicon single crystal is grown without adding a dopant for adjusting the resistivity to the silicon melt, and irradiating this non-doped silicon single crystal with neutrons results in ³⁰ Si in the crystal. Phosphorus can be doped by utilizing the phenomenon that is converted to ³¹ P. ^{Since 30} Si is uniformly contained in a single crystal at a concentration of about 3%, this neutron irradiation is a method in which phosphorus can be doped most uniformly in both the radial and axial directions of the crystal.
The resistivity can also be controlled by adding an n-type dopant to the silicon melt. At this time, it is desirable to apply a so-called DLCZ method (Double Layered Czochralski). The DLCZ method is a method for suppressing a change in concentration in the crystal axis direction of a dopant having a small segregation coefficient such as phosphorus. This method is disclosed, for example, in Japanese Patent Laid-Open No. 5-43384. In the CZ method, all the polycrystalline silicon is once dissolved in a crucible, added as a silicon melt, phosphorus is added, and the temperature at the bottom of the crucible is lowered. Dopant concentration incorporated into the single crystal by solidifying the silicon melt upward from the bottom to form a silicon solidified layer and growing the crystal while gradually dissolving the silicon solidified layer from the top toward the bottom Is a method of keeping the constant almost constant.
In the present invention, the change in resistivity in the crystal axis direction of the silicon single crystal can also be suppressed by adopting the DLCZ method.

Moreover, the resistivity change in the crystal axis direction of the silicon single crystal can also be suppressed by adding a predetermined amount of phosphorus and a p-type dopant having a segregation coefficient smaller than that of phosphorus. This is called a so-called double doping method and is disclosed in, for example, Japanese Patent Application Laid-Open No. 2002-128591, and is a method for suppressing a change in resistivity in the axial direction of a crystal doped with a dopant having a small segregation coefficient such as phosphorus. . The phosphorus concentration change is compensated for by doping p-type dopant (for example, Al, Ga, In) having a segregation coefficient smaller than that of phosphorus as a counter dopant. FIG. 2 shows a change in resistivity in the crystal axis direction when only phosphorus is doped and when phosphorus and aluminum are simultaneously doped. When the resistivity specification of the wafer is 50 ± 5 Ω · cm, the yield is improved about three times by simultaneously doping with phosphorus and aluminum. The yield is the highest when the concentration ratio of aluminum to phosphorus at the upper end of the single crystal is about 50%. In the present invention, phosphorous and a p-type dopant having a segregation coefficient smaller than that of phosphorous are contained in concentrations of 1 × 10 ¹³ atoms / cm ³ or more and 1 × 10 ¹⁵ atoms / cm ³ or less, respectively. The change in resistivity in the crystal axis direction can be suppressed.

  Furthermore, in the present invention, a so-called CCZ method can also be applied. This method is disclosed in, for example, Japanese Patent Application Laid-Open No. 61-36197, and by adding polycrystalline silicon containing no dopant to a silicon melt containing phosphorus during single crystal growth, In this method, the concentration of the incorporated dopant is kept almost constant.

  Furthermore, in the case of single crystal growth in which a dopant is added to a silicon melt as in the DLCZ method or CCZ method, the crystal rotation speed during crystal growth is rotated fast in order to suppress resistivity variation in the wafer surface. In the case of growing a single crystal having a diameter of 200 mm or less, it is desirable to rotate the crystal rotation speed in the range of 15 to 30 rpm, and in the case of a diameter of 300 mm or more, in the range of 8 to 15 rpm. Normally, when the crystal rotation speed is increased, the pulling speed margin width for obtaining a grow-in defect-free crystal is narrowed, and it becomes difficult to grow a single crystal itself. By growing the silicon single crystal in the contained gas atmosphere, a sufficient pulling speed margin for obtaining a grow-in defect free crystal can be secured.

Alternatively, when the rotation speed of the quartz crucible is R1 (rpm) and the rotation speed of the crystal is R2 (rpm), the range is R1: 0.1 or more and 2 or less, R2: 1 or more and 7 or less, and R1: 0. When R is 5 or more and 0.7 or less, R2 <7-5 (R1-0.5) is satisfied, and when R1: 0.7 or more and 1 or less, R2 <6 is satisfied, and R1 is 1 or more and 2 or less. In this case, it can be set in a range satisfying R2 <6-4 (R1-1). In this case, a silicon single crystal having a low oxygen concentration can be grown by setting the interstitial oxygen concentration in the single crystal to 4.0 × 10 ¹⁷ atoms / cm ³ or less. The quartz crucible rotation speed R1 (rpm) and the crystal rotation speed R2 (rpm) are in the range of R1: 0.1 or more and 2 or less, R2: 1 or more and 7 or less, provided that R1: 0.3 or more, 0. When 5 or less, R2 <7-5 (R1-0.3) is satisfied, and when R1: 0.5 or more and 0.7 or less, R2 <6 is satisfied, and R1: 0.7 or more and 1 or less. In this case, the range may be set to satisfy R2 <6-3.4 (R1-0.7). In this case, a silicon single crystal having a low oxygen concentration can be provided by setting the interstitial oxygen concentration in the single crystal to 3.5 × 10 ¹⁷ atoms / cm ³ or less. The quartz crucible rotation speed R1 (rpm) and the crystal rotation speed R2 (rpm) are in the range of R1: 0.1 or more and 1 or less, R2: 1 or more and 7 or less, provided that R1: 0.2 or more and 0.3 or less. In the following cases, R2 <7-10 (R1-0.2) is satisfied, and in the case of R1: 0.3 to 0.5, R2 <6 is satisfied, and R1: 0.5 to 0.7. In this case, R2 <6-5 (R1-0.5) is satisfied, and when R1: 0.7 or more and 1 or less, R2 <5-6.7 (R1-0.7) is satisfied. Can be set. In this case, a silicon single crystal having an interstitial oxygen concentration of 3.0 × 10 ¹⁷ atoms / cm ³ or less in the single crystal can be grown, and a silicon single crystal having a lower oxygen concentration can be grown.

Next, 5 × 10 ¹² atoms / cm ³ or more and 5 × 10 ¹⁵ atoms / cm ³ or less, or 1 × 10 ¹³ atoms / cm ³ or more and 2 × 10 ¹⁵ atoms / cm ³ or less are more preferable. Is doped with nitrogen of 5 × 10 ¹³ atoms / cm ³ or more and 9 × 10 ¹⁴ atoms / cm ³ or less, thereby facilitating elimination of COP defects and dislocation clusters. Alternatively, when a silicon single crystal is doped with nitrogen of 1 × 10 ¹³ atoms / cm ³ or more and 5 × 10 ¹⁴ atoms / cm ³ or less, it is easy to eliminate COP defects and dislocation clusters. If the doping amount of nitrogen is less than the above range, COP defects, dislocation clusters, OSF regions, and Pv regions may not be completely eliminated. If the nitrogen doping amount exceeds the above range, it is difficult to eliminate OSF regions and Pv regions. . In addition, dislocations and the like occur due to the formation of nitrides, and the silicon single crystal cannot be grown, which is not preferable.
Next, the silicon single crystal is doped with nitrogen of 1 × 10 ¹⁴ atoms / cm ³ or more and 5 × 10 ¹⁵ atoms / cm ³ or less, thereby facilitating elimination of COP defects and dislocation clusters. If the doping amount of nitrogen is less than 1 × 10 ¹⁴ atoms / cm ³ , COP defects and dislocation clusters may not be completely eliminated, and if it exceeds 5 × 10 ¹⁵ atoms / cm ³ , nitrides are formed and silicon is formed. A single crystal cannot be grown.

Moreover, according to the silicon single crystal wafer of the present invention, the pass rate of TZDB is 90% or more, and the concentration of oxygen donor generated when heat treatment is performed at 450 ° C. for 1 hour is 6 × 10 ¹² cm ^−3. Or 9.8 × 10 ¹² cm ⁻³ or less, and the density of BMD generated when two-stage heat treatment is performed at 800 ° C. for 4 hours and 1000 ° C. for 16 hours is 5 × 10 ⁷ cm ⁻³ or less Since the recombination lifetime in the case of performing the two-step heat treatment is 100 μsec or more, the characteristics required for the silicon single crystal wafer for IGBT can be satisfied.

The recombination lifetime is deteriorated by interstitial oxygen contained in the silicon single crystal being precipitated as SiO ₂ through a device formation process. According to the wafer of the present invention, since the interstitial oxygen concentration is 8.5 × 10 ¹⁷ atoms / cm ³ or less as described above, the recombination lifetime can be 100 μsec or more.

The method for producing a silicon single crystal wafer for IGBT of the present invention is a method for producing a silicon single crystal wafer for IGBT obtained by growing a silicon single crystal by the Czochralski method, and in an atmosphere gas in a CZ furnace. Introducing a hydrogen atom-containing substance with a hydrogen gas equivalent partial pressure in the range of 40 Pa or more and 400 Pa or less, and the silicon single crystal pulling rate is such that the grown-in defect-free silicon single crystal can be pulled at an interstitial oxygen concentration. Is grown to a single crystal of 8.5 × 10 ¹⁷ atoms / cm ³ or less, and the silicon single crystal after being pulled is irradiated with neutrons to be doped with phosphorus.
Moreover, the manufacturing method of the silicon single crystal wafer for IGBT of this invention is a manufacturing method of the silicon single crystal wafer for IGBT obtained by growing a silicon single crystal by the Czochralski method, Comprising: An n-type dopant is added to a silicon melt. A hydrogen atom-containing substance having a hydrogen gas equivalent partial pressure in the range of 40 Pa or more and 400 Pa or less is introduced into the atmosphere gas in the CZ furnace, and the pulling rate of the silicon single crystal is reduced to a grown-in defect-free silicon single crystal Can grow a single crystal having an interstitial oxygen concentration of 8.5 × 10 ¹⁷ atoms / cm ³ or less.

The method for producing a silicon single crystal wafer for IGBT of the present invention is a method for producing a silicon single crystal wafer for IGBT obtained by growing a silicon single crystal by the Czochralski method, wherein phosphorus is added to the silicon melt. 2.9 × 10 ¹³ atoms / cm ³ or more and 2.9 × 10 ¹⁵ atoms / cm ³ or less, a p-type dopant having a segregation coefficient smaller than that of phosphorus, and the concentration in the crystal is 1 × 10 according to the segregation coefficient Hydrogen atoms containing material that is added in the range of ¹³ atoms / cm ^{3 to} 1 × 10 ¹⁵ atoms / cm ³ and in the atmosphere gas in the CZ furnace is in the range of 40 Pa to 400 Pa in terms of hydrogen gas partial pressure. The rate of pulling of the silicon single crystal is such that the growth rate of the grown-in defect-free silicon single crystal can be increased. Degrees can be grown to 8.5 × ¹⁰ 17 atoms / cm ³ or less of a single crystal.
Furthermore, in the method for producing a silicon single crystal wafer for IGBT of the present invention, nitrogen is added to the silicon single crystal at a concentration of 5 × 10 ¹² atoms / cm ³ or more and 5 × 10 ¹⁵ atoms / cm ³ or less. Is preferred.

Here, the hydrogen-containing substance is a substance containing hydrogen atoms in its molecule, and is a gaseous substance that generates hydrogen gas by being thermally decomposed when dissolved in the silicon melt. This hydrogen-containing substance includes hydrogen gas itself. By mixing this hydrogen-containing substance with an inert gas and introducing it into the atmosphere at the time of forming the necking portion, the hydrogen concentration in the silicon melt can be improved. Specific examples of the hydrogen-containing substance include inorganic compounds containing hydrogen atoms such as hydrogen gas, H ₂ O, and HCl, hydrocarbon atoms such as silane gas, CH ₄ , and C ₂ H _2, and hydrogen atoms such as alcohol and carboxylic acid. Examples of the organic compound include, but it is particularly preferable to use hydrogen gas. In addition, as the atmospheric gas in the CZ furnace, inexpensive Ar gas is preferable, and various rare gases such as He, Ne, Kr, and Xe alone or a mixed gas thereof can be used.

Moreover, in this invention, the density | concentration of the hydrogen containing substance in hydrogen containing atmosphere is made into the range of 40 Pa or more and 400 Pa or less in hydrogen gas conversion partial pressure. Here, the hydrogen gas equivalent partial pressure is because the amount of hydrogen atoms obtained by thermal decomposition of the hydrogen-containing material depends on the number of hydrogen atoms originally contained in the hydrogen-containing material. . For example, 1 mole of H ₂ O contains 1 mole of H _2, but 1 mole of HCl contains only 0.5 mole of H ₂ . Therefore, in the present invention, the hydrogen-containing substance is used so that an atmosphere equivalent to the reference atmosphere can be obtained on the basis of a hydrogen-containing atmosphere in which hydrogen gas is introduced into the inert gas at a partial pressure of 40 to 400 Pa. It is desirable to determine the concentration of hydrogen, and the preferable pressure of the hydrogen-containing substance at this time is defined as a partial pressure in terms of hydrogen gas.
That is, in the present invention, it is assumed that a hydrogen-containing substance is dissolved in a silicon melt and is thermally decomposed in a high-temperature silicon melt to be converted into hydrogen atoms. What is necessary is just to adjust the addition amount of a hydrogen-containing substance so that a pressure may be in the range of 40-400 Pa.

By introducing a hydrogen atom-containing substance having a gas-converted partial pressure in the range of 40 Pa or more and 400 Pa or less, the allowable range of the speed at which a grown-in defect-free silicon single crystal can be pulled up can be increased. A wafer from which COP defects and dislocation clusters are eliminated in the entire direction can be easily manufactured. Further, the non-doped silicon single crystal after the pulling is irradiated with neutrons to dope phosphorus, or an n-type dopant such as phosphorus is added to the silicon melt, thereby reducing the variation in resistivity in the plane of the wafer. % Or less. The reduction in resistivity variation can also be achieved by adding phosphorus and a p-type dopant having a segregation coefficient smaller than that of phosphorus to the silicon melt.
Further, by adding nitrogen to the silicon melt, the allowable range of the speed at which the grown-in defect-free silicon single crystal can be pulled can be further increased, and the elimination of COP defects and dislocation clusters in the wafer is facilitated. .

  According to the present invention, there is provided a method for manufacturing a silicon single crystal wafer for IGBT and a silicon single crystal wafer for IGBT capable of expanding a pulling speed margin and manufacturing a wafer having a small variation in resistivity. it can.

FIG. 1 is a graph showing the relationship between interstitial oxygen concentration and oxygen donor concentration after heat treatment. FIG. 2 is a graph showing the relationship between the solidification rate and the resistivity. FIG. 3 is a schematic vertical cross-sectional view of a CZ furnace used in carrying out the method for producing a silicon single crystal wafer according to the embodiment of the present invention. FIG. 4 is a schematic cross-sectional view showing the peripheral portion of the silicon single crystal wafer according to the embodiment of the present invention. FIG. 5A is a schematic cross-sectional view showing an IGBT. FIG. 5B is a schematic cross-sectional view showing the IGBT. FIG. 5C is a schematic cross-sectional view showing the IGBT. FIG. 6 is a graph showing the relationship between the OSF density, the BMD density, and the distance from the wafer center in the OSF region, the Pv region, and the Pi region in Experimental Example A.

Explanation of symbols

3 ... Silicon melt 6 ... Silicon single crystal T ... Seed crystal

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Configuration of CZ furnace)
FIG. 3 is a longitudinal sectional view of a CZ furnace suitable for carrying out the method for manufacturing a silicon single crystal wafer for IGBT in the embodiment of the present invention.
The CZ furnace shown in FIG. 3 includes a crucible 1 disposed in the center of the chamber, a heater 2 disposed outside the crucible 1, and a magnetic field supply device 9 disposed outside the heater 2. . The crucible 1 has a double structure in which a quartz crucible 1a containing a silicon melt 3 inside is held by an outer graphite crucible 1b, and is rotated and moved up and down by a support shaft 1c called a pedestal.
A cylindrical heat shield 7 is provided above the crucible 1. The heat shield 7 has a structure in which an outer shell is made of graphite and the inside thereof is filled with graphite felt. The inner surface of the heat shield 7 is a tapered surface whose inner diameter gradually decreases from the upper end to the lower end. The upper outer surface of the heat shield 7 is a tapered surface corresponding to the inner surface, and the lower outer surface is formed in a substantially straight surface so as to gradually increase the thickness of the heat shield 7 downward.
Then, the silicon single crystal 6 can be formed by immersing the seed crystal T attached to the seed chuck 5 in the silicon melt 3 and pulling up the seed crystal T while rotating the crucible 1 and the pulling shaft 4. .

The heat shield 7 blocks the radiation heat from the heater 2 and the silicon melt 3 surface to the side surface of the silicon single crystal 6, surrounds the side surface of the growing silicon single crystal 6, and the silicon melt 3. It surrounds the surface. An example of the specification of the heat shield 7 is as follows.
The radial width W is, for example, 50 mm, the inclination θ of the inner surface of the inverted truncated cone surface with respect to the vertical direction is, for example, 21 °, and the height H1 of the lower end of the heat shield 7 from the melt surface is, for example, 60 mm.

  The magnetic field supplied from the magnetic field supply device 9 may be a horizontal magnetic field or a cusp magnetic field. For example, the strength of the horizontal magnetic field is 2000 to 4000 G (0.2 T to 0.4 T), more preferably 2500. -3500G (0.25T-0.35T), and the magnetic field center height is set to be within a range of -150 to +100 mm, more preferably -75 to +50 mm with respect to the melt surface.

(Manufacturing method of silicon single crystal wafer for IGBT)
Next, a method for manufacturing a silicon single crystal wafer for IGBT using the CZ furnace shown in FIG. 3 will be described.
First, for example, 100 kg of high-purity silicon polycrystal is charged into the crucible 1, and a silicon wafer having a CVD film made of, for example, silicon nitride is introduced as a nitrogen source. The nitrogen concentration in the silicon crystal is 5 × 10 ¹² atoms / cm ³ or more and 5 × 10 ¹⁵ atoms / cm ³ or less, or 1 × 10 ¹³ atoms / cm ³ or more and 5 × 10 ¹⁴ atoms / cm ³ or less, or It is preferable to adjust the nitrogen concentration in the silicon melt such that the concentration is 1 × 10 ¹⁴ atoms / cm ³ or more and 5 × 10 ¹⁵ atoms / cm ³ or less.

Next, the inside of the CZ furnace is a hydrogen-containing atmosphere composed of a mixed gas of a hydrogen-containing substance and an inert gas, the atmosphere pressure is 1.3 to 13.3 kPa (10 to 100 torr), and the hydrogen-containing substance in the atmosphere gas is The concentration is adjusted to be about 40 to 400 Pa in terms of hydrogen gas partial pressure. When hydrogen gas is selected as the hydrogen-containing substance, the hydrogen gas partial pressure may be 40 to 400 Pa. The concentration of hydrogen gas at this time is in the range of 0.3% to 31%.
In addition, it can also be set as the atmosphere only of the inert gas which does not contain hydrogen gas.

  If the hydrogen gas equivalent partial pressure of the hydrogen-containing material is less than 40 Pa, the allowable range of the pulling rate is reduced, and generation of COP defects and dislocation clusters cannot be suppressed. Further, the higher the hydrogen gas equivalent concentration (hydrogen concentration) of the hydrogen-containing substance, the greater the effect of suppressing dislocation generation. However, if the hydrogen gas equivalent partial pressure exceeds 400 Pa, the risk of explosion or the like increases when an oxygen leak occurs in the CZ furnace, which is not preferable for safety. The hydrogen gas equivalent partial pressure of the hydrogen-containing substance is more preferably in the range of 40 Pa to 250 Pa, and particularly preferably the hydrogen gas equivalent partial pressure is in the range of 40 Pa to 135 Pa.

Next, a horizontal magnetic field of, for example, 3000 G (0.3 T) is applied from the magnetic field supply device 9 so that the center height of the magnetic field is −75 to +50 mm with respect to the melt liquid surface, and the polycrystalline silicon is formed by the heater 2. Heat to make silicon melt 3.
Next, the seed crystal T attached to the seed chuck 5 is immersed in the silicon melt 3, and the crystal is pulled up while rotating the crucible 1 and the pulling shaft 4. As the pulling conditions in this case, the growth rate of the single crystal is V (mm / min), and the ratio V / G (mm) when the temperature gradient G (° C./mm) is 1350 ° C. from the melting point during single crystal growth. ² / min · ° C.) is controlled to about 0.22 to 0.15, and V is controlled to 0.42 to 0.33 mm / min, which is a speed at which the grown-in defect-free silicon single crystal can be pulled up. The following conditions can be exemplified. As other conditions, the rotation speed of the quartz crucible is 5 to 0.2 rpm, the rotation speed of the single crystal is 20 rpm or less, the pressure in the argon atmosphere is 1333 to 26660 Pa, and the magnetic field strength is 3000 to 5000 Gauss. Can be illustrated. In particular, by setting the rotation speed of the quartz crucible to 5 rpm or less, diffusion of oxygen atoms contained in the quartz crucible into the silicon melt can be prevented, and the interstitial oxygen concentration in the silicon single crystal can be reduced. it can. Moreover, the variation in resistivity within the silicon single crystal can be reduced by setting the rotation speed of the single crystal to 5 rpm or more.
By setting the above pulling conditions, the interstitial oxygen concentration in the silicon single crystal can be made 8.5 × 10 ¹⁷ atoms / cm ³ or less, thereby preventing the generation of oxygen donors in the IGBT manufacturing process. be able to. If the interstitial oxygen concentration exceeds 8.5 × 10 ¹⁷ atoms / cm ³ , oxygen donors are generated in the IGBT manufacturing process, and the characteristics of the IGBT are changed.

Next, a neutron beam is irradiated to the formed single crystal silicon to which a dopant for adjusting the resistivity is not added. By this neutron beam irradiation, a part of silicon atoms is converted into phosphorus, whereby the single crystal silicon can be uniformly doped with phosphorus, and single crystal silicon with a uniform resistivity can be obtained. The irradiation conditions of the neutron beam may be, for example, irradiation for about 80 hours at a crystal rotation of about 2 rpm at a position where the neutron beam flux is 3.0 × 10 ¹² pieces / cm ² / s ⁻¹ . The silicon ingot thus irradiated with the neutron beam has a resistivity of about 48 Ω · cm to 52 Ω · cm.

  Instead of neutron irradiation, n-type (P, As, Sb, etc.) dopant may be added to the silicon melt in advance. However, since the segregation coefficient is small, the length direction of the silicon single crystal The resistivity changes greatly. In order to prevent such a change in n-type dopant concentration, for example, the above-described DLCZ method, double doping method, or CCZ method may be employed. Furthermore, the crystal rotation speed during single crystal growth may be set to 15 rpm or more in order to suppress variation in resistivity in the wafer plane.

Next, the wafer may be cut out from the single crystal silicon, and lapping or etching may be performed as necessary, and then RTA heat treatment may be performed as necessary.
When lapping, in order to prevent the wafer from cracking, it is preferable to form a front side chamfer at the peripheral edge of the wafer surface and a back side chamfer at the rear peripheral edge of the wafer. FIG. 4 shows a cross section of the wafer peripheral portion after completion of wafer processing.

As shown in FIG. 4, the front surface 22 of the wafer is provided with a main surface 23 that is a flat surface and a surface chamfered portion 24 formed at the peripheral edge. Further, the back surface 26 is provided with a main surface 27 which is a flat surface and a back surface side chamfered portion 28 formed at the peripheral edge. The front side chamfered portion 24 has a width A1 in the direction from the peripheral edge 29 inward in the wafer radial direction, and a width A2 in the direction from the peripheral edge 29 in the backside chamfered portion 28 inward in the wafer radial direction. It is narrowed. The width A1 of the surface chamfer 24 is preferably in the range of 50 μm to 200 μm. Further, the width A2 of the back side chamfer 28 is preferably in the range of 200 μm to 300 μm.
Further, the front side chamfer 24 has the first inclined surface 11 that is inclined with respect to the main surface 23 of the front surface 22, and the back side chamfered portion 28 is the first inclined surface 11 that is inclined with respect to the main surface 27 of the rear surface 26. Two inclined surfaces 12 are provided. The inclination angle θ1 of the first inclined surface 11 is preferably in the range of 10 ° to 50 °, the inclination angle θ2 of the second inclined surface 12 is preferably in the range of 10 ° to 30 °, and θ1 ≦ θ2 is satisfied. preferable.
A first curved surface 13 is provided between the first inclined surface 11 and the peripheral edge 29 to connect them. A second curved surface 14 is provided between the second inclined surface 12 and the peripheral edge 29 to connect them. The range of the radius of curvature R1 of the first curved surface 13 is preferably in the range of 80 μm to 250 μm, and the range of the radius of curvature R2 of the second curved surface 14 is preferably in the range of 100 μm to 300 μm.

Next, a polysilicon layer is formed on one side of the wafer. Since the silicon single crystal wafer of this embodiment has an extremely low interstitial oxygen concentration, the gettering effect due to oxygen precipitates cannot be expected. Therefore, it is necessary to form a polycrystalline silicon layer as a gettering layer on the back surface side to remove heavy metal contamination in the IGBT manufacturing process. Further, by forming the polycrystalline silicon layer on the back surface side, it is possible to prevent the occurrence of slip or the like and prevent the propagation of the slip to the wafer surface side. The thickness of the polysilicon layer is preferably in the range of 50 nm to 2000 nm. If the thickness is 50 nm or more, the gettering effect and the effect of suppressing the occurrence of slip can be sufficiently exerted, and if the thickness is 2000 nm or less, warpage of the wafer can be prevented.
Thus, the silicon single crystal wafer for IGBT of this embodiment can be manufactured.

According to the manufacturing method described above, by introducing a hydrogen atom-containing substance having a hydrogen gas equivalent partial pressure in the range of 40 Pa or more and 400 Pa or less, an allowable width of a speed at which a grown-in defect-free silicon single crystal can be pulled is increased. Thus, a wafer from which COP defects and dislocation clusters are eliminated in the entire crystal diameter direction can be easily manufactured. Also, the silicon single crystal after pulling is irradiated with neutrons to dope phosphorus, or by adding an n-type dopant such as phosphorus to the silicon melt, the variation in resistivity within the wafer surface is 5% or less. Can be. The reduction in resistivity variation can also be achieved by adding phosphorus and a p-type dopant having a segregation coefficient smaller than that of phosphorus to the silicon melt.
Further, by adding nitrogen to the silicon melt, the allowable range of the speed at which the grown-in defect-free silicon single crystal can be pulled can be further increased, and the elimination of COP defects and dislocation clusters in the wafer is facilitated. .

(Silicon single crystal wafer for IGBT)
The silicon single crystal wafer manufactured as described above has COP defects and dislocation clusters eliminated in the entire crystal diameter direction, and the interstitial oxygen concentration is 8.5 × 10 ¹⁷ atoms / cm ³ or less. In-plane resistivity variation is 5% or less. The resistivity itself is about 48 Ω · cm to 52 Ω · cm. Further, the silicon single crystal wafer is doped with nitrogen of 5 × 10 ¹² atoms / cm ³ or more and 5 × 10 ¹⁵ atoms / cm ³ or less.
Furthermore, in the silicon single crystal wafer of this embodiment, the pass rate of TZDB at a breakdown electric field of 8 MV / cm is 90% or more, and the concentration of oxygen donor that precipitates when heat treatment is performed at 450 ° C. for 1 hour is 9 8 × 10 ¹² cm ⁻³ or less, and the density of BMD generated when two-stage heat treatment is performed at 800 ° C. for 4 hours and 1000 ° C. for 16 hours is 5 × 10 ⁷ cm ⁻³ or less. The recombination lifetime in the case of performing the step heat treatment is 100 μsec or more.
Furthermore, in the silicon single crystal wafer of this embodiment, the LPD density of 0.1 μm size or more on the wafer surface is 0.1 piece / cm ² or less, and the light etching defect density is 1 × 10 ³ pieces / cm ^2. It is as follows. Furthermore, in the silicon single crystal wafer of this embodiment, a polycrystalline silicon layer having a thickness of 50 nm or more and 2000 nm or less is formed on the back surface side, and a surface chamfered portion is formed on the peripheral edge of the wafer surface. A back side chamfer is formed on the peripheral edge of the back side.

According to the silicon single crystal wafer for IGBT of this embodiment, COP defects and dislocation clusters are eliminated in the entire crystal diameter direction, and therefore, when the gate oxide film is formed on the wafer surface in the IGBT manufacturing process, COP defects are not generated. The gate oxide film is not taken in, and the GOI is not deteriorated.
Further, since the OSF region is excluded, in the IGBT manufacturing process, there are no oxygen precipitates stable up to a high temperature, no defect is formed in the device active region, and leakage current in the integrated circuit can be prevented. Furthermore, the yield rate can be 90% or higher.
Further, since the Pv region is eliminated, there is no oxygen precipitation nucleus that is stabilized by the low-temperature heat treatment in the IGBT manufacturing process, no defect is formed in the device active region, and leakage current in the integrated circuit can be prevented. Furthermore, the yield rate can be 95% or more.

Further, since the OSF region is excluded and there is no region where the density of OSF is 10 / cm ² or more, COP defects are taken into the gate oxide film when the gate oxide film is formed on the wafer surface in the IGBT manufacturing process. The GOI is not deteriorated. In addition, leakage current in the integrated circuit can be prevented. Furthermore, the yield rate can be 90% or higher.
Further, since the Pv region is excluded and there is no region where the BMD is 1E7 / cm ³ or more when measured by infrared tomography, there is no COP defect when forming a gate oxide film on the wafer surface in the IGBT manufacturing process. The gate oxide film is not taken in, and the GOI is not deteriorated. In addition, leakage current in the integrated circuit can be prevented. Furthermore, the yield rate can be 95% or more.

Furthermore, by eliminating COP defects, dislocation clusters, OSF regions, and Pv regions throughout the crystal diameter direction, the wafer can be suitably used as an IGBT wafer, which is an element that uses the wafer in the vertical direction. That is, since COP defects and dislocation clusters are eliminated, the quality of the bulk of the wafer becomes excellent, and the recombination lifetime, which is an important characteristic for an IGBT wafer, can be improved.
Further, since the interstitial oxygen concentration is 8.5 × 10 ¹⁷ atoms / cm ³ or less, the concentration of oxygen donor generated after the heat treatment of the wafer can be suppressed to 9.8 × 10 ¹² atoms / cm ³ or less. Thus, the change in the resistivity of the wafer can be prevented, and the quality of the silicon single crystal wafer can be stabilized.

Moreover, according to the silicon single crystal wafer of the present invention, since the variation in resistivity within the wafer surface is 5% or less, the quality of the silicon single crystal wafer can be stabilized.
Furthermore, 5 × 10 ¹² atoms / cm ³ or more, 5 × 10 ¹⁵ atoms / cm ³ or less, or 1 × 10 ¹³ atoms / cm ³ or more, 5 × 10 ¹⁴ atoms / cm ³ or less, or 1 × 10 Doping with nitrogen of ¹⁴ atoms / cm ³ or more and 5 × 10 ¹⁵ atoms / cm ³ or less facilitates elimination of COP defects and dislocation clusters. If the doping amount of nitrogen is less than the above range, COP defects and dislocation clusters may not be completely eliminated, and if it exceeds the above range, it becomes difficult to eliminate the OSF region and the Pv region.
In addition, the pass rate of TZDB is 90% or more, the concentration of oxygen donor generated when heat treatment is performed at 450 ° C. for 1 hour, is 9.8 × 10 ¹² cm ⁻³ or less, and 4 hours at 800 ° C. The density of BMD deposited when performing a two-stage heat treatment at 1000 ° C. for 16 hours is 5 × 10 ⁷ cm ⁻³ or less, and the recombination lifetime when performing the two-stage heat treatment is 100 μsec or more. Therefore, the characteristics required for a silicon single crystal wafer for IGBT can be satisfied.

(Experimental example 1)
Silicon ingots having various interstitial oxygen concentrations were produced by the CZ method. Specifically, the polycrystalline silicon lump was put into a quartz crucible, and the polycrystalline silicon lump was heated in an argon atmosphere to obtain a silicon melt. Phosphorus was added as a dopant to the silicon melt. The amount of phosphorus added was adjusted so that the resistivity of the silicon single crystal was 65 Ω · cm. Next, the seed crystal is immersed in the silicon melt while applying a horizontal magnetic field of 3000 G (0.3 T) from the magnetic field supply device so that the center height of the magnetic field is −75 to +50 mm with respect to the melt surface. Then, while rotating the seed crystal and the quartz crucible, the seed crystal was gradually pulled up to grow a single crystal under the seed crystal. The growth rate (pulling rate) of the single crystal is V (mm / min), and the ratio V / G when the temperature gradient G is 1350 ° C. from the melting point during single crystal growth is 0.185. The V was set to 0.49 mm / min. In this way, an ingot of single crystal silicon that was pulled under the pulling conditions of Conditions 1 to 4 was manufactured. The interstitial oxygen concentration in the silicon ingot was controlled by adjusting the rotation speed of the quartz crucible. In condition 4, a silicon wafer with a silicon nitride film was introduced into the silicon melt, thereby doping the silicon single crystal with 4.1 × 10 ¹⁴ atoms / cm ³ of nitrogen.

  Next, the pulled single crystal silicon ingot was sliced to cut out the wafer. The cut wafer was subjected to surface treatment such as lapping and etching. In this way, a silicon single crystal wafer having a diameter of 200 mm and a thickness of 0.75 mm was manufactured.

The obtained silicon single crystal wafer was measured for interstitial oxygen concentration and evaluated for variations in resistivity within the wafer surface. The interstitial oxygen concentration was measured according to the Fourier transform infrared spectrophotometry standardized by ASTM F-121 (1979). In addition, the resistivity variation is measured at a total of three locations, the wafer center, the middle position between the wafer center and outer periphery, and the position 5 mm from the wafer outer periphery, and the maximum and minimum values are selected from the three resistivities. A value was selected and calculated according to the formula “(maximum value−minimum value) × 100 / minimum value”. The results are shown in Table 1.
Further, Table 1 shows the allowable range of the pulling speed. This allowable width is obtained by gradually reducing the pulling rate of the crystal, vertically slicing the crystal in the growth direction, and observing the Grown-in defect distribution by Cu-decoration after X-ray topography. In addition, the pulling speed margin is such that COP defects and dislocation clusters can be eliminated in the entire crystal diameter direction in which dislocation cluster regions are determined by measuring light etching defects.

As shown in Table 1, it was found that the interstitial oxygen concentration can actually be reduced by reducing the crucible rotation speed from 7 rpm to 1 rpm (condition 1 → conditions 2 to 4). However, in conditions 1 and 2, although the crystal rotation speed was slow, the allowable range of the pulling speed could be secured to some extent, but the variation in resistivity was very large.
Further, comparing conditions 2 and 3, in condition 3, the variation in resistivity was reduced by increasing the rotation speed of the crystal, but the allowable range of the pulling speed was greatly reduced. This is presumably because the solid-liquid interface shape between the silicon melt and the single crystal changed due to the increase in the rotation speed of the single crystal.
Furthermore, with respect to the condition 4, the allowable range of the pulling rate was increased by doping nitrogen with respect to the condition 3, but the variation in resistivity was also increased. This is presumably because the convection state of the silicon melt was changed by nitrogen doping.

  From the above, under the pulling conditions of Conditions 1 to 4, it was difficult to simultaneously achieve reduction in interstitial oxygen concentration, reduction in variation in resistivity, and increase in the allowable range of pulling speed.

(Experimental example 2)
Silicon ingots having various interstitial oxygen concentrations were produced by the CZ method. Specifically, the polycrystalline silicon lump was put into a quartz crucible, and the polycrystalline silicon lump was heated in an argon atmosphere to obtain a silicon melt. Next, the seed crystal is immersed in the silicon melt while applying a horizontal magnetic field of 3000 G (0.3 T) from the magnetic field supply device so that the center height of the magnetic field is −75 to +50 mm with respect to the melt surface. Then, while rotating the seed crystal and the quartz crucible, the seed crystal was gradually pulled up to grow a single crystal under the seed crystal. The growth rate (pulling rate) of the single crystal is V (mm / min), and the ratio V / G when the temperature gradient G is 1350 ° C. from the melting point during single crystal growth is 0.185. The V was set to 0.49 mm / min. In this manner, single crystal silicon ingots pulled under the pulling conditions 5 to 14 were manufactured.

The rotation speed of the quartz crucible was 2 rpm under all conditions, and the rotation speed of the single crystal was 20 rpm under all conditions. Furthermore, in conditions 5 and 6, a silicon wafer with a silicon nitride film was introduced into the silicon melt, and nitrogen was doped into the silicon single crystal. Moreover, in conditions 7-11, hydrogen gas was introduce | transduced into argon gas atmosphere and it pulled up on the conditions of hydrogen partial pressure 30-400 Pa. Further, under conditions 12 to 14, nitrogen doping and hydrogen gas introduction were performed simultaneously. Furthermore, in conditions 7-10 and 12-13, the resistivity is adjusted by adding phosphorus to the silicon melt, and in other conditions, neutrons are applied to the single crystal silicon pulled up in the same manner as in Experimental Example 1. Irradiated with rays and doped with phosphorus. Irradiation with neutrons was performed under the condition of irradiation with a bundle of 3.0 × 10 ¹² particles / cm ² / s for 80 hours. In this way, the resistivity of the silicon single crystal was adjusted to 65 Ω · cm.

  Thereafter, a single crystal silicon ingot was sliced to cut out a wafer. The cut wafer was subjected to surface treatment such as lapping and etching. In this way, a silicon single crystal wafer having a diameter of 200 mm and a thickness of 0.75 mm was manufactured.

  For the obtained silicon single crystal wafer, the interstitial oxygen concentration was measured in the same manner as in Experimental Example 1, and the variation in resistivity within the wafer surface was evaluated. The results are shown in Table 2. Table 2 also shows the nitrogen concentration in the wafer, the hydrogen partial pressure in the atmosphere of the CZ furnace, and the conditions for the dopant introduction method. Further, similarly to Experimental Example 1, the allowable range of the pulling speed is shown at the same time.

As shown in Tables 1 and 2, the variation in resistivity deteriorated by nitrogen doping in condition 4 was improved by performing phosphorous doping by neutron irradiation as shown in conditions 5 and 6, but the allowable range of pulling rate Was not enough.
In addition, the allowable range of the pulling rate that was reduced by increasing the rotation speed of the crystal in Condition 3 was improved by introducing hydrogen into the atmosphere as shown in Conditions 8-10. As in conditions 8 to 10, while introducing a predetermined amount of hydrogen and controlling the crucible rotation speed and the single crystal rotation speed, the interstitial oxygen concentration is reduced, the variation in resistivity is reduced, and the pulling speed is increased. It has been found that an increase in the allowable range can be realized at the same time.
Also, the variation in resistivity increased by nitrogen doping in condition 4 was improved by introducing hydrogen into the atmosphere as shown in conditions 12 and 13. This is considered to be because the change in the convection state of the silicon melt caused by nitrogen doping was suppressed by introducing hydrogen. Moreover, in conditions 12 and 13, the allowable range of the pulling rate could be expanded as compared with the case of nitrogen doping alone (conditions 5 to 6) and hydrogen introduction alone (conditions 7 to 11).
Furthermore, with respect to these conditions 12 and 13, in the condition 14 in which phosphorus was introduced by neutron irradiation, the variation in resistivity was further reduced.

(Experimental example 3)
First, an n-type (50 Ω · cm) wafer having a diameter of 200 mm manufactured according to the conditions of Experimental Example 1 was subjected to a heat treatment simulating the IGBT manufacturing process shown in Table 3. Thereafter, B (boron) ion implantation of 2 × 10 ¹⁵ atoms / cm ³ was performed at 30 keV, and drive-in was performed under the conditions of 1000 ° C. × 1 h to form a p / n junction. The diffusion depth is about 2 μm. The electrode area is 1 cm ³ . Table 4 shows the results of evaluating a non-defective product rate by determining that a chip having a leakage current of 100 μA or more when 1000 V is applied is defective.

  From this result, as in Experimental Examples B, C, E, F, H, and J, in order to obtain a wafer with a non-defective rate of 90% or more, it is a Pv + Pi region, that is, a V region, an OSF region, It is necessary to exclude the I region, and as in Experimental Examples C, F, and J, in order to obtain a wafer having a non-defective rate of 95% or more, only the Pi region is required, that is, the V region, the OSF. It can be seen that it is necessary to exclude the region, the Pv region, and the I region.

  It is possible to provide a method for manufacturing a silicon single crystal wafer for IGBT and a silicon single crystal wafer for IGBT capable of expanding a pulling speed margin and manufacturing a wafer having a small variation in resistivity.

Claims (10)

An IGBT silicon single crystal wafer made of a silicon single crystal grown by the Czochralski method, which eliminates COP defects, dislocation clusters, and OSF regions throughout the crystal diameter direction, and has an interstitial oxygen concentration of 8. A silicon single crystal wafer for IGBT having a resistivity of 5 × 10 ¹⁷ atoms / cm ³ or less and a variation in resistivity within the wafer surface of 5% or less.   When the silicon single crystal is grown by the Czochralski method, it is grown at a pulling speed capable of pulling up the silicon single crystal capable of eliminating COP defects, dislocation clusters and OSF regions in the entire crystal diameter direction. 2. The silicon single crystal wafer for IGBT according to claim 1, wherein the silicon single crystal after being pulled is irradiated with neutrons and doped with phosphorus. A silicon single crystal wafer for IGBT composed of a silicon single crystal grown by the Czochralski method, in which COP defects, dislocation clusters, OSF regions and Pv regions are excluded in the entire crystal diameter direction, and the interstitial oxygen concentration A silicon single crystal wafer for IGBT, characterized in that is 8.5 × 10 ¹⁷ atoms / cm ³ or less and variation in resistivity within the wafer surface is 5% or less.   When the silicon single crystal was grown by the Czochralski method, it was grown at a pulling speed capable of pulling up the silicon single crystal capable of eliminating COP defects, dislocation clusters, OSF regions, and Pv regions in the entire crystal diameter direction. 4. The silicon single crystal wafer for IGBT according to claim 3, wherein the silicon single crystal after being pulled is irradiated with neutrons and doped with phosphorus. 5. The IGBT according to claim 1, wherein the silicon single crystal is doped with nitrogen of 5 × 10 ¹² atoms / cm ^{3 to} 5 × 10 ¹⁵ atoms / cm ^3. Silicon single crystal wafer for use. This is a method for producing a silicon single crystal wafer for IGBT obtained by growing a silicon single crystal by the Czochralski method, and the hydrogen gas equivalent partial pressure in the atmosphere gas in the CZ furnace is in the range of 40 Pa or more and 400 Pa or less. By introducing a hydrogen atom-containing substance, the pulling rate of the silicon single crystal is such that the silicon single crystal capable of removing COP defects, dislocation clusters, and OSF regions in the entire crystal diameter direction can be pulled, and the interstitial oxygen concentration is 8.5. A method for producing a silicon single crystal wafer for IGBT, comprising growing a single crystal of × 10 ¹⁷ atoms / cm ³ or less and irradiating the pulled silicon single crystal with neutrons to dope phosphorus. This is a method for producing a silicon single crystal wafer for IGBT obtained by growing a silicon single crystal by the Czochralski method, and the hydrogen gas equivalent partial pressure in the atmosphere gas in the CZ furnace is in the range of 40 Pa or more and 400 Pa or less. By introducing a hydrogen atom-containing substance, the pulling speed of the silicon single crystal is such that the silicon single crystal capable of removing COP defects, dislocation clusters, OSF regions, and Pv regions in the entire crystal diameter direction can be pulled, and the interstitial oxygen concentration is A method for producing a silicon single crystal wafer for IGBT, comprising growing a single crystal of 8.5 × 10 ¹⁷ atoms / cm ³ or less and doping the silicon single crystal after pulling with neutron irradiation to dope phosphorus. A method for producing a silicon single crystal wafer for IGBT obtained by growing a silicon single crystal by the Czochralski method, wherein an n-type dopant is added to a silicon melt, and hydrogen gas is converted into an atmospheric gas in a CZ furnace. Introducing a hydrogen atom-containing substance with a partial pressure in the range of 40 Pa or more and 400 Pa or less, and the silicon single crystal capable of eliminating the COP defects, dislocation clusters, and OSF regions can be pulled up in the entire crystal diameter direction of the silicon single crystal. A method for producing a silicon single crystal wafer for IGBT, comprising growing a single crystal having an interstitial oxygen concentration of 8.5 × 10 ¹⁷ atoms / cm ³ or less at a speed. A method for producing a silicon single crystal wafer for IGBT obtained by growing a silicon single crystal by the Czochralski method, wherein an n-type dopant is added to a silicon melt, and hydrogen gas is converted into an atmospheric gas in a CZ furnace. A silicon single crystal capable of eliminating a COP defect, a dislocation cluster, an OSF region, and a Pv region by introducing a hydrogen atom-containing substance having a partial pressure in a range of 40 Pa or more and 400 Pa or less and increasing the pulling speed of the silicon single crystal in the entire crystal diameter direction A method for producing a silicon single crystal wafer for IGBT, comprising growing a single crystal having an interstitial oxygen concentration of 8.5 × 10 ¹⁷ atoms / cm ³ or less at a pullable speed. The nitrogen is added to the silicon single crystal at a concentration of 5 × 10 ¹² atoms / cm ³ or more and 5 × 10 ¹⁵ atoms / cm ³ or less. Of manufacturing a silicon single crystal wafer for IGBT.

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