JP4259708B2 - Manufacturing method of SOI substrate - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing an SOI (Silicon-On-Insulator) substrate in which a silicon layer is formed on an insulating layer. More specifically, the present invention relates to a method for manufacturing an SOI substrate using SIMOX (Separation by IMplanted Oxygen) technology.
[0002]
[Prior art]
The SIMOX method is known as one of methods for manufacturing an SOI substrate. In the SIMOX method, after implanting oxygen ions from the surface of a silicon wafer, an annealing process is performed to form a buried silicon oxide layer in a region at a predetermined depth from the wafer surface, so that single crystal silicon is formed on the buried silicon oxide layer. An SOI substrate having a layer (hereinafter referred to as an SOI layer) is obtained.
The silicon wafer into which oxygen ions are implanted is a wafer made by the Czochralski (hereinafter referred to as CZ) method, and there are usually particles originating from crystals (Crystal Originated Particles, hereinafter referred to as COP). . This COP is a pit caused by crystals that appear on the wafer surface when the silicon wafer after mirror polishing is washed with a mixed solution of ammonia and hydrogen peroxide. When this wafer is measured with a particle counter, this pit is also detected as a light scattering defect together with the original particles.
[0003]
[Problems to be solved by the invention]
When an SOI substrate is manufactured using a CZ silicon wafer in which such a COP exists, the HF defect density increases. The HF defect means that the buried oxide film is locally eroded when the SOI substrate is subjected to HF processing, and is usually visually recognized as an etching pit after the HF processing. In the device process, the HF treatment for the substrate is generally indispensable. However, since the buried oxide film is not exposed to the substrate surface except for the end portion as the name indicates, the buried oxide film itself does not come into contact with the HF, that is, at all. It is not affected by. However, for example, when there is a hole (for example, COP) that opens on the surface of the substrate and reaches the buried oxide film, HF flows in from this and erodes the buried oxide film, causing a defect in the element formed at this portion. .
[0004]
In order to improve this point, it has been proposed to manufacture an SOI substrate by implanting oxygen ions from the surface of the epitaxial layer using a silicon wafer in which thin epitaxial layers are stacked. This increases the number of steps for forming the substrate and increases the cost of the SOI substrate, which is not suitable for commercial mass production of the SOI substrate.
[0005]
An object of the present invention is to provide a manufacturing method capable of mass-producing an SOI substrate having a small HF defect density without increasing the number of steps.
[0006]
[Means for Solving the Problems]
In the invention according to claim 1, as shown in FIG. 1, after implanting oxygen ions from the surface of the silicon wafer 11, the silicon wafer 11 is annealed to be buried to a predetermined depth from the wafer surface. In the method of manufacturing the SOI substrate 10 for forming the silicon substrate 11, when the silicon wafer 11 has an ingot pulling rate V and the temperature gradient of the contact surface of the ingot-silicon melt is G in a hot zone structure, the pulling rate V with respect to the temperature gradient G The ratio of V (G / G) is equal to or higher than the first critical ratio ((V / G) ₁ ) for preventing the generation of interstitial silicon type point defect aggregates. Pull the ingot from the silicon melt in the hot zone furnace so that it is maintained below the second critical ratio ((V / G) ₂ ), which limits it to the region where vacant point defects are dominant Under Agglomerate vacancy type point defects sliced central from the ingot without any, and Ri Oh the wafer no agglomerate of interstitial silicon type point defects in the edge portion, aggregates of the silicon wafer 11 is the point defect when the detection limit as 1 × 10 ³ cells / cm ^3, Ri number der following the detection limit of the aggregate of point defects, and the annealing 1350 ° C., by the 4 h, HF It is characterized in that an SOI substrate having a defect density of 0.1 / cm ² is mass-produced without increasing the number of processes .
According to the first aspect of the present invention, since there are almost no point defect aggregates, the HF defect density of the SOI layer caused by COP can be reduced.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
The silicon wafer of the present invention is produced by slicing an ingot from a silicon melt in a hot zone furnace with a predetermined pulling speed profile based on Boronkov theory by the CZ method.
In general, when a silicon single crystal ingot is pulled from a silicon melt in a hot zone furnace by the CZ method, point defects and agglomerates (agglomerates: three-dimensional) Defect) occurs. There are two general forms of point defects: vacancy-type point defects and interstitial silicon-type point defects. A vacancy-type point defect is one in which one silicon atom leaves one of the normal positions in the silicon crystal lattice. Such holes become hole-type point defects. On the other hand, when an atom is found at a position (interstitial site) other than the lattice point of the silicon crystal, this becomes an interstitial silicon point defect.
[0008]
Point defects are generally formed at the contact surface between a silicon melt (molten silicon) and an ingot (solid silicon). However, by continuously pulling up the ingot, the portion that was the contact surface begins to cool as it is pulled up. During cooling, vacancy point defects or interstitial silicon point defects merge with each other by diffusion to form vacancy agglomerates or interstitial agglomerates. Is formed. In other words, the aggregate is a three-dimensional structure generated due to the merge of point defects.
[0009]
Agglomerates of vacancy-type point defects include defects called LSTD (Laser Scattering Tomograph Defects) or FPD (Flow Pattern Defects) in addition to the above-mentioned COP. Interstitial silicon-type point defect aggregates are interstitial dislocations ( Interstitial-type Large Dislocation (hereinafter referred to as LD)). FPD is a source of traces that show a unique flow pattern that appears when a silicon wafer produced by slicing an ingot is chemically etched with a Secco etchant for 30 minutes. This is a source having a refractive index different from that of silicon when irradiated with infrared rays. Furthermore, LD is also called a dislocation cluster, or a pit is formed when a silicon wafer having such a defect is immersed in a selective etching solution containing hydrofluoric acid as a main component.
[0010]
Boronkov's theory is that in order to grow a high-purity ingot with a small number of defects, the ingot pulling speed is V (mm / min), and the temperature gradient at the contact surface of the ingot-silicon melt is G (° C. in a hot zone structure. / Mm), V / G (mm ² / min · ° C.) is controlled. In this theory, as shown in FIG. 2, V / G is taken as the horizontal axis, and the vacancy-type point defect concentration and the interstitial silicon type point defect concentration are set to the same vertical axis. The relationship is represented schematically, and it is explained that the boundary between the void region and the interstitial silicon region is determined by V / G. More specifically, an ingot having an increased vacancy point defect concentration is formed when the V / G ratio is higher than the critical point, whereas an ingot having an increased interstitial silicon point defect concentration is formed when the V / G ratio is lower than the critical point. It is formed. In FIG. 2, [I] indicates a region where the interstitial silicon type point defect is dominant and an interstitial silicon type point defect exists ((V / G) ₁ or less), and [V] is in the ingot. The vacancy-type point defect is dominant and indicates a region ((V / G) ₂ or more) where the vacancy-type point defect aggregate exists, [P] A perfect region ((V / G) ₁ to (V / G) ₂ ) in which an aggregate of interstitial silicon type point defects does not exist is shown. In the region [V] adjacent to the region [P], there are regions ((V / G) ₂ to (V / G) ₃ ) that form OSF nuclei. Here, OSF means an oxidation induced stacking fault (Oxidation Induced Stacking Fault). Oxygen precipitate micro-defects that become OSF nuclei are introduced during crystal growth, and are manifested in a thermal oxidation process when manufacturing semiconductor devices. This causes a defect such as an increase in leakage current of the manufactured device.
[0011]
The predetermined pulling rate profile of the present invention shows that when the ingot is pulled from the silicon melt in the hot zone furnace, the ratio of the pulling rate to the temperature gradient (V / G) indicates the formation of agglomerates of interstitial silicon type point defects. The first critical ratio to be prevented ((V / G) ₁ ) or higher, and the agglomeration of vacancy-type point defects is limited to a region where the vacancy-type point defects in the center of the ingot are dominantly present. It is determined so as to be maintained below the two critical ratio ((V / G) ₂ ).
[0012]
The pulling speed profile is determined based on the above-mentioned Boronkov theory by simulation by slicing a reference ingot in the axial direction experimentally or by combining these techniques. That is, this determination is made by checking the axial slice of the ingot and the sliced wafer after the simulation, and further repeating the simulation. For the simulation, a plurality of types of pulling speeds are determined within a predetermined range, and a plurality of reference ingots are grown. As shown in FIG. 3, the pulling speed profile for the simulation is from a high pulling speed (a) such as 1.2 mm / min to a low pulling speed (c) of 0.5 mm / min and again a high pulling speed (d). Adjusted to The low pulling speed may be 0.4 mm / min or less, and the change in pulling speeds (b) and (d) is preferably linear.
[0013]
A plurality of reference ingots, pulled at different speeds, are each sliced axially. The optimal V / G is determined from the correlation between the axial slice, wafer verification and simulation results, and then the optimal pulling speed profile is determined and the ingot is manufactured with that profile. The actual pull rate profile will depend on many variables including, but not limited to, the desired ingot diameter, the particular hot zone furnace used and the quality of the silicon melt.
[0014]
Drawing the cross-sectional view of the ingot when the pulling speed is gradually reduced and V / G is continuously reduced, the fact shown in FIG. 4 can be seen. FIG. 4 shows a region [V] in which vacancy-type point defects exist predominantly in the ingot, [I], a region in which interstitial silicon-type point defects dominate, and vacancy-type point defects. A perfect region where no agglomerates and no agglomerates of interstitial silicon type point defects exist is indicated as [P]. As shown in FIG. 4, the axial position P ₁ of the ingot includes a region where a hole-type point defect is dominantly present at the center. The position P ₃ includes a ring region in which an interstitial silicon type point defect exists dominantly and a perfect region in the center. Further, the position P ₂ is a perfect region because there is no aggregate of void type point defects in the center related to the present invention and no aggregate of interstitial silicon type point defects in the edge portion.
[0015]
As is apparent from FIG. 4, the wafer W ₁ corresponding to the position P ₁ includes a region where a vacancy-type point defect exists predominantly in the center. The wafer W ₃ corresponding to the position P ₃ includes a ring in which interstitial silicon type point defects exist predominantly and a central perfect region. Further, the wafer W ₂ corresponding to the position P ₂ is a wafer according to the present invention, and there is no agglomeration of vacancy type point defects in the center and no agglomeration of interstitial silicon type point defects at the edge part. Perfect area. A slight region ((V / G) ₂ to (V / G) _{3 in} FIG. 2) in contact with the perfect region of the region where the vacancy-type point defects exist dominantly generates COP and LD within the wafer surface. It is an area that is not. However, this silicon wafer W ₁ was heat-treated at a temperature of 1000 ° C. ± 30 ° C. for 2 to 5 hours in an oxygen atmosphere according to the conventional OSF clarification heat treatment, and subsequently ₁ to 1130 ° C. ± 30 ° C. Heat treatment for 16 hours produces OSF. As shown in FIG. 5, in the wafer W ₁ , an OSF ring is generated in the vicinity of ½ of the wafer radius. COP tends to appear in the region where the vacancy-type point defects surrounded by the OSF ring are dominant.
[0016]
In addition, since agglomerates of point defects such as COP and LD may show different values in detection sensitivity and detection lower limit depending on the detection method, in this specification, mirror-finished silicon single crystals are etched without stirring. When the product of the observation area and the etching allowance is observed as an inspection volume with an optical microscope after application, each aggregate of flow pattern (vacancy type defects) and dislocation clusters (interstitial silicon type point defects) is 1 × The case where one defect is detected for an inspection volume of 10 ⁻³ cm ³ is defined as a detection lower limit (1 × 10 ³ / cm ³ ).
[0017]
In the SIMOX method of the present invention, the above-described wafer W _{2 in} which the number of point defect aggregates is equal to or less than the detection lower limit value is used. As shown in FIG. 1, in this method, oxygen ions are applied to a predetermined region from the surface of the silicon wafer 11 heated to 500 to 650 ° C., an acceleration voltage of 50 to 200 keV, and a dose (implantation amount) of 2 × 10 ¹⁷ to 2 ×. Implantation is performed at about 10 ¹⁸ / cm ² (FIG. 1A). Next, annealing is performed for about 5 hours in a mixed gas atmosphere of Ar and O ₂ or N ₂ and O ₂ at a high temperature of 1300 ° C. or higher, and the buried silicon oxide layer 12 is reacted by the reaction between oxygen and silicon implanted in a predetermined region. Is formed (FIG. 1B). Since the wafer W ₂ is an extremely high quality wafer having the number of point defect aggregates below the detection lower limit, the SOI substrate 10 comprising the SOI layer 13 and the embedded silicon oxide layer 12 inside the wafer is produced by the above method. As a result, an SOI layer having a very low HF defect density can be obtained.
[0018]
【Example】
Next, examples of the present invention will be described together with comparative examples.
<Example 1>
4 is a region corresponding to the position P ₂ shown in FIG. 4 from the silicon melt obtained by melting the raw material polycrystalline silicon, and V / G shown in FIG. 2 is (V / G) ₁ or more (V / G G) Raised the ingot so that it entered the area below ₂ . The silicon wafer sliced from the pulled ingot was lapped and chamfered, and then the wafer surface damage was removed by chemical etching to obtain a mirror silicon wafer having a thickness of 625 μm.
As shown in FIG. 1A, this silicon wafer 11 is heated to 500 to 650 ° C., and in this state, a predetermined region of the wafer 11 (for example, a region of about 0.47 μm from the substrate surface) is subjected to the following conditions. Oxygen ions (O ⁺ ) were implanted.
Accelerating voltage: 190 keV
Beam current: 50 mA
Dose amount: 1.6 × 10 ¹⁸ / cm ²
After the ion implantation, the wafer 11 is annealed at 1350 ° C. for 4 hours in a mixed gas atmosphere of Ar and O ₂ as shown in FIG. In other words, an SOI substrate 10 was obtained. Reference numeral 13 denotes an SOI layer.
[0019]
<Comparative Example 1>
In the region where the ingot total length corresponds to the position P ₁ shown in FIG. 4 from the silicon melt obtained by melting the raw material polycrystalline silicon, the V / G shown in FIG. 2 is in the region where (V / G) ₂ or more. Raised the ingot to enter. The silicon wafer sliced from the pulled ingot was lapped and chamfered, and then the wafer surface damage was removed by chemical etching to obtain a mirror silicon wafer having a thickness of 625 μm.
An SOI substrate was obtained from this silicon wafer in the same manner as in Example 1.
[0020]
<Comparison evaluation>
For each of the SOI substrates of Example 1 and Comparative Example 1, the HF defect density in the SOI layer was measured by the following method. That is, samples collected from each SOI substrate were immersed in 50% HF for 10 minutes, then pulled up, and etching pits caused by defects were observed with an optical microscope, and the density was determined. As a result, it was 0.3 pieces / cm ² in Comparative Example 1, whereas it was 0.1 pieces / cm ² in Example 1, and etching pits caused by defects in the SOI layer of Example 1 It can be seen that the density is extremely low.
[0021]
【The invention's effect】
As described above, according to the present invention, since the silicon wafer has almost no agglomerates of point defects, the HF defect density of the SOI layer of the SOI substrate can be reduced. In addition, the SOI substrate can be mass-produced without increasing the number of steps as compared with an SOI substrate made from a silicon wafer on which conventional thin film epitaxial layers are stacked.
[Brief description of the drawings]
FIG. 1 is a partial cross-sectional view illustrating a method for manufacturing an SOI substrate according to the present invention.
FIG. 2 Based on Boronkov's theory, an ingot in which vacancy-type point defects predominate is formed when the V / G ratio is higher than the critical point, and interstitial silicon type defects predominate when the V / G ratio is lower than the critical point. The figure which shows that an ingot is formed.
FIG. 3 is a characteristic diagram showing a change in pulling speed for determining a desired pulling speed profile.
FIG. 4 is a schematic view of an X-ray topography showing a region where a vacancy type point defect exists predominantly, a region where an interstitial silicon type point defect exists predominantly, and a perfect region of the reference ingot according to the present invention.
5 is a view showing a situation in which an OSF ring appears on a silicon wafer W ₁ corresponding to a position P ₁ in FIG. 4;
[Explanation of symbols]
10 SOI substrate 11 Silicon wafer 12 Embedded silicon oxide layer 13 SOI layer

Claims (1)

A method for manufacturing an SOI substrate in which oxygen ions are implanted from the surface of a silicon wafer (11), and then the silicon wafer (11) is annealed to form a buried silicon oxide layer (12) at a predetermined depth from the wafer surface. In
When the silicon wafer 11 has an ingot pulling speed V and the temperature gradient of the contact surface of the ingot-silicon melt is G in a hot zone structure, the ratio of the pulling speed V to the temperature gradient G (V / G ) Is more than the first critical ratio ((V / G) ₁ ) to prevent the formation of interstitial silicon type point defect aggregates, and the hole type point defect aggregates are in the center of the ingot. The ingot is pulled from the silicon melt in the hot zone furnace so that it is maintained below the second critical ratio ((V / G) ₂ ), which limits it to the dominant region, and is sliced from the ingot to the center. agglomerate of vacancy type point defects without and Ri Oh the wafer no agglomerate of interstitial silicon type point defects in the edge portion,
When the silicon wafer (11) to the detection limit of the aggregate of point defects and 1 × 10 ³ cells / cm ^3, Ri numbers the detection limit der following aggregates of the point defects, and, the A method for manufacturing an SOI substrate, characterized by mass-producing SOI substrates having an HF defect density of 0.1 / cm ² without increasing the number of steps by annealing at 1350 ° C. for 4 hours .

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