JP4124151B2 - IG wafer manufacturing method - Google Patents

Description

  The present invention provides an intrinsic getter from a silicon wafer cut from a silicon single crystal ingot pulled up by the Czochralski method (hereinafter referred to as CZ method) in order to obtain a silicon wafer suitable for a semiconductor integrated circuit such as a DRAM. The present invention relates to a method for manufacturing a ring (intrinsic gettering, hereinafter referred to as IG) wafer.

  In recent years, in the process of manufacturing a semiconductor integrated circuit, as a cause of decreasing the yield, microscopic defects of oxygen precipitates that are the core of oxidation-induced stacking faults (hereinafter referred to as OSF) and particles caused by crystals (Crystal Originated Particles, hereinafter referred to as COP) or the presence of interstitial-type large dislocation (hereinafter referred to as LD). OSF is introduced with a micro defect that becomes a nucleus during crystal growth, and becomes apparent in a thermal oxidation process or the like when manufacturing a semiconductor device, and causes a defect such as an increase in leakage current of the manufactured device. COPs are pits caused by crystals that appear on the wafer surface when the mirror-polished silicon wafer is washed with a mixture of ammonia and hydrogen peroxide. When this wafer is measured with a particle counter, this pit is also detected as a light scattering defect together with the original particles. This COP causes deterioration of electrical characteristics, for example, dielectric breakdown characteristics (Time Dependent dielectric Breakdown, TDDB) of oxide films, oxide breakdown voltage characteristics (Time Zero Dielectric Breakdown, TZDB), and the like. Further, if COP exists on the wafer surface, a step is generated in the device wiring process, which may cause disconnection. In addition, the element isolation portion also causes leakage and the like, thereby reducing the product yield. Furthermore, LD is also called a dislocation cluster, or a pit is formed when a silicon wafer having such a defect is immersed in a selective etching solution containing hydrofluoric acid as a main component. This LD also causes deterioration of electrical characteristics such as leakage characteristics and isolation characteristics.

From the above, it is necessary to reduce OSF, COP and LD from a silicon wafer used for manufacturing a semiconductor integrated circuit.
A defect-free silicon wafer having no OSF, COP, and LD is disclosed (for example, see Patent Document 1). This defect-free silicon wafer has a perfect region [P] where a perfect region where agglomerates of vacancy-type point defects and agglomerates of interstitial silicon-type point defects do not exist in a silicon single crystal ingot, respectively. P] is a silicon wafer cut out from an ingot. The perfect region [P] is between a region [I] where interstitial silicon type point defects exist predominantly and a region [V] where hole type point defects exist predominantly within the silicon single crystal ingot. Intervene. In the silicon wafer composed of the perfect region [P], the ingot pulling speed is V (mm / min), and the temperature gradient in the ingot vertical direction in the vicinity of the interface between the silicon melt and the ingot is G (° C./mm). When the thermal oxidation treatment is performed, a value of V / G (mm ² / min · ° C.) is determined so that the OSF generated in a ring shape disappears in the center of the wafer.

However, although the silicon wafer cut out from the ingot composed of the perfect region [P] does not have OSF, COP, and LD, oxygen precipitation does not necessarily occur inside the wafer in the heat treatment of the device manufacturing process. The IG effect may not be sufficiently obtained. When a wafer that does not have sufficient IG capability is contaminated with metal in the device process, junction leakage, device malfunction due to trap levels caused by metal impurities, and the like, resulting in a decrease in product yield.
Conventionally, a process of introducing an oxygen precipitation nucleus into a wafer by holding a silicon wafer cut out from a silicon single crystal ingot immediately after grinding and polishing at 500 to 800 ° C. for 0.5 to 20 hours, and this oxygen precipitation nucleus A step of rapidly heating a silicon wafer containing a temperature from 800 to 1000 ° C. and holding it for 0.5 to 20 minutes, and a step of further cooling the silicon wafer that has been rapidly heated and held for 0.5 to 20 minutes to room temperature In addition, an IG treatment method including a step of heating a cooled silicon wafer from 500 to 700 ° C. to 800 to 1100 ° C. at a rate of 2 to 10 ° C./min and holding at that temperature for 2 to 48 hours has been proposed ( For example, see Patent Document 2.)

In this treatment method, when heated rapidly under the above temperature conditions, not only the wafer surface but also the inside of the wafer temporarily falls below the thermal equilibrium concentration, the interstitial silicon atoms become deficient, and the oxygen precipitate nuclei are likely to grow stably. become. At the same time, since the deficient interstitial silicon atoms are compensated to become stable, interstitial silicon atoms are generated on the wafer surface, and the generated interstitial silicon atoms begin to diffuse into the wafer. The vicinity of the wafer surface, which was in a deficient state of interstitial silicon atoms, is immediately saturated by the generation of interstitial silicon atoms, and the oxygen precipitation nuclei begin to disappear. However, since it takes a certain amount of time for the interstitial silicon atoms generated on the wafer surface to diffuse into the wafer, the environment in which oxygen precipitation nuclei easily grow longer as the wafer enters deeper from the wafer surface. Therefore, the closer to the wafer surface, the lower the density of oxygen precipitation nuclei, and the longer this heat treatment time (0.5 to 20 minutes), the thicker the oxygen precipitation nuclei, that is, the layer in which no defects are formed (hereinafter referred to as DZ layer). It gets bigger. Further, the higher the temperature is in the range of 800 to 1000 ° C., the larger the diffusion coefficient of interstitial silicon atoms, and the greater the thickness of the DZ layer is in a short time.
When rapidly heated and allowed to cool to room temperature and then heated again to 800 to 1100 ° C., oxygen precipitation nuclei inside the wafer that survived the rapid heating grow to become oxygen precipitates, which become a stable IG source.
Japanese Patent Application Laid-Open No. 11-1393 JP-A-8-45945

However, in the IG processing method, as a pretreatment for generating the IG source, the silicon wafer immediately after grinding and polishing is held at 500 to 800 ° C. for 0.5 to 20 hours to introduce oxygen precipitation nuclei into the wafer. A process was required, and after rapid heating, a heat treatment was required to grow oxygen precipitate nuclei inside the wafer into oxygen precipitates. For this reason, there has been a problem that the number of heat treatments in the wafer state is large.
An object of the present invention is to provide a method for producing a wafer that exhibits a desired IG effect by reducing the number of heat treatments in the state of a silicon wafer in addition to the absence of agglomerates of point defects .

According to the first aspect of the present invention, when the OSF revealing heat treatment is performed, OSF is generated in a disk shape at an area of 25% or more of the total area of the wafer at the center of the wafer, and 1 × A silicon wafer which is generated at a density of 10 ^{5 to} 3 × 10 ⁷ pieces / cm ² and which is free of COP and free of LD is heated from room temperature to 1100 to 1250 ° C. in an atmosphere containing hydrogen gas or hydrogen gas at 3 ° C. This is a method for producing an IG wafer that is rapidly heated at a temperature elevation rate of 1 minute to 150 ° C./second and held for 1 minute to 2 hours.
In the invention according to claim 1, by using a wafer containing oxygen precipitates having a predetermined density in the OSF region existing in the above ratio as the wafer, a pre-heat treatment step of introducing oxygen precipitation nuclei into the conventional wafer and oxygen precipitation A nucleus growth step is not required, and a high IG effect is exhibited by rapidly heating the polished wafer under the above conditions.

請 Motomeko 1 IG wafer made of the described methods, the layer is not formed of the oxygen precipitates (DZ layer) is formed over 1~100μm depth from the wafer surface, 2 × 10 deeper portion than the DZ layer ⁴ has characteristics that have a to 2 × 10 ⁸ pieces / cm ² of oxygen precipitates, exhibits high IG effect.

  As described above, according to the invention according to claim 1, in addition to the absence of agglomerates of point defects, a wafer that exhibits a desired IG effect by reducing the number of heat treatments in a silicon wafer state. Obtainable.

The silicon wafer of the present invention is produced by slicing an ingot from a silicon melt in a hot zone furnace with a predetermined pulling speed profile based on Boronkov theory by the CZ method.
In general, when a silicon single crystal ingot is pulled from a silicon melt in a hot zone furnace by the CZ method, point defects and agglomerates (agglomerates: three-dimensional) Defect) occurs. There are two general forms of point defects: vacancy-type point defects and interstitial silicon-type point defects. A vacancy-type point defect is one in which one silicon atom leaves one of the normal positions in the silicon crystal lattice. Such holes become hole-type point defects. On the other hand, when an atom is found at a position (interstitial site) other than the lattice point of the silicon crystal, this becomes an interstitial silicon point defect.

  Point defects are generally formed at the contact surface between a silicon melt (molten silicon) and an ingot (solid silicon). However, by continuously pulling up the ingot, the portion that was the contact surface begins to cool as it is pulled up. During cooling, vacancy point defects or interstitial silicon point defects merge with each other by diffusion to form vacancy agglomerates or interstitial agglomerates. Is formed. In other words, the aggregate is a three-dimensional structure generated due to the merge of point defects.

The agglomerates of vacancy-type point defects include defects called LSTD (Laser Scattering Tomograph Defects) or FPD (Flow Pattern Defects) in addition to the above-mentioned COP. Contains a defect called. FPD means when a silicon wafer produced by slicing an ingot is subjected to secco etching (Secco etching, etching with a mixed solution of HF: K ₂ Cr ₂ O ₇ (0.15 mol / l) = 2: 1). LSTD is a source that generates a scattered light having a refractive index different from that of silicon when an infrared ray is irradiated into a silicon single crystal.

Boronkov's theory is that in order to grow a high-purity ingot with a small number of defects, the ingot pulling speed is V (mm / min), and the temperature gradient at the contact surface of the ingot-silicon melt is G (° C. in a hot zone structure. / Mm), V / G (mm ² / min · ° C.) is controlled. In this theory, as shown in FIG. 1, V / G is taken as the horizontal axis, and V / G and point defect concentration are set to the same vertical axis for the vacancy type point defect concentration and the interstitial silicon type point defect concentration. The relationship is represented schematically, and it is explained that the boundary between the void region and the interstitial silicon region is determined by V / G. More specifically, when the V / G ratio is equal to or higher than the critical point, an ingot having a dominant vacancy-type point defect concentration is formed. On the other hand, when the V / G ratio is lower than the critical point, an ingot having a dominant interstitial silicon-type point defect concentration is formed. It is formed. In FIG. 1, [I] indicates a region where an interstitial silicon type point defect is dominant and an interstitial silicon type point defect exists ((V / G) ₁ or less), and [V] indicates an ingot. The vacancy-type point defect is dominant and indicates a region ((V / G) ₂ or more) where the vacancy-type point defect aggregate exists, [P] A perfect region ((V / G) ₁ to (V / G) ₂ ) in which an aggregate of interstitial silicon type point defects does not exist is shown. A region [OSF] ((V / G) ₂ to (V / G) ₃ ) that forms an OSF nucleus exists in the region [V] adjacent to the region [P].

In addition, agglomerates of point defects such as COP and LD may show different values for detection sensitivity and detection lower limit depending on the detection method. Therefore, in this specification, the meaning of “there is no agglomeration of point defects” means that the product of the observation area and the etching allowance is measured by an optical microscope after the mirror-finished silicon single crystal is subjected to non-stirring secco etching. Is observed as an inspection volume, each aggregate of flow pattern (vacancy type defects) and dislocation clusters (interstitial silicon type point defects) has one defect for the inspection volume of 1 × 10 ⁻³ cm ^3. When the detected case is defined as a detection lower limit (1 × 10 ³ pieces / cm ³ ), it means that the number of point defect aggregates is not more than the above detection lower limit.
The perfect region [P] is further classified into a region [P _I ] and a region [P _V ]. [P _I ] is a region where the V / G ratio is from the above (V / G) ₁ to the critical point, and [P _V ] is a region where the V / G ratio is from the critical point to the above (V / G) _2. is there. That is, [P _I ] is a region adjacent to the region [I] and having an interstitial silicon type point defect concentration lower than the lowest interstitial silicon type point defect concentration capable of forming interstitial dislocations, and [P _V]. ] Is a region adjacent to the region [V] and having a vacancy-type point defect concentration lower than the lowest vacancy-type point defect concentration capable of forming an OSF.

The predetermined pulling speed profile of the invention according to claim 1 is equal to or higher than the second critical ratio ((V / G) ₂ ) corresponding to the region [OSF] forming the OSF nucleus and the third critical ratio ((V / G) ₃ ) Determined to be maintained below.

The pulling speed profile is determined based on the above-mentioned Boronkov theory by simulation by slicing a reference ingot in the axial direction experimentally or by combining these techniques. That is, this determination is made by slicing the ingot sliced in the axial direction in the transverse direction after the simulation, checking it in the wafer state, and further repeating the simulation. For the simulation, a plurality of types of pulling speeds are determined within a predetermined range, and a plurality of reference ingots are grown. As shown in FIG. 2, the pulling speed profile for the simulation is from a high pulling speed (a) such as 1.2 mm / min to a low pulling speed (c) of 0.5 mm / min and again a high pulling speed (d). Adjusted to The low pulling speed may be 0.4 mm / min or less, and the change in pulling speeds (b) and (d) is preferably linear.
A plurality of reference ingots pulled at different speeds are each sliced separately in the axial direction. The optimal V / G is determined from the correlation between the axial slice, wafer verification and simulation results, and then the optimal pulling speed profile is determined and the ingot is manufactured with that profile. The actual pull rate profile will depend on many variables including, but not limited to, the desired ingot diameter, the particular hot zone furnace used and the quality of the silicon melt.

Drawing the cross-sectional view of the ingot when V / G is continuously reduced by gradually reducing the pulling speed, the fact shown in FIG. 3 can be seen. FIG. 3 shows a region [V] in which vacancy type point defects exist predominantly in the ingot [V], a region in which interstitial silicon type point defects exist predominantly [I], and vacancy type point defects. A perfect region where no agglomerates and no agglomerates of interstitial silicon type point defects exist is indicated as [P]. As described above, the perfect region [P] is further classified into a region [P _I ] and a region [P _V ]. The region [P _V ] is a region where vacant point defects that do not become aggregates exist in the perfect region [P], and the region [P _I ] is an interstitial silicon type that does not become aggregates in the perfect region [P]. This is an area where point defects exist.
As shown in FIG. 3, the axial position P ₁ of the ingot includes a region where a vacancy-type point defect exists predominantly in the center. The position P ₂ includes a region in which a small hole-type point defect exists predominantly in the center as compared with the position P ₁ . The position P ₃ is a perfect region because there is no hole type point defect in the center and no interstitial silicon type point defect in the edge portion. The position P ₄ includes a ring region where an interstitial silicon type point defect exists predominantly and a perfect region in the center.

As is apparent from FIG. 3, the wafer W ₁ corresponding to the position P ₁ includes a region where a vacancy-type point defect exists predominantly in the center. This wafer W ₁ was heat-treated in an oxygen atmosphere at a temperature of 1000 ° C. ± 30 ° C. for 2 to 5 hours according to a conventional OSF clarification heat treatment, and subsequently at a temperature of 1130 ° C. ± 30 ° C. for 1 to 16 hours. When the heat treatment is performed, an OSF ring is generated in the vicinity of the periphery of the wafer W _{1 as} shown in FIG. COP tends to appear in the region where the vacancy-type point defects surrounded by the OSF ring are dominant. The wafer W ₄ corresponding to the position P ₄ includes a ring in which interstitial silicon type point defects exist predominantly and a central perfect region.

[1] wafer according to the silicon wafer claim 1 according to claim 1 is a wafer W ₂ corresponding to the position P ₂ in FIG. The wafer W ₂ includes a region in which vacancy-type point defects are dominantly present in the center of the wafer W ₁ with an area (50%) that is ½ of the total area of the wafer. When the OSF revealing heat treatment is performed on the wafer W ₂ , the OSF is not formed in a ring shape but is generated in a disk shape at the center of the wafer. The wafer W _{2 according} to claim 1 generates OSF in 25% or more of the total wafer area. If the OSF is less than 25% of the total area of the wafer, the BMD generation region is narrow and it is difficult to obtain a sufficient IG effect. Preferably it is 50 to 80%. As shown in FIG. 5, the wafer W ₂ is produced by slicing an ingot grown with a pulling speed profile selected and determined so that the OSF is not ring-shaped and is manifested in the center. FIG. 6 is a plan view thereof. The wafer W ₂ is COP free because the OSF does not form a ring shape. Also, there is no occurrence of LD (interstitial dislocation). The ingot for producing the wafer W ₂ contains oxygen precipitates that are not accompanied by dislocation generation at a rate of 2 × 10 ⁴ to 2 × 10 ⁸ pieces / cm ² . For this reason, as shown in JP-A-8-45945, the wafer is kept at a relatively low temperature of 500 to 800 ° C. for 0.5 to 20 hours before rapid heating, and oxygen is densely contained in the wafer. Precipitation nuclei need not be introduced. When the BMD density is less than 2 × 10 ⁴ pieces / cm ^2, it is difficult to obtain a sufficient IG effect when rapid heating is performed in a wafer state. 2 × 10 ⁸ pieces / cm ² is the maximum BMD density that can be generated in the OSF region.

[2] Heat treatment method according to claim 1 The heat treatment method according to claim 1 is one rapid heating. This rapid heating is performed in an atmosphere containing hydrogen gas or hydrogen gas. Specifically, a silicon wafer W ₂ at room temperature containing oxygen precipitates not accompanied by the occurrence of dislocation in the above proportion is quickly put into a furnace heated to a temperature of 1100 to 1250 ° C. and held for 1 minute to 2 hours. As another method, a room temperature silicon wafer W ₂ containing oxygen precipitates with no dislocations in the above proportion is placed in a high-speed heating furnace using a lamp capable of generating high heat, and a lamp switch is turned on to start thermal radiation. Then rapidly heat to a temperature of 1100 to 1250 ° C. and hold for 1 minute to 2 hours. Here, rapid heating refers to heat treatment at a temperature increase rate of 3 ° C./min to 150 ° C./sec, preferably 30 ° C./min to 100 ° C./sec. In the case of rapid heating by lamp light irradiation, since the wafer can be heated uniformly, there is an advantage that the wafer is less likely to warp compared to a case where it is put in a preheated furnace. If the final temperature reached by rapid heating is less than 1100 ° C., the disappearance of oxygen precipitates in the vicinity of the wafer surface is insufficient and a DZ layer cannot be secured sufficiently. On the other hand, when the temperature exceeds 1250 ° C., dislocation occurs before oxygen precipitates near the wafer surface disappear, and a DZ layer cannot be secured sufficiently. If the holding time is less than 1 minute, the time for reducing the oxygen precipitates on the wafer surface is too short, and the disappearance of oxygen precipitates on the wafer surface is insufficient, so that the DZ layer cannot be secured sufficiently. On the other hand, if it exceeds 2 hours, a DZ layer having a thickness more than necessary is obtained, and the productivity is adversely affected. The preferred holding time is determined from 1 minute to 1.5 hours.
After this rapid heating, if the silicon wafer is allowed to cool to room temperature, a DZ layer is formed over a depth of 1 to 100 μm from the wafer surface, and the BMD density in a portion deeper than this DZ layer is 2 × 10 ⁴ to 2 × 10 6. ⁸ wafers / cm ³ of IG wafer can be obtained.

Next, examples of the present invention will be described together with comparative examples.
<Example 1>
A p-type silicon ingot doped with boron (B) having a diameter of 8 inches was pulled using a silicon single crystal pulling apparatus. This ingot had a length of the straight body of 1200 mm, a crystal orientation of (100), a resistivity of about 10 Ωcm, and an oxygen concentration of 1.0 × 10 ¹⁸ atoms / cm ³ (former ASTM). ^Two ingots were grown under the same conditions while continuously decreasing the V / G during pulling from 0.24 mm ² / min ° C. to 0.18 mm ² / min ° C. One of the ingots is cut in the center of the ingot in the pulling direction as shown in FIG. 3, the position of each region is examined, and the silicon wafer W ₂ corresponding to P ₂ in FIG. 3 is cut out from the other ingot. A sample was prepared. In this example, the sample wafer W ₂ includes an area in which the vacancy-type point defects exist predominantly in the center with an area (50%) of ½ of the total area of the wafer. When the OSF revealing heat treatment is performed on the wafer W ₂ , the OSF is not formed in a ring shape as shown in FIG. 6, but is generated in a disk shape with an area of 25% or more of the total wafer area at the center of the wafer. To do.
The wafer W ₂ cut out from the ingot and mirror-polished is heated from room temperature to 1200 ° C. at a heating rate of about 50 ° C./minute in an atmosphere of 10% hydrogen gas and 90% argon gas and held at 1200 ° C. for 90 seconds. Then, heat treatment was performed.

<Comparative Example 1>
Using the same apparatus as in Example 1, a p-type silicon ingot doped with boron (B) having a diameter of 8 inches was pulled up. This ingot had the same length as the straight body portion, crystal orientation, resistivity, and oxygen concentration as in Example 1. Two ingots were grown under the same conditions by controlling V / G in the same manner as in Example 1. One of the ingots is cut in the center of the ingot in the pulling direction as shown in FIG. 3, the position of each region is examined, and a silicon wafer W ₃ at a position corresponding to P ₃ in FIG. ₃ is cut out from the other ingot. A sample was prepared. In this example, the wafer W _{3 as a} sample is a wafer without a disk due to the reduction of the disk of Example 1 when the OSF revealing heat treatment is performed. This wafer W ₃ was heat-treated in the same manner as in Example 1.

<Comparison evaluation 1>
Each wafer of Example 1 and Comparative Example 1 was cleaved, and the wafer surface was further selectively etched with a Wright etchant, and the BMD area density of the region at a depth of 350 μm from the wafer surface was observed by observation with an optical microscope. It was measured. These results are shown in Table 1.
As is clear from Table 1, since the oxygen precipitate is more in the wafer of Example 1 than in the wafer of Comparative Example 1 when the OSF revealing heat treatment is performed, the wafer of Example 1 is the same as the wafer of Comparative Example 1. A higher IG effect can be obtained.

The figure which shows that a void | hole rich ingot is formed when a V / G ratio is more than a critical point based on the Boronkov theory, and an interstitial silicon rich ingot is formed when a V / G ratio is below a critical point. The characteristic view which shows the change of the pulling speed for determining a desired pulling speed profile. FIG. 3 is a schematic view of an X-ray topography showing a vacancy-rich region, an interstitial silicon-rich region, and a perfect region of a reference ingot according to the present invention. FIG. 4 is a plan view of the wafer W ₁ showing a situation where an OSF ring appears on the silicon wafer W ₁ corresponding to the position P ₁ in FIG. 3. FIG. 4 is a cross-sectional view obtained by slicing in the axial direction through the axial center of the ingot corresponding to the position P ₂ in FIG. 3. FIG. 4 is a plan view of the wafer W ₂ showing a state in which OSF appears at the center of the silicon wafer W ₂ corresponding to the position P ₂ in FIG. 3.

Claims (1)

When OSF revealing heat treatment is performed, 1 × 10 ^{5 to} 3 × 10 ⁷ oxygen precipitates are generated in the form of a disk in the central portion of the wafer, with an area of 25% or more of the total area of the wafer, and without the occurrence of dislocations. / Cm ² generated at a density of 3 ° C./min to 150 ° C./second from room temperature to 1100 to 1250 ° C. in an atmosphere containing hydrogen gas or hydrogen gas. A method for producing an IG wafer, which is rapidly heated at a rate of temperature rise and held for 1 minute to 2 hours.

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