JP3855531B2 - Silicon wafer with polysilicon layer and method for manufacturing the same - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a silicon wafer manufactured by the Czochralski method (hereinafter referred to as CZ method) and used for manufacturing a semiconductor integrated circuit, and a manufacturing method thereof. More specifically, the present invention relates to a silicon wafer with a polysilicon layer having a polysilicon layer on the back surface and a manufacturing method thereof.
[0002]
[Prior art]
In recent years, in the process of manufacturing a semiconductor integrated circuit, as a cause of lowering yield, micro defects of oxygen precipitates that are the core of oxidation-induced stacking faults (hereinafter referred to as OSF) and particles caused by crystals (Crystal Originated Particle, hereinafter referred to as COP) or the presence of interstitial-type large dislocation (hereinafter referred to as L / D). OSF is introduced with a micro defect that becomes a nucleus during crystal growth, and becomes apparent in an oxidation process or the like when manufacturing a semiconductor device, and causes a defect such as an increase in leakage current of the manufactured device. When the mirror-polished silicon wafer is washed with a mixture of ammonia and hydrogen peroxide, pits are formed on the wafer surface. When this wafer is measured with a particle counter, the pits are detected as particles together with the original particles. The pits are caused by crystals and are called COPs to distinguish them from the original particles. COPs that are pits on the surface of the wafer cause deterioration of electrical characteristics such as oxide dielectric breakdown characteristics (Time Dependent dielectric Breakdown (TDDB), oxide breakdown voltage characteristics (Time Zero Dielectric Breakdown, TZDB). Further, if COP is present on the wafer surface, a step is produced in the device wiring process, and this step causes disconnection and lowers the product yield.
L / D is also referred to as a dislocation cluster, or it is also referred to as a dislocation pit because a pit is generated when a silicon wafer having such a defect is immersed in a selective etching solution containing hydrofluoric acid as a main component.
[0003]
From the above, it is necessary to reduce OSF, COP, and L / D from a silicon wafer used for manufacturing a semiconductor integrated circuit.
[0004]
JP-A-8-330316 discloses a defect-free silicon single crystal manufacturing method that does not generate OSF and dislocation clusters (L / D). This method uses silicon at low speed so that the OSF generated in a ring shape when thermally oxidized in the state of a silicon wafer disappears at the center of the wafer and dislocation clusters (L / D) are eliminated from the entire wafer surface. This is a method for growing a single crystal.
[0005]
[Problems to be solved by the invention]
However, the range of the pulling rate of the silicon single crystal and the range of the temperature gradient in the axial direction for producing a defect-free silicon single crystal by this method are relatively narrow, respectively, and the diameter of the pulling silicon single crystal increases. In addition, it becomes difficult to produce a defect-free silicon single crystal, and due to fluctuations in pulling speed, the OSF may be manifested in the center of the wafer instead of in a ring shape. Since the OSF deteriorates the junction leakage characteristics as described above, it has been demanded to be improved.
[0006]
The object of the present invention is to eliminate the generation of OSF due to this thermal oxidation even if the OSF is not formed in a ring shape when the conventional OSF revealing heat treatment is performed but the wafer is manifested in the center of the wafer. Another object of the present invention is to provide a silicon wafer with a polysilicon layer that is COP-free and a method for manufacturing the same.
Another object of the present invention is to provide a silicon wafer with a polysilicon layer in which oxygen precipitation is uniformly performed on all surfaces of the wafer, and a uniform gettering effect is obtained with no variation between the wafer peripheral portion and the wafer central portion. And a manufacturing method thereof.
[0007]
[Means for Solving the Problems]
According to the first aspect of the present invention, the oxygen concentration at which no particles (COP) or interstitial dislocations (L / D) are generated in the wafer plane is 1.2 × 10 ¹⁸ atoms / cm ³ or less (formerly An ASTM) silicon wafer that is heat-treated for 2 to 5 hours at a temperature of 1000 ° C. ± 30 ° C. in an oxygen atmosphere and subsequently heat-treated at a temperature of 1130 ° C. ± 30 ° C. for 1 to 16 hours. A silicon wafer with a polysilicon layer, wherein a polysilicon layer having a thickness of 1.3 ± 0.3 μm is formed on the back surface of the silicon wafer to be formed.
According to a second aspect of the present invention, a polysilicon layer is formed on the back surface of the silicon wafer according to the first aspect at a temperature of 670 ° C. ± 30 ° C. by a chemical vapor deposition (hereinafter referred to as CVD) method with a thickness of 1.3 ± It is a manufacturing method of the silicon wafer with a polysilicon layer characterized by forming in 0.3 micrometer.
The silicon wafer according to claim 1 is a wafer made by the CZ method under the condition that OSF appears at the center thereof, and has a relatively large number of oxygen precipitation nuclei at the center, and oxygen precipitation nuclei at other portions. Almost no. Moreover, it is COP free except for the central part. When a polysilicon layer is formed on the back surface of the silicon wafer by the method according to claim 2, oxygen precipitates are formed on the entire surface of the wafer during the CVD process. As a result, oxygen precipitation is uniformly performed on all surfaces of the wafer, and a uniform gettering effect with no variation between the wafer central portion and other portions can be obtained.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
The silicon wafer of the present invention is produced by slicing an ingot from a silicon melt in a hot zone furnace with a predetermined pulling speed profile based on the Boronkov theory by the CZ method.
In general, when a silicon single crystal ingot is pulled from a silicon melt in a hot zone furnace by the CZ method, point defects and agglomerates (agglomerates: three-dimensional) Defect) occurs. There are two general forms of point defects: vacancy-type point defects and interstitial silicon-type point defects. A vacancy-type point defect is one in which one silicon atom leaves one of the normal positions in the silicon crystal lattice. Such holes become hole-type point defects. On the other hand, when an atom is found at a position (interstitial site) other than the lattice point of the silicon crystal, this becomes an interstitial silicon point defect.
[0009]
Point defects are generally formed at the contact surface between a silicon melt (molten silicon) and an ingot (solid silicon). However, by continuously pulling up the ingot, the portion that was the contact surface begins to cool as it is pulled up. During cooling, vacancy point defects or interstitial silicon point defects merge with each other by diffusion to form vacancy agglomerates or interstitial agglomerates. Is formed. In other words, the aggregate is a three-dimensional structure generated due to the merge of point defects.
The agglomerates of vacancy-type point defects include defects called LSTD (Laser Scattering Tomograph Defects) or FPD (Flow Pattern Defects) in addition to the above-mentioned COP. It contains a defect called D. FPD is a source of traces that show a unique flow pattern that appears when a silicon wafer produced by slicing an ingot is chemically etched with a Secco etchant for 30 minutes. This is a source having a refractive index different from that of silicon when irradiated with infrared rays.
[0010]
Boronkov's theory is that in order to grow a high-purity ingot with a small number of defects, the ingot pulling speed is V (mm / min), and the temperature gradient at the contact surface of the ingot-silicon melt is G (° C. in a hot zone structure. / Mm), V / G (mm ² / min · ° C.) is controlled. In this theory, as shown in FIG. 1, V / G graphically represents the vacancy concentration and interstitial silicon concentration as a function, and the boundary of the vacancy / interstitial silicon region on the wafer is determined by V / G. Explain that. More specifically, when the V / G ratio is equal to or higher than the critical point, an ingot in which vacant point defects exist predominantly is formed. On the other hand, when the V / G ratio is lower than the critical point, interstitial silicon type point defects are dominant. An existing ingot is formed.
[0011]
The predetermined pulling rate profile of the present invention shows that when the ingot is pulled from the silicon melt in the hot zone furnace, the ratio of the pulling rate to the temperature gradient (V / G) indicates the formation of agglomerates of interstitial silicon type point defects. The first critical ratio to be prevented ((V / G) ₁ ) or higher, and the agglomeration of vacancy-type point defects is limited to a region where the vacancy-type point defects in the center of the ingot are dominantly present. It is determined so as to be maintained below the two critical ratio ((V / G) ₂ ).
[0012]
This pull-up speed profile can be determined by simulation of Boronkov's theory by slicing the reference ingot experimentally, by slicing the reference ingot experimentally to the wafer, or by combining these techniques. To be determined. That is, this determination is made by checking the axial slice of the ingot and the sliced wafer after the simulation, and further repeating the simulation. For the simulation, a plurality of types of pulling speeds are determined within a predetermined range, and a plurality of reference ingots are grown. As shown in FIG. 2, the pulling speed profile for the simulation is from a high pulling speed (a) such as 1.2 mm / min to a low pulling speed (c) of 0.5 mm / min and again a high pulling speed (d). Adjusted to The low pulling speed may be 0.4 mm / min or less, and the change in pulling speeds (b) and (d) is preferably linear.
[0013]
A plurality of reference ingots, pulled at different speeds, are each sliced axially. The optimal V / G is determined from the correlation between the axial slice, wafer verification and simulation results, and then the optimal pulling speed profile is determined and the ingot is manufactured with that profile. The actual pull rate profile will depend on many variables including, but not limited to, the desired ingot diameter, the particular hot zone furnace used and the quality of the silicon melt.
[0014]
Drawing the cross-sectional view of the ingot when V / G is continuously reduced by gradually reducing the pulling speed, the fact shown in FIG. 3 can be seen. FIG. 3 shows a rich region [V] in which vacancy type point defects exist predominantly in the ingot, [I], a region in which interstitial silicon type point defects exist predominantly, and vacancy type points. A perfect region where no defect agglomerates and interstitial silicon-type point defect agglomerates exist is indicated as [P]. As shown in FIG. 3, the axial position P ₁ of the ingot includes a region where a vacancy-type point defect exists predominantly in the center. The position P ₂ includes a region in which a small hole-type point defect exists predominantly in the center as compared with the position P ₁ . The position P ₄ includes a ring region in which an interstitial silicon type point defect is dominantly present and a central perfect region. Further, the position P ₃ is a perfect region because there is no hole type point defect in the center and no interstitial silicon type point defect in the edge portion.
[0015]
As is apparent from FIG. 3, the wafer W ₁ corresponding to the position P ₁ includes a region where a vacancy-type point defect exists predominantly in the center. The wafer W ₂ corresponding to the position P ₂ includes a region where a vacancy-type point defect exists predominantly in a small area in the center as compared with the wafer W ₁ . The wafer W ₄ corresponding to the position P ₄ includes a ring in which interstitial silicon type point defects exist predominantly and a central perfect region. Further, the wafer W ₃ corresponding to the position P ₃ is completely a perfect region because there is no hole type point defect in the center and no interstitial silicon type point defect in the edge portion.
[0016]
A slight region in contact with the perfect region of the region where the vacancy-type point defects exist predominantly is a region where neither COP nor L / D occurs in the wafer surface. However, this silicon wafer was heat-treated in an oxygen atmosphere at a temperature of 1000 ° C. ± 30 ° C. for 2 to 5 hours in accordance with a conventional OSF clarification heat treatment, and subsequently at a temperature of 1130 ° C. ± 30 ° C. for 1 to 16 hours. When heat-treated, OSF is generated. As shown in FIG. 4, OSF ring is generated in the vicinity of half the radius of the wafer W ₁ in the wafer. COP tends to appear in the region where the vacancy-type point defects surrounded by the OSF ring are dominant. On the other hand, in the wafer W ₂ , the OSF is not formed in a ring shape but is generated only in the center portion of the wafer. Silicon wafers used in the present invention is the wafer W _2. That is, the silicon wafer W ₂ of the present invention is obtained by slicing an ingot grown with a pulling speed profile selected and determined so that the OSF is not ring-shaped as shown in FIG. Produced. FIG. 6 is a plan view thereof. The silicon wafer W ₂ is COP free because the OSF does not form a ring shape. There is no occurrence of L / D.
[0017]
In the silicon wafer of the present invention, the oxygen concentration in the wafer is further controlled. In the CZ method, the oxygen concentration in the wafer is controlled by changing the flow rate of argon supplied into the hot zone furnace, the rotation speed of the quartz crucible for storing the silicon melt, the pressure in the hot zone furnace, and the like. The oxygen concentration inside the wafer is controlled to 1.2 × 10 ¹⁸ atoms / cm ³ or less (former ASTM). In order to achieve this oxygen concentration, for example, the flow rate of argon is controlled to 80 to 150 liters / minute, the rotation speed of the quartz crucible for storing the silicon melt is 4 to 9 rpm, and the pressure in the hot zone furnace is 15 to 60 Torr. To do. The reason why the silicon wafer of the present invention has an oxygen concentration of 1.2 × 10 ¹⁸ atoms / cm ³ or less (former ASTM) is to prevent excessive precipitation of oxygen precipitation nuclei.
[0018]
On the surface of the silicon wafer produced by slicing the ingot pulled up under the above conditions, the polysilicon layer has a thickness of 1.3 ± 0.00 mm at a temperature of 670 ° C. ± 30 ° C. by using, for example, SiH ₄ by the CVD method. It is formed with 3 μm. When the thickness of the polysilicon layer is less than 1.0 μm, the effect of the polysilicon layer is poor, and when it exceeds 1.6 μm, the productivity is lowered. Even before the polysilicon layer is formed, even if the oxygen concentration is uniform within the wafer surface, oxygen precipitation is likely to occur at the center of the wafer and oxygen precipitation is difficult to occur at other portions, forming a polysilicon layer. As a result, the state of oxygen precipitation in the wafer surface becomes uniform.
As a result, when the silicon wafer with a polysilicon layer is heat-treated in the semiconductor device process, even if oxygen precipitate nuclei exist in the wafer, these nuclei do not grow, and the conventional heat treatment for OSF manifestation is performed. Even if it goes, OSF does not occur.
[0019]
【Example】
Next, examples of the present invention will be described together with comparative examples.
<Example>
The ingot was pulled up so that the region corresponding to the position P ₂ shown in FIG. 3 was grown over the entire length of the ingot. At this time, in order to control the oxygen concentration in the ingot, the flow rate of argon was maintained at about 110 liters / minute, the rotation speed of the quartz crucible for storing the silicon melt was maintained at about 5-10 rpm, and the pressure in the hot zone furnace was maintained at about 60 Torr. . The silicon wafer sliced from the ingot pulled up in this way is lapped and chamfered, and then the wafer surface damage is removed by chemical etching, and the wafer back surface is CVD-processed using SiH ₄ at 680 ° C. for 1 A polysilicon layer was formed with a thickness of 5 μm. Then, a silicon wafer having a diameter of 8 inches and a thickness of 725 μm was prepared by mirror polishing.
<Comparative example>
The same silicon wafer as that of Example 1 was used as a comparative example, except that no polysilicon layer was formed.
[0020]
<Comparison evaluation>
The silicon wafer of the example and the silicon wafer of the comparative example were subjected to a first heat treatment imitating the heat treatment in the semiconductor device process. That is, these wafers were heat-treated at a temperature of 800 ° C. for 4 hours under an oxygen atmosphere, and subsequently heat-treated at a temperature of 1000 ° C. for 16 hours. In these examples and comparative examples, the oxygen concentration on the wafer surface from the center to the periphery of the wafer was measured by Fourier transform infrared spectroscopy (FT-IR). FIG. 7 shows Δ [Oi], which is the difference in oxygen concentration before and after the heat treatment.
The second heat treatment imitating the heat treatment in the semiconductor device process was performed on another silicon wafer of the example and another silicon wafer of the comparative example. That is, these wafers were heat-treated in an oxygen atmosphere at a temperature of 700 ° C. for 8 hours, and subsequently heat-treated at a temperature of 1000 ° C. for 12 hours. In these examples and comparative examples, the oxygen concentration on the wafer surface from the wafer center to the periphery was measured by FT-IR. FIG. 8 shows Δ [Oi], which is the difference in oxygen concentration before and after the heat treatment.
[0021]
As shown in FIGS. 7 and 8, the oxygen concentration difference Δ [Oi] before and after the heat treatment of the silicon wafer of the comparative example greatly varies between about 40 mm from the center of the wafer, whereas the silicon of the example The oxygen concentration difference Δ [Oi] before and after the heat treatment of the wafer was only gradually reduced between about 90 mm from the center of the wafer and was uniform within the wafer surface.
[0022]
Further, another silicon wafer of the example and another silicon wafer of the comparative example were heat-treated at a temperature of 1000 ° C. for 4 hours and subsequently heat-treated at a temperature of 1130 ° C. for 3 hours (pyrogenic oxidation treatment). It was investigated whether OSF was actualized. As a result, an OSF in which the silicon wafer of the comparative example was clouded at the center of the wafer appeared. On the other hand, OSF did not appear in the wafer surface of the silicon wafer of the example.
[0023]
【The invention's effect】
As described above, according to the present invention, a silicon wafer in which neither COP nor L / D occurs in the wafer surface, and OSF reveals OSF in the center of the wafer when the conventional OSF reveal heat treatment is performed. On the other hand, if a polysilicon layer is formed on the back surface of this wafer, it is COP free and OSF generation due to heat treatment in the semiconductor device process can be eliminated. Further, oxygen precipitation is uniformly performed on all surfaces of the wafer, and there is a feature that a uniform gettering effect with no variation between the wafer peripheral portion and the wafer central portion can be obtained.
[Brief description of the drawings]
FIG. 1 is a diagram showing that a void-rich ingot is formed when the V / G ratio is higher than a critical point, and an interstitial silicon-rich ingot is formed when the V / G ratio is lower than the critical point, based on the Boronkov theory. .
FIG. 2 is a characteristic diagram showing a change in pulling speed for determining a desired pulling speed profile.
FIG. 3 is a schematic view of an X-ray tomography showing a vacancy-rich region, an interstitial silicon-rich region, and a perfect region of a reference ingot according to the present invention.
4 is a diagram showing a situation in which an OSF ring appears on a silicon wafer W ₁ corresponding to a position P ₁ in FIG. 3;
FIG. 5 is a cross-sectional view obtained by slicing in the axial direction through the axial center of the ingot corresponding to the position P ₁ in FIG. 3;
6 is a diagram showing a situation in which OSF appears at the center of the silicon wafer W ₂ corresponding to the position P ₂ in FIG. 3;
FIG. 7 is a view showing the state of Δ [Oi] in the wafer surface before and after the first heat treatment imitating the heat treatment in the semiconductor device process for each silicon wafer of Examples and Comparative Examples.
FIG. 8 is a diagram showing the state of Δ [Oi] in the wafer surface before and after the second heat treatment imitating the heat treatment in the semiconductor device process for each silicon wafer of Examples and Comparative Examples.

Claims (2)

A silicon wafer having an oxygen concentration of 1.2 × 10 ¹⁸ atoms / cm ³ or less (former ASTM) in which no crystal-induced particles or interstitial dislocations are generated in the wafer surface, and 1000 ° C. ±± When heat treatment is performed for 2 to 5 hours at a temperature of 30 ° C., and subsequently for 1 to 16 hours at a temperature of 1130 ° C. ± 30 ° C., a thickness of 1.3 ± A silicon wafer with a polysilicon layer, wherein a 0.3 μm polysilicon layer is formed. A silicon wafer having an oxygen concentration of 1.2 × 10 ¹⁸ atoms / cm ³ or less (former ASTM) in which no crystal-induced particles or interstitial dislocations are generated in the wafer surface, and 1000 ° C. ±± When heat treatment is performed at a temperature of 30 ° C. for 2 to 5 hours and subsequently heat treatment is performed at a temperature of 1130 ° C. ± 30 ° C. for 1 to 16 hours, oxidation-induced stacking faults appear at the center of the wafer. A method for producing a silicon wafer with a polysilicon layer, wherein a polysilicon layer is formed at a temperature to a thickness of 1.3 ± 0.3 μm by a chemical vapor deposition method.

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