JP2000306916A - Silicon wafer with polycrystalline silicon layer and manufacture of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a wafer free of OSF and COP, even if a conventional thermal treatment for making OSF obvious is carried out, make oxide deposition uniform over the whole surface of the wafer and obtain uniform gettering effects, without variation between the circumferential edge and central part of the wafer. SOLUTION: Oxygen concentration of a silicon wafer, with which crystal oriented particles(COPs) and penetration-type displacements(L/Ds) are not produced on a wafer surface is not larger than 1.2×1018 atoms/cm3 (old ASTM). If the silicon wafer is subjected to a thermal treatment at 1,000 deg.C±30 deg.C for 2-5 hours in an oxygen atmosphere, and successively, is subjected to a thermal treatment at 1,130 deg.C±30 deg.C for 1-16 hours, oxidation starting failures(OSFs) are made obvious in the central part of the silicon wafer. A polycrystalline silicon layer with a thickness of 1.3±0.3 μm is formed on the rear surface of the silicon wafer at a temperature of 670 deg.C±30 deg.C by chemical vapor phase deposition(CVD) method.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a silicon wafer manufactured by the Czochralski method (hereinafter referred to as CZ method) and used for manufacturing a semiconductor integrated circuit, and a method for manufacturing the same. More particularly, the present invention relates to a silicon wafer with a polysilicon layer having a polysilicon layer on the back surface and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, in the process of manufacturing a semiconductor integrated circuit, an oxidation-induced stacking fault (hereinafter referred to as OSF) is a cause of lowering the yield.
That. ) Nuclei of oxygen precipitates and microcrystalline particles (Crystal Originated Particl
e, hereinafter referred to as COP. ) Or interstitial dislocations (Int
erstitial-type Large Dislocation, hereinafter referred to as L / D. ). In OSF, micro defects serving as nuclei are introduced during crystal growth and become apparent in an oxidation step or the like when manufacturing a semiconductor device, and cause a defect such as an increase in leak current of the manufactured device. When the mirror-polished silicon wafer is washed with a mixed solution of ammonia and hydrogen peroxide, pits are formed on the wafer surface. When the wafer is measured with a particle counter, the pits are detected as particles together with the original particles. The pits are caused by crystals and are referred to as COPs to distinguish them from original particles. The COP, which is a pit on the wafer surface, has electrical characteristics, such as a time-dependent dielectric breakdown characteristic (Time Dependent
It causes deterioration of dielectric breakdown (TDDB), oxide breakdown voltage characteristics (Time Zero Dielectric Breakdown, TZDB), and the like. Also, if the COP exists on the wafer surface, a step occurs in a device wiring process, and this step causes disconnection and lowers the product yield. L
/ D is also called a dislocation pit because a pit is generated when a silicon wafer having this defect is immersed in a selective etching solution containing hydrofluoric acid as a main component.

[0003] From the above, OSF, CO, etc. can be obtained from a silicon wafer used for manufacturing a semiconductor integrated circuit.
There is a need to reduce P and L / D.

A method for producing a defect-free silicon single crystal free of OSF and dislocation cluster (L / D) is disclosed in
It is disclosed in JP-A-330316. This method uses a silicon wafer at a low speed so that the ring-shaped OSF generated when the silicon wafer is thermally oxidized disappears at the center of the wafer and dislocation clusters (L / D) are eliminated from the entire surface of the wafer. This is a method for growing a single crystal.

[0005]

However, the range of the pulling speed of the silicon single crystal and the range of the temperature gradient in the axial direction of the crystal for producing a defect-free silicon single crystal by this method are relatively narrow, and the pulling is performed. As the diameter of the silicon single crystal increases, it becomes more difficult to manufacture defect-free silicon single crystals. Due to fluctuations in the pulling rate, etc., when the wafer is formed into a wafer, the OSF is not ring-shaped but appears at the center of the wafer. May also occur. Since the OSF deteriorates the junction leak characteristics as described above, improvement has been demanded.

[0006] An object of the present invention is to provide a wafer in which the OSF is not ring-shaped but is exposed at the center of the wafer when the conventional heat treatment for OSF exposure is performed.
It is an object of the present invention to provide a COP-free silicon wafer with a polysilicon layer which eliminates the occurrence of OSF due to the thermal oxidation and a method of manufacturing the same. Another object of the present invention is to provide a silicon wafer with a polysilicon layer in which oxygen precipitation is uniformly performed on all surfaces of the wafer, and a uniform gettering effect is obtained without variation between the wafer periphery and the wafer center. And a method for manufacturing the same.

[0007]

The invention according to claim 1 is
Particles (COP) caused by crystals in the wafer plane
Oxygen concentration is 1.2 × 10 ¹⁸ atoms / cm ³ or less where neither interstitial dislocations (L / D) are generated (former ASTM)
Silicon wafer under an oxygen atmosphere at 1000
Heat treatment at a temperature of 30 ° C. ± 30 ° C. for 2 to 5 hours.
When a heat treatment is performed at a temperature of 0 ° C. ± 30 ° C. for 1 to 16 hours, a polysilicon layer having a thickness of 1.3 ± 0.3 μm is formed on the back surface of the silicon wafer in which OSF is exposed at the center of the wafer. It is a silicon wafer with a polysilicon layer. According to a second aspect of the present invention, a polysilicon layer is formed on a rear surface of the silicon wafer according to the first aspect at a temperature of 670 ° C. ± 30 ° C. by a chemical vapor deposition (hereinafter, referred to as a CVD) method with a thickness of 1.3 ± 1.3. A method for manufacturing a silicon wafer with a polysilicon layer, characterized in that the silicon wafer is formed to have a thickness of 0.3 μm. The silicon wafer according to claim 1 is a wafer made by the CZ method under a condition where OSF appears at the center, and has a relatively large number of oxygen precipitation nuclei in the center,
Other portions have almost no oxygen precipitation nuclei. COP-free except for the center. When a polysilicon layer is formed on the back surface of the silicon wafer by the method according to claim 2, oxygen precipitates are formed on the entire surface of the wafer during the CVD process. As a result, oxygen precipitation is performed uniformly on all surfaces of the wafer, and a uniform gettering effect without variation between the central portion of the wafer and other portions can be obtained.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The silicon wafer of the present invention has a C
After the ingot is pulled up from the silicon melt in the hot zone furnace by the Z method with a predetermined pulling speed profile based on Voronkov's theory, the ingot is sliced. Generally, when a silicon single crystal ingot is pulled from a silicon melt in a hot zone furnace by the CZ method, defects in the silicon single crystal include point defects and agglomerates: Defects). Point defects have two general forms: vacancy type point defects and interstitial silicon type point defects. A vacancy-type point defect is one in which one silicon atom has separated from one of the normal positions in the silicon crystal lattice. Such holes become hole type point defects. On the other hand, if an atom is found at a position (interstitial site) other than the lattice point of the silicon crystal, this becomes an interstitial silicon point defect.

[0009] Point defects are generally formed at the interface between the silicon melt (molten silicon) and the ingot (solid silicon). However, by continuously pulling up the ingot, the portion that was the contact surface starts to cool down with pulling up. During cooling, vacancy-type point defects or interstitial silicon-type point defects merge with each other by diffusion to form vacancy agglomerates or interstitial agglomerates. Is formed. In other words, the aggregate is a three-dimensional structure generated due to the merging of point defects. Aggregates of vacancy-type point defects are LSTDs (Laser Scattering Tomograms) in addition to the COPs described above.
agg defects or FPDs (Flow Pattern Defects), and the aggregates of interstitial silicon-type point defects include the aforementioned defects called L / D. What is FPD?
LSTD is a source of traces that exhibit a unique flow pattern that appears when a silicon wafer produced by slicing an ingot is chemically etched with a Secco etchant for 30 minutes. Is a source having a refractive index different from that of silicon and generating scattered light.

Boronkov's theory states that in order to grow a high-purity ingot having a small number of defects, the pulling speed of the ingot is set to V (mm / min) and the temperature gradient of the ingot-silicon melt contact surface in a hot zone structure is reduced. G (° C / mm)
Is to control V / G (mm ² / min · ° C.). In this theory, as shown in FIG. 1, V / G graphically represents the vacancy concentration and the interstitial silicon concentration as a function, and the boundary of the vacancy / interstitial silicon region on the wafer is determined by V / G. Is explained. More specifically, when the V / G ratio is higher than the critical point, an ingot in which vacancy-type point defects are predominantly formed, whereas when the V / G ratio is lower than the critical point, interstitial silicon-type point defects are predominant. An existing ingot is formed.

[0011] The predetermined pull rate profile of the present invention is that when the ingot is pulled from the silicon melt in a hot zone furnace, the ratio of the pull rate to the temperature gradient (V / G) is an aggregate of interstitial silicon type point defects. Aggregates of vacancy-type point defects which are equal to or higher than the first critical ratio ((V / G) ₁ ) for preventing generation of vacancies are located in the region where vacancy-type point defects predominantly exist in the center of the ingot. It is determined so as to be maintained at or below the second critical ratio ((V / G) ₂ ).

The profile of the pulling speed is obtained by slicing the reference ingot in the axial direction experimentally and slicing the reference ingot on the wafer experimentally.
Alternatively, by combining these techniques, it is determined by simulation based on the above-mentioned Boronkov theory. That is, this determination is made by checking the axial slice of the ingot and the sliced wafer after the simulation, and repeating the simulation. For the simulation, a plurality of kinds of pulling speeds are determined within a predetermined range, and a plurality of reference ingots are grown. As shown in FIG. 2, the pulling speed profile for the simulation is from a high pulling speed (a) such as 1.2 mm / min to a low pulling speed (c) of 0.5 mm / min and again a high pulling speed (d). It is adjusted to. The low pulling speed may be 0.4 mm / min or less, the pulling speeds (b) and (d)
The change in is desirably linear.

A plurality of reference ingots pulled at different speeds are individually sliced in the axial direction. Optimal V /
G is determined from the correlation of the results of the axial slicing, wafer validation and simulation, followed by the determination of the optimal pulling speed profile, which is used to produce the ingot. The actual pulling speed profile will depend on many variables including but not limited to the desired ingot diameter, the particular hot zone furnace used and the quality of the silicon melt.

FIG. 3 shows the fact that a drawing of a cross section of the ingot when the pulling speed is gradually reduced and V / G is continuously reduced is illustrated. In FIG. 3, [V] represents an abundant region where vacancy type point defects predominantly exist in the ingot, [I] represents a region where interstitial silicon type point defects predominantly exist, and vacancy type points. Perfect regions where there are no defect aggregates and no interstitial silicon type point defect aggregates are indicated as [P]. As shown in FIG. 3, the axial position P ₁ of the ingot contains a region where vacancy type point defects at the center dominantly present. Position P ₂ includes an area smaller vacancy type point defects at the center dominantly present as compared to the position P _1. Position P ₄ includes a ring region and the central perfect area that exists dominantly interstitial silicon type point defects. The position P ₃ is neither vacancy type point defects at the center, all since there is no silicon point defect interstitial the edge portion is perfect area.

As is apparent from FIG. 3, the wafer W ₁ corresponding to the position P ₁ includes a region in which vacancy type point defects predominantly exist in the center. Wafer W ₂ corresponding to the position P ₂ is,
It includes a region vacancy type point defects are dominantly present in a small area in the center compared to the wafer W _1. Wafer W ₄ corresponding to position P ₄ includes a ring where interstitial silicon-type point defects predominantly exist and a central perfect region. Further, the wafer W ₃ corresponding to the position P ₃ is a perfect area because there is no void type point defect at the center and no interstitial silicon type point defect at the edge.

A small area in contact with the perfect area of the area where the vacancy type point defects are predominantly present is an area where neither COP nor L / D is generated in the wafer surface. However, this silicon wafer is heat-treated at 1000 ° C. ± 30 ° C. for 2 to 5 hours in an oxygen atmosphere according to the conventional OSF revealing heat treatment, and then 1130 ° C. ± 30 ° C.
Heat treatment at a temperature of 1 to 16 hours produces OSF.
As shown in FIG. 4, OSF ring is generated in the vicinity of half the radius of the wafer W ₁ in the wafer. The region where the vacancy-type point defects dominated by the OSF ring are C
OP tends to appear. In contrast, wafer W
_{In 2} , the OSF does not form a ring but occurs only at the center of the wafer. Silicon wafers used in the present invention is the wafer W _2. In other words, the silicon wafer W ₂ of the present invention is obtained by slicing an ingot grown with a pulling speed profile selected and determined so that the OSF is not ring-shaped but exposed only at the center as shown in FIG. It is made. FIG. 6 is a plan view thereof. Since the silicon wafer W ₂ OSF does not form a ring, a COP-free. There is no occurrence of L / D.

In the silicon wafer of the present invention, the oxygen concentration in the wafer is further controlled. In the CZ method, the oxygen concentration in the wafer is controlled by changing the flow rate of argon supplied into the hot zone furnace, the rotation speed of the quartz crucible storing the silicon melt, the pressure in the hot zone furnace, and the like. The oxygen concentration inside the wafer is 1.2 × 10 ¹⁸ at
oms / cm ³ or less (old ASTM). In order to achieve this oxygen concentration, for example, the flow rate of argon is set to 80 to
The rotation speed of the quartz crucible storing silicon melt is controlled at 4 to 9 rpm, and the pressure in the hot zone furnace is controlled at 15 to 60 Torr at 150 liter / min. The silicon wafer of the present invention has an oxygen concentration of 1.2 × 10 ¹⁸ at.
oms / cm ³ or less (former ASTM) is to prevent excessive precipitation of oxygen precipitation nuclei.

The surface of a silicon wafer produced by slicing an ingot pulled under the above conditions is CV
A polysilicon layer is formed to a thickness of 1.3 ± 0.3 μm at a temperature of 670 ° C. ± 30 ° C. using, for example, SiH ₄ by D method. If the thickness of the polysilicon layer is less than 1.0 μm, the effect of the polysilicon layer will be poor, and if it exceeds 1.6 μm, the productivity will decrease. Before the polysilicon layer is formed, even if the oxygen concentration is uniform in the wafer surface, oxygen precipitation is likely to occur at the center of the wafer, and oxygen precipitation is difficult in other parts, forming a polysilicon layer. Thereby, the state of oxygen precipitation in the wafer surface is made uniform. Thereby, when the silicon wafer with the polysilicon layer is heat-treated in the semiconductor device process,
Even if nuclei of oxygen precipitates are present in the wafer, these nuclei no longer grow, and no OSF is generated even when a conventional heat treatment for OSF manifestation is performed.

[0019]

Next, examples of the present invention will be described together with comparative examples. An area corresponding to the position P ₂ shown in <Embodiment> FIG. 3 was pulled ingot to cultivate over ingot length. At this time, in order to control the oxygen concentration in the ingot, the flow rate of argon is about 110 l / min, and the rotation speed of the quartz crucible for storing the silicon melt is about 5 to 10 rpm.
m, the pressure in the hot zone furnace was maintained at about 60 Torr. After lapping and chamfering the silicon wafer sliced from the ingot pulled up in this way, damage to the wafer surface is removed by chemical etching, and SiH _{4 is} deposited on the back surface of the wafer by CVD.
To form a polysilicon layer at 680 ° C. with a thickness of 1.5 μm. After that, by mirror polishing, the diameter 8
An inch, 725 μm thick silicon wafer was prepared. <Comparative Example> The same silicon wafer as in Example 1 was used as a comparative example except that no polysilicon layer was formed.

<Comparative Evaluation> The silicon wafer of the example and the silicon wafer of the comparative example were subjected to a first heat treatment simulating a heat treatment in a semiconductor device process. That is, these wafers were heat-treated at 800 ° C. for 4 hours in an oxygen atmosphere, and then heat-treated at 1000 ° C. for 16 hours. In these examples and comparative examples, the oxygen concentration on the wafer surface from the central portion to the peripheral portion of the wafer was measured by Fourier transform infrared spectroscopy (FT-IR). FIG. 7 shows the difference in oxygen concentration before and after the heat treatment, Δ [Oi]. A second heat treatment simulating a heat treatment in a semiconductor device process was performed on another silicon wafer of the example and another silicon wafer of the comparative example. That is, these wafers were heat-treated in an oxygen atmosphere at a temperature of 700 ° C. for 8 hours, and subsequently heat-treated at a temperature of 1000 ° C. for 12 hours. In these examples and the comparative example, the oxygen concentration on the wafer surface from the center to the periphery of the wafer was measured by FT-
It was measured by IR. The difference in oxygen concentration before and after heat treatment.
[Oi] is shown in FIG.

As shown in FIGS. 7 and 8, the difference in oxygen concentration △ [Oi] before and after the heat treatment of the silicon wafer of the comparative example fluctuates greatly up to about 40 mm from the center of the wafer. The oxygen concentration difference Δ [Oi] of the silicon wafer before and after the heat treatment is 90 m from the center of the wafer.
m, it was uniform within the wafer surface, only slowly decreasing.

Further, about still another silicon wafer of the embodiment and still another silicon wafer of the comparative example, 1000
Heat treatment was performed at a temperature of 1 ° C. for 4 hours, followed by heat treatment at a temperature of 1130 ° C. for 3 hours (pyrogenic oxidation treatment), and it was visually examined whether or not OSF had become apparent. As a result, an OSF in which the silicon wafer of the comparative example became cloudy at the center of the wafer appeared. On the other hand, in the silicon wafer of the example, OSF did not appear in the wafer surface.

[0023]

As described above, according to the present invention, neither COP nor L / D is generated in the wafer surface, and when the conventional OSF revealing heat treatment is performed, the OSF is formed at the center of the wafer.
When a polysilicon layer is formed on the back surface of a silicon wafer on which silicon is exposed, COP is free, and the OS formed by the heat treatment in the semiconductor device process is performed.
The occurrence of F can be eliminated. Another feature is that oxygen precipitation is uniformly performed on all surfaces of the wafer, and a uniform gettering effect with no variation between the wafer peripheral portion and the wafer center portion can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram based on Bornkov's theory showing that when the V / G ratio is above the critical point, a vacancy-rich ingot is formed, and when the V / G ratio is below the critical point, an interstitial silicon-rich ingot is formed. .

FIG. 2 is a characteristic diagram showing a change in pulling speed for determining a desired pulling speed profile.

FIG. 3 shows a porosity-rich region of a reference ingot according to the invention,
X indicating interstitial silicon-rich region and perfect region
Schematic diagram of line tomography.

FIG. 4 shows a silicon wafer W ₁ corresponding to a position P ₁ in FIG.
The figure which shows the situation in which an OSF ring appears.

5 is a cross-sectional view sliced in the axial direction through the axial center of the ingot corresponding to the position P ₁ in FIG.

FIG. 6 shows a silicon wafer W ₂ corresponding to a position P ₂ in FIG.
The figure which shows the situation in which OSF appears in the center part of FIG.

FIG. 7 is a view showing the state of △ [Oi] in the wafer surface before and after a first heat treatment simulating a heat treatment in a semiconductor device process for each silicon wafer of the example and the comparative example.

FIG. 8 is a diagram illustrating the state of △ [Oi] in the wafer surface before and after a second heat treatment simulating a heat treatment in a semiconductor device process for each silicon wafer of the example and the comparative example.

Continued on the front page F term (reference) 4G077 AA02 AB01 BA04 CF10 FJ06 5F045 AA03 AB03 AC01 AD10 AF01 AF02 AF03 AF16 AF17 BB12 BB13

Claims (2)

[Claims] An oxygen concentration at which neither particles due to crystals nor interstitial dislocations are generated in a wafer surface is 1.2 ×
10 ¹⁸ atoms / cm ³ or less (former ASTM) silicon wafer, 1000 ° C. ± 30 ° C. in an oxygen atmosphere
Heat treatment at 2 ℃ for 2-5 hours, then 1130 ℃ ± 3
When a heat treatment is performed at a temperature of 0 ° C. for 1 to 16 hours, a polysilicon layer having a thickness of 1.3 ± 0.3 μm is formed on the back surface of the silicon wafer where oxidation-induced stacking faults become apparent at the center of the wafer. Silicon wafer with polysilicon layer. 2. An oxygen concentration in which neither particles due to crystals nor interstitial dislocations are generated in the wafer surface is 1.2 ×
10 ¹⁸ atoms / cm ³ or less (former ASTM) silicon wafer, 1000 ° C. ± 30 ° C. in an oxygen atmosphere
Heat treatment at 2 ℃ for 2-5 hours, then 1130 ℃ ± 3
When heat treatment is performed at a temperature of 0 ° C. for 1 to 16 hours, oxidation-induced stacking faults become apparent at the center of the wafer. A polysilicon layer is formed on the back surface of the silicon wafer at a temperature of 670 ° C. ± 30 ° C. by a chemical vapor deposition method. 3. A method for manufacturing a silicon wafer with a polysilicon layer, wherein the silicon wafer has a thickness of 3 ± 0.3 μm.