KR100386230B1 - Silicon Wafer for Deposition of an Epitaxial Layer and an Epitaxial Wafer and a Method for Manufacturing the Same - Google Patents

Abstract

When an epitaxial layer free of oxidation induced stacking faults (hereinafter referred to as OSFs) is formed, traces of particles originating from crystals (Crystal Originated Particles, hereinafter referred to as COP) are formed on the surface of the epitaxial layer. Also, a wafer is disclosed in which an invasive dislocation (Interstitial-type Large Dislocation Loop, hereinafter referred to as L / D) hardly occurs. The wafer of the present invention generates uniformly dense oxygen precipitates (Bulk Micro Defect, hereinafter referred to as BMD) in the wafer surface through heat treatment in the semiconductor device manufacturing process after the epitaxial layer is formed, and then in the wafer surface. Uniform intrinsic gettering (hereinafter referred to as IG) effect can be obtained.

In addition, the present invention is an epitaxial layer lamination silicon wafer having a resistivity of 0.02 Ωcm or less, with particles and interstitial dislocations due to crystals being 0 to 10 each per wafer. The present invention also relates to an epitaxial wafer in which an epitaxial layer having a resistivity of 0.1? Cm or more and a thickness of 0.5 to 5 mu m is formed on the wafer by CVD (chemical vapor deposition).

Description

Silicon Wafer for Deposition of an Epitaxial Layer and an Epitaxial Wafer and a Method for Manufacturing the Same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a silicon wafer for laminating an epitaxial layer of a thin film made by the Czochralski method (hereinafter referred to as CZ method), an epitaxial wafer on which an epitaxial layer is laminated, and a method of manufacturing the same.

Until now, epitaxial wafers have been first applied to high performance bipolar transistors and then to bipolar ICs. In an epitaxial wafer, an epitaxial layer of single crystal silicon having an arbitrary film thickness and resistivity can be formed on a silicon wafer serving as a substrate. Thus, for example, a high-resistance epitaxial layer is formed on a low resistance substrate to form a high-speed transistor. It can be realized. In addition, effective separation between the pn junction elements essential in the bipolar IC is effectively performed by the formation of the epitaxial layer. In recent years, in order to further improve the operation speed of transistors and to improve the performance, it is required to make the thickness of the epitaxial layer very thin.

However, in order to meet this demand, when the epitaxial layer is made very thin (for example, 3 µm or less), particles originating from crystals (Crystal Originated Particles, hereinafter referred to as COP) on the surface of the silicon wafer serving as the substrate, Problems arise when there is an interstitial-type large dislocation loop (hereinafter referred to as L / D). COP here is a defect due to the crystal being a kind of pit. When the mirror-polished silicon wafer is washed with a mixture of ammonia and hydrogen peroxide, pits are formed on the wafer surface, and when the wafer is measured with a particle counter, pits are also detected as particles with the original particles. In addition, L / D is one of the lattice defects of a crystal, and appears as a boundary between a smooth part and a non-smooth part inside a crystal, and is an intrusion type line defect in which the part in which the crystal lattice is broken is connected in a line shape. This L / D is also called a dislocation cluster, or is called a dislocation pit because pit is generated when the silicon wafer on which this defect has occurred is immersed in a selective etching solution containing hydrofluoric acid as a main component.

That is, when COP exists in the surface of the silicon wafer used as a board | substrate, the trace of COP will appear also on the epitaxial layer surface in the shape of this wafer surface. In addition, if L / D is potentially present on the surface of the silicon wafer serving as the substrate, the wafer under the epitaxial layer (substrate) is formed by heating the epitaxial furnace when forming the epitaxial layer on the wafer. L / D is present on the phase, and this L / D increases the defect density on the epitaxial layer surface.

On the other hand, in the CZ silicon wafer, ring-like oxidation-induced lamination defects (OSFs) that are present at the time of thermal oxidation of a semiconductor device manufacturing process may occur depending on the pulling rate at the time of pulling up a silicon single crystal. Oxygen precipitate nuclei which become oxygen precipitates are formed during crystal growth during crystal growth. The oxygen precipitates are formed by presenting the oxygen precipitate nuclei in the wafer by heat treatment such as an oxidation step in manufacturing a semiconductor device. OSF is due to this oxygen precipitate.

In the case where the silicon wafer serving as the substrate is a wafer in which OSF appears in this manner, or if traces of COP or L / D are present on the epitaxial layer surface, these traces of OSF or COP may have electrical characteristics, for example, aging of the oxide film. It may cause deterioration of dielectric breakdown characteristics (TDDB) and oxide voltage breakdown characteristics (TZDB). In addition, if the trace of COP and L / D are present on the epitaxial layer surface, a step occurs in the wiring process of the device, and this step causes disconnection and lowers the yield of the product.

In order to solve this problem, a thin film epitaxial wafer and a manufacturing method thereof are disclosed (Japanese Patent Laid-Open Nos. 10-209056 and 10-209057). That is, Japanese Patent Application Laid-Open No. 10-2O9O56 discloses that a single crystal silicon substrate having a COP density of 1 × 10 ⁵ or less / cm 3 or less and further having no COP on the surface or a small number thereof is produced by the CZ method. A method of forming an epitaxial layer having a thickness of less than 4.0 μm under reduced pressure and a thin film epitaxial wafer thereof are disclosed.

Further, Japanese Patent Application Laid-Open No. 10-209057 discloses that a single crystal silicon substrate having a high density of doped p-type impurities and no COP on the surface or a small number thereof is produced by the CZ method, and the thickness is reduced under reduced pressure on the substrate. A method of forming an epitaxial layer of less than 4.0 μm and a thin film epitaxial wafer thereof are disclosed.

According to these methods, for example, in the formation of an epitaxial layer having a thickness of 1 m, the number of COPs of 0.13 m or more on a 15.24 cm (6 inch) wafer can be 50 or less.

However, since both methods produce a silicon wafer serving as a substrate using a silicon single crystal pulled up at a relatively low speed of about 0.4 mm / min by the CZ method, the generation of COP can be suppressed in this silicon wafer. The problem that L / D is present on the epitaxial layer surface due to the generation of / D has not been solved.

In addition, as shown by the solid lines (a) to (c) of FIG. 15, when the CZ silicon wafer is a p-type wafer doped with B (boron) before forming an epitaxial layer on its surface, oxygen in the wafer is generally As the density was higher, oxygen precipitates (Bulk Micro Defect, hereinafter referred to as BMD) were generated at a higher density therein by heat treatment in the manufacturing process of the semiconductor device. This BMD has the effect of so-called intrinsic gettering (hereinafter referred to as IG), which captures trace amounts of heavy metal impurities that enter the device manufacturing process.

Further, as shown by the broken lines and dashed lines (d) to (f) in FIG. 15, the C-type silicon wafer is a p-type wafer doped with B after forming an epitaxial layer on the surface thereof, and the B density of the wafer is 10 ^18. In the case of less than atoms / cm 3, regardless of the high and low oxygen density, the occurrence of the BMD was suppressed and the IG effect was not sufficiently obtained. On the other hand, when the B density of the wafer is 10 ¹⁸ atoms / cm 3 or more, BMD is generated at the same density as that of the wafer before forming the epitaxial layer, and has an IG effect.

In addition, the said BMD density is the value calculated | required when heat-processing a silicon wafer at 750 degreeC for 8 hours and then 1000 degreeC for 16 hours.

However, in the CZ wafer pulled up under the condition of generating an OSF ring, when the B density is 10 ¹⁸ atoms / cm 3 or more, after forming the epitaxial layer, the portion corresponding to the ring is a portion other than the BMD. Although it occurs more densely, there is a problem that the generation of BMD is remarkably suppressed outside the OSF ring, and the IG effect is nonuniform within the wafer surface.

A first object of the present invention is to provide a silicon wafer for epitaxial layer lamination, which hardly generates traces of COP or L / D on the surface of the epitaxial layer when an OSF free (OSF free) epitaxial layer is formed. There is.

A second object of the present invention is an epitaxial wafer capable of producing uniformly high density BMD in the wafer surface through heat treatment in the semiconductor device manufacturing process after forming the epitaxial layer, and obtaining a uniform IG effect in the wafer surface; It is providing the manufacturing method thereof.

It is a third object of the present invention to provide an epitaxial wafer and a method for producing the same which have improved electrical characteristics and a large yield at the same time.

Fig. 1 shows, in the invention of the first embodiment, a vacancy predominant ingot is formed at the V / G ratio above the critical point based on the theory of Voronkov, and interstitial Si at the V / G ratio below the critical point. A diagram showing that a predominant ingot is formed.

2 is a characteristic diagram showing a change in the pulling speed for determining a desired pulling speed profile.

Fig. 3 is a schematic diagram of X-ray topography showing a void predominance region, interstitial Si predominance region, and perfect region of a reference ingot according to the invention of the first embodiment.

4 is a diagram illustrating a situation in which an OSF ring appears on a silicon wafer W ₁ corresponding to a position P ₁ in FIG. 3.

FIG. 5 is a position P ₂ of FIG. 3 selected and pulled up so that the OSF is present in the center only in the center, not in the shape of a ring in the center of the invention of the first embodiment. Sectional drawing of an ingot corresponding to the explanatory drawing of the silicon wafer W ₂ .

FIG. 6 is a view showing a state in which OSF appears on a disk in the center of the silicon wafer W ₂ of FIG. 3.

Of Figure 7 is a cross-sectional view and a silicon wafer of the ingot corresponding to the position of the first embodiment invention, the aggregate of the Si-type point defects between the aggregates and the grid of the void type point defects that do not exist in the Fig. ₃ P 3 W 3 Illustrative diagram.

8 is a plan view of the wafer described in FIG. 7;

9 is a diagram corresponding to FIG. 1 in the invention of the second embodiment.

FIG. 10 is a diagram illustrating a situation in which OSF does not appear on the silicon wafer W ₀ corresponding to the position P ₀ in FIG. 3.

11 is a view showing a situation of the number of COPs when the thicknesses of the epitaxial layers of Example 5 and Comparative Example 4 are changed.

The figure which shows BMD density distribution in the wafer surface in the wafer of the Example and the comparative example in invention of 3rd Embodiment.

13 is a plan view of a silicon wafer with OSF.

FIG. 14 is a view showing a change in the value of D ₁ / D ₀ when the B density is changed by making V / G constant. FIG.

15 is a diagram showing a relationship between B density and BMD density of a silicon wafer before and after forming an epitaxial layer.

<Overview of invention>

The first aspect of the present invention is characterized in that the resistivity of the silicon wafer for laminating the epitaxial layer is characterized in that particles (COP) and interstitial dislocations (L / D) attributable to crystals are each 0 to 10 per wafer. It is a silicon wafer of 0.02 Ωcm or less.

The second aspect of the present invention is an oxidation-induced lamination defect (OSF) when heat treated at an temperature range of 1000 ° C. ± 30 ° C. for 2 to 5 hours and then heat treated at 1130 ° C. ± 30 ° C. for 1 to 16 hours in an oxygen atmosphere. ) An epitaxial wafer having a silicon wafer which does not occur) and an epitaxial layer of a silicon single crystal having a thickness of 0.2 to 5 탆 formed on the wafer, and having zero particles due to crystals on the entire surface of the epitaxial layer. to be.

According to a third aspect of the present invention,

Pulling up the silicon single crystal ingot, slicing the ingot to produce a silicon wafer, and forming an epitaxial layer of silicon single crystal on the silicon wafer by chemical vapor deposition (CVD), The pulling rate is V (mm / min), and the temperature gradient in the axial direction at the center of the ingot is Ga (° C / mm) in the temperature range from the melting point of silicon to 1300 ° C., respectively, and at the periphery of the ingot. When the axial temperature gradient is Gb (° C./mm), the ingot is pulled up so that V / Ga and V / Gb are 0.23 to 0.50 mm 2 / min · ° C., respectively, and the thickness of the silicon wafer is 0.2 to 5 μm. An epitaxial layer of a silicon single crystal is formed.

According to a fourth aspect of the present invention, an oxide-induced lamination defect occurs when annealing in an oxygen atmosphere at a temperature range of 1000 ° C. ± 30 ° C. for 2 to 5 hours, followed by heat treatment at 1130 ° C. ± 30 ° C. for 1 to 16 hours. A silicon wafer for epitaxial layer lamination having a resistivity of 0.02 Ωcm or less, which is not generated at the center portion.

According to a fifth aspect of the present invention, a silicon single crystal ingot is pulled up while doping a p-type impurity to a predetermined density or more, a step of slicing the ingot to produce a silicon wafer, and a chemical vapor deposition method on the silicon wafer. Forming an epitaxial layer of a single crystal, wherein the pulling rate is V (mm / min) and the axial temperature gradient at the center of the ingot is in the temperature range from silicon melting point to 1300 ° C. (° C./° C.). mm), the oxidation-induced lamination defects at the center of the wafer are subjected to heat treatment for 2 to 5 hours at a temperature range of 1000 ° C. ± 30 ° C. and then heat treatment at a temperature range of 1130 ° C. ± 30 ° C. under an oxygen atmosphere for 1 to 16 hours. A method of manufacturing an epitaxial wafer, wherein the ingot is pulled up at a predetermined V / G so as not to occur.

<Embodiment of the invention>

[A] First, a first embodiment of the present invention will be described.

The silicon wafer for laminating the epitaxial layer of this embodiment is obtained by the CZ method from the silicon melt in the hot zone with a predetermined pulling rate profile based on the Voronkov theory. After pulling up, this ingot is sliced and manufactured.

In general, when pulling up the silicon single crystal ingot from the silicon melt in the hot zone furnace by the CZ method, point defects and agglomerates of point defects occur as defects in the silicon single crystal. There are two common types of point defects: void point defects and inter-grid Si point defects. Pore point defects are those in which one silicon atom deviates from one of its normal positions with a silicon crystal lattice. These voids become void point defects. On the other hand, if atoms are found at an interstitial site other than the lattice point of the silicon crystal, this becomes an interstitial Si point defect.

Point defects are usually formed at the contact surface between silicon melt (melted silicon) and ingot (solid silicon). However, by continuously pulling up the ingot, the portion that was the contact surface starts to cool down simultaneously with the pulling up. During cooling, the void point defects or interstitial Si point defects merge with each other by diffusion, and vacancy agglomerates of interstitial point defects or interstitial agglomerates of interstitial Si point defects are formed. In other words, aggregates are three-dimensional structures that arise due to merging of point defects.

The agglomerates of void type defects include defects called LSTD (Laser Scattering Tomograph Defects) or FPD (Flow Pattern Defects) in addition to the above-described COP, and the agglomerates of Si-type point defects between lattice defects such as L / D described above. Include. FPD is a source of traces that reveal the unique flow pattern that appears when chemically etching a silicon wafer made by slicing an ingot with Secco etchant for 30 minutes. LSTD has a different refractive index than silicon when irradiating infrared rays in a silicon single crystal. Is the source of the occurrence.

Boron Cove's theory states that the speed of pulling up the ingot to grow high purity ingots with few defects is V (mm / min), and the temperature gradient of the contact surface of the ingot-silicon melt in the hot zone structure is called G (° C / mm). V / G (mm2 / min 占 폚) is controlled. In this theory, as shown in Fig. 1, V / G graphically expresses pore density and interstitial Si density as a function, and explains that the boundary of the pore / lattice Si region on the wafer is determined by V / G. . More specifically, an ingot in which the void type defect predominantly exists when the V / G ratio is above the critical point is formed, whereas an ingot in which the lattice Si type defect is predominantly formed is formed when the V / G ratio is below the critical point.

The predetermined pulling rate profile of the first embodiment is characterized in that the ratio of the pulling rate (V / G) to the temperature gradient when the ingot is pulled from the silicon melt in the hot zone furnace is agglomerates of interstitial Si type point defects. Above the first critical ratio ((V / G) ₁ ) which prevents occurrence, the second critical ratio (limiting the aggregate of void point defects into the region where the void point defects in the center of the ingot predominantly exists (( V / G) ₂ ) to be kept below.

The profile of this pulling speed is determined based on the Voroncove theory by simulation by slicing the reference ingot in the axial direction experimentally or by combining these techniques. That is, this determination is made after the simulation, by checking the axially sliced and sliced wafers of the ingot, and repeating the simulation further. Several pulling speeds are determined in a predetermined range for the simulation, and a plurality of reference ingots are grown. As shown in Fig. 2, the pulling speed profile for the simulation is at a high pulling speed (a), such as 1.2 mm / min, at a low pulling speed (c) of 0.5 mm / min and again at a high pulling speed (d). Adjusted. The low pulling speed may be 0.4 mm / min or less, and the change in the pulling speeds (b) and (d) is preferably linear.

A plurality of reference ingots pulled up at different speeds are each sliced in the axial direction. The optimal V / G is determined from the correlation of the slicing in the axial direction, the identification of the wafer and the simulation result, and then the optimum pull rate profile is determined, from which the ingot is manufactured. The actual pull rate profile depends on a number of variables, including but not limited to the desired ingot diameter, the specific hot zone furnace used and the quality of the silicon melt.

When the drawing speed is lowered gradually to draw the cross section of the ingot when the V / G is continuously lowered, the fact shown in FIG. 3 can be seen. FIG. 3 shows the region where the void-type point defects predominantly exist in the ingot [V], the region where the inter-grid Si-type point defects predominantly exist [I], and the aggregates of the gap-type defects and the inter-lattice Si Perfect regions in which aggregates of mold point defects do not exist are shown as [P], respectively. 3, the axial position of the ingot is P _1, and includes a region in which the void-type point defects exist dominantly at the center. Position P ₂ comprises a region where a small void point defect predominantly exists in the center compared to position P ₁ . The position P ₄ includes a ring region where the interstitial Si type point defects predominantly exist and a central perfect region. The positions P ₃ are all perfect regions because there are no void point defects in the center and no Si-type point defects between lattice edges.

As is apparent from FIG. 3, the wafer W ₁ corresponding to the position P ₁ includes a region where the void point defect predominantly exists in the center. The wafer W ₂ corresponding to the position P ₂ includes an area in which a void point defect predominantly exists in a small area in the center compared with the wafer W ₁ . Wafer W ₄ corresponding to position P ₄ includes a central perfect region and a ring in which interstitial Si type point defects predominantly exist. In addition, a wafer W ₃ corresponding to the position P ₃ is all because no void-type point defects at the center, there is also Si type point defects at the edge portion of the interstitial area perfect.

In some areas in contact with the perfect area of the area where this void type point defect predominantly exists, and both are perfect areas, no COP or L / D occurs in the wafer surface. As shown in FIG. 4, in the wafer W ₁ , an OSF ring is generated near half of the wafer radius. As this heat processing condition, heat processing for 2 to 5 hours at the temperature of 1000 degreeC +/- 30 degreeC in oxygen atmosphere, and then heat-processing for 1 to 16 hours at the temperature of 1130 degreeC +/- 30 degreeC is mentioned, for example. The region where the void-type point defect surrounded by this OSF ring predominantly exists tends to exhibit COP. On the other hand, in the wafer W ₂ , the OSF does not become a ring, but only occurs in the center of the wafer.

The silicon wafer of the first embodiment is a wafer W ₂ or W ₃ in both the perfect area. As shown in Figs. 5 and 6, the silicon wafer W ₂ is manufactured by slicing ingots grown in a pulling velocity profile determined by selecting the OSF to be present in a disk only at the center thereof. In this silicon wafer W ₂ , since the OSF does not form a ring phase, COP and L / D are each 0 to 10 per wafer. 0 per wafer is also referred to as "COP free" or "L / D free". In addition, the silicon wafer W ₃ is fabricated by slicing ingots grown in the pulling velocity profile, which are all selected to make a perfect region as shown in FIG. 8 is a plan view thereof. The silicon wafer W about _3, COP and L / D is O to 10, each dog per wafer.

Here, "COP free" means that the COP number of 0.12 micrometers or more is substantially zero. In addition, since the size of COP may show a different value according to the manufacturer and model of a particle counter, in this specification, "0.12 micrometer COP" means the SFS 6200 series by the KLA-Tencor company of vertical incidence type, ADE COP which shows a value of 0.12 micrometer with each particle counter of CR80 series manufactured by LS Corporation, or LS 6000 series by Hitachi Denshi Engineering Corporation. In addition, the value measured by the said particle counter is a conversion value of polystyrene latex particle | grains, and is not an actual measured value by atomic force microscope (AFM).

Since the silicon wafer of the first embodiment has 0 to 10 COPs and L / Ds per wafer, respectively, even if the thickness of the epitaxial layer is very thin, the traces of COP and L / D on the surface of the epitaxial layer Rarely occurs. The number per COP and L / D per wafer refers to the number of wafers with a diameter of 30.48 cm (12 inches) or less.

An epitaxial layer by epitaxial growth of silicon is formed on the surface of the silicon wafer W ₂ or W ₃ produced by slicing the ingot pulled up under the above conditions. For the epitaxial growth, the CVD method is used from the viewpoints of crystallinity, mass production, simplicity of the device, and ease of forming various device structures. The epitaxial growth of silicon by CVD involves introducing a source gas containing silicon, such as SiCl ₄ , SiHCl ₃ , SiH ₂ Cl ₂ , SiH ₄ , together with H ₂ gas into the reactor, and the silicon wafer W on the surface of the ₂ or W ₃ is carried out by precipitation of the silicon produced by the thermal decomposition or reduction of the raw material gas. In particular, when forming an epitaxial layer of a thin film, reduced pressure CVD (1.3 to 2.0 kPa (10 to 15 Torr)) is preferable. By epitaxial growth in reduced pressure CVD, the epitaxial growth temperature can be reduced to form an epitaxial layer having a uniform thickness, and at the same time, the automatic doping of the thin film epitaxial layer from the high density substrate (wafer) can be suppressed. have.

When the epitaxial wafer is a high performance bipolar transistor or an epitaxial wafer for a bipolar IC, the silicon wafer serving as the substrate is produced with low resistance and the epitaxial layer is produced with high resistance. As such a silicon wafer W ₂ or W ₃ , a resistivity having a low resistivity of not more than O.O2 Ωcm, preferably from O.O1 to O.O2 Ωcm, more preferably 0.015 Ωcm or less is used, and as such an epitaxial layer, A resistivity of at least 5 Ωcm, preferably at least 10 Ωcm is used. This low-resistance silicon wafer is a dopant in p-type when the silicon single crystal is pulled up by the CZ method and has a density of B (boron) of 3 × 10 ¹⁸ atoms / cm 3 or more, and in the case of n-type dopant. Sb (antimony) is used at a density of 1 × 10 ¹⁸ atoms / cm 3 or more. In addition, when the epitaxial layer is formed of high resistance, a gas such as _{B 2 H 6, PH 3,} AsH 3 with a raw material gas is used.

When the thickness of the epitaxial layer of this embodiment is made very thin (0.2 to 5 mu m), when the transistor is fabricated from this epitaxial wafer, the operation speed of the transistor can be further improved and the performance can be improved. If the thickness is less than 0.2 µm, it is difficult to equalize the thickness of the epitaxial layer, and if the thickness exceeds 5 µm, high performance will not be achieved. Preferred thickness is 1 to 3 mu m.

[B] Next, a second embodiment of the present invention will be described.

The desired pull rate profile of this embodiment is such that when the ingot is pulled from the silicon melt in the hot zone furnace, the pull rate ratio (V / G) to the temperature gradient is limited to the void predominance region in the center of the ingot. The critical ratio ((V / G) ₃ ) is largely determined. The profile of this pulling speed is determined similarly to 1st Embodiment.

As shown in FIG. 3, in the axial position P ₀ of the ingot of this embodiment, all the regions are void predominant regions. As is clear from FIG. 3, in the wafer W ₀ corresponding to the position P ₀ , all regions are void predominant regions.

When the wafer W ₂ is heat treated as described above, as shown in FIG. 4, an OSF ring is generated in the vicinity of half of the wafer radius. The wafer W ₀ in the ingot corresponding to the position P ₀ As is larger toward the wafer W ₀ corresponds to the position P ₀ from the wafer W ₁ corresponding to the position P ₁ of the third diameter of the OSF ring is expanded, as shown in Figure 10 The OSF ring does not occur even if the thermal oxidation treatment is performed in excess of the diameter of.

In general, in the wafer W ₀ corresponding to the position P ₀ , a larger COP tends to appear from the periphery of the wafer toward the center of the wafer. Accordingly, the pulling method, which is the feature of the second embodiment, is a method of growing an area corresponding to the position P ₀ over the entire length of the ingot, and simultaneously sets the temperature gradient in the axial direction at the center of the ingot as Ga, The ingot is pulled up so that V / Ga and V / Gb are 0.23 to 0.50 mm 2 / min · ° C, respectively, when the temperature gradient in the axial direction is Gb. In this way, the number of COPs of 0.12 micrometers or more is 0.5 or less, and the COP number of less than 0.12 micrometers on the surface of the wafer is suppressed in the range of 3 to 10 / cm / cm2 at the center of the wafer. . OSF occurs when V / Ga and V / Gb are less than 0.23 mm 2 / min · ° C., and when it exceeds 0.5 mm 2 / min · ° C., the growth of silicon single crystal ingot becomes unstable.

COP of 0.12 micrometers or more is measured with the predetermined particle counter mentioned above. Of the COPs of less than 0.12 μm, COPs of 0.10 μm or more are measured with the predetermined particle counter described above. Or COP of less than 0.12 μm is measured by counting FPDs, or based on “Method of Detecting Micro Pits of Silicon Wafers” of Patent No. 2520316. This detection method cleans the wafer surface multiple times under a constant condition using an ammonia-based cleaning liquid until the number of feet of the silicon wafer surface can be measured using a particle counter, and at the same time, the number of feet of the wafer surface after cleaning. Is measured using this particle counter, and the wafer surface is re-washed under the same conditions, and the footage of the wafer surface after re-cleaning is measured using this particle counter, and the difference between these measurements and the measurement until It is a method of detecting the size and the number of micro pits on the wafer surface after one cleaning based on the number of cleaning.

In the silicon wafer of this embodiment, the oxygen density in the wafer is further controlled. In the CZ method, the oxygen density in the wafer is controlled by changing the flow rate of argon supplied into the hot zone furnace, the rotational speed of the quartz crucible storing the silicon melt, the pressure in the hot zone furnace, and the like. Oxygen precipitation when the semiconductor device manufacturer heat-treated in a semiconductor device manufacturing process by setting the oxygen density inside the wafer to be 1.2 × 10 ¹⁸ atoms / cm 3 to 1.6 × 10 ¹⁸ atoms / cm 3 (old ASTM) and distributing oxygen atoms throughout the wafer. Nuclei appear uniformly across the periphery at the center of the wafer to obtain a silicon wafer for IG. In order to make this oxygen density, for example, the flow rate of argon is 60 to 110 liters / minute, the rotation speed of the quartz crucible for storing the silicon melt is 4 to 12 rpm, and the pressure in the hot zone furnace is 2.7 to 10.7 kPa (20 to 80 Torr). A low oxygen density silicon wafer that does not require the IG effect controls the oxygen density inside the wafer to less than 1.2 x 10 ¹⁸ atoms / cm 3 (old ASTM). This wafer does not generate oxygen precipitation nuclei when the semiconductor device manufacturer heat-treats the semiconductor device manufacturing process. In order to achieve this oxygen density, for example, the flow rate of argon is 80 to 150 liters / minute, the rotation speed of the quartz crucible for storing the silicon melt is 4 to 9 rpm, and the pressure in the hot zone furnace is 2.0 to 8.0 kPa (15 to 60). Torr).

On the surface of the silicon wafer produced by slicing the ingot pulled up under the above conditions, a silicon single crystal thin film is formed by the epitaxial growth method. This epitaxial layer employs a chemical vapor deposition (CVD) method for epitaxial growth from the viewpoints of crystallinity, mass production, simplicity of devices, and ease of forming various device structures. The epitaxial growth of silicon by CVD method introduces a source gas containing silicon, such as SiCl ₄ , SiHCl ₃ , SiH ₂ Cl ₂ , SiH ₄ , together with H ₂ gas into the reactor, It can be performed by depositing the silicon | silicone produced | generated by pyrolysis or reduction of source gas on the surface at high temperature of about 1000-1200 degreeC. Here, by forming an epitaxial layer having a thickness of 0.2 to 5 mu m, not only COP of 0.12 mu m or more existing on the wafer surface before epitaxial layer formation is lost, but also COP of less than 0.12 mu m is easily lost. That is, the number of COPs on the entire wafer surface is zero (COP free). In the case of the atmospheric pressure CVD method, when the thickness of the epitaxial layer is less than 0.2 µm, the thickness of the epitaxial layer is not stable in the wafer surface. In the case of the reduced pressure CVD method, when the thickness of the epitaxial layer is less than 0.2 µm, the COP does not sufficiently disappear. In the case of a silicon wafer with an epitaxial layer for high integration, the upper limit of the thickness of the epitaxial layer is 5 µm or less, preferably 3 µm or less.

[C] In addition, a third embodiment of the present invention will be described.

The silicon wafer for laminating the epitaxial layer of this embodiment is produced by slicing the ingot after pulling up the ingot from the silicon melt in the hot zone furnace by the CZ method to a predetermined condition.

This predetermined condition is similar to the first and second embodiments in that the ingot pulling rate is V (mm / min), and the temperature gradient in the ingot vertical direction of the ingot-silicon melt contact surface in the hot zone structure is G (° C. / mm), it is determined by controlling V / G (mm2 / min 占 폚).

When this CZ silicon wafer is subjected to the above-described thermal oxidation treatment, ring-shaped OSF may occur. The OSF ring moves toward the outer circumferential side of the ingot as the V / G increases, and as the V / G decreases, the ring diameter decreases to become a disk at the center of the wafer and then disappear.

Moreover, this ring diameter changes with the doping amount of B (boron) which is a p-type impurity, even if V / G is made constant. 13, the diameter of the OSF ring diameter of D _1, D _0, and the wafer, showing the relationship between the density D ₁ / D ₀ and B are shown in Fig. As apparent from Fig. 14, the B density forms a ring at 2 × 10 ¹⁸ atoms / cm 3 or less, and becomes a disk at about 6 × 10 ¹⁸ atoms / cm 3, and disappears when it is 9 × 10 ¹⁸ atoms / cm 3 or more.

In the silicon wafer of the third embodiment, when doping B (boron) at a predetermined density of 4 × 10 ¹⁸ atoms / cm 3 or more, OSF generated in a ring shape when thermal oxidation is performed by controlling V / G is carried out at the center of the wafer. It is a wafer which was made to disappear from. On the surface of this silicon wafer, an epitaxial layer by epitaxial growth of silicon is formed by CVD method. As described above, when the doping density of B is high and the thermal oxidation treatment is performed, silicon wafers in which OSF disappears at the center of the wafer generate BMD at uniform and high density within the wafer surface even after the epitaxial layer is formed. Uniform IG effect can be obtained. In addition, L / D does not appear at all on the wafer before the epitaxial layer is formed. This is presumably because the formation of agglomerates of interstitial Si type point defects is controlled because B atoms doped at high density are bonded to interstitial Si and the interstitial Si density decreases. Therefore, even if the epitaxial layer is formed on the wafer surface, no trace of L / D transfer occurs on the epitaxial layer surface.

Since the silicon wafer of the third embodiment dopes B (boron) at 4 × 10 ¹⁸ atoms / cm 3 or more, the resistivity becomes low resistance of 0.22 cm or less. If the epitaxial layer is made high in resistance here, it becomes an epitaxial wafer suitable for the epitaxial wafer for a high performance bipolar transistor or a bipolar IC. In forming the high-resistance epitaxial layer, a gas such as B ₂ H ₆ is used simultaneously with the source gas.

Next, the Example of this invention is described with a comparative example.

<Example 1>

The ingot was pulled up so as to grow the area corresponding to the position P ₂ shown in FIG. 3 over the entire length of the ingot. At this time, it was doped with B (boron) as dopant at a density of 1 × 10 ^l9 atoms / ㎤. A silicon wafer (wafer W _{2 in} FIG. 3) sliced from this silicon single crystal ingot was wrapped, and a silicon wafer having a resistivity of 0.02 Ωcm and a diameter of 20.32 cm (8 inches) was prepared by lapping and performing mirror polishing.

A size defect of 0.09 탆 or more (including COP) on the surface of the silicon wafer was investigated using a laser particle counter (SFS 6200, manufactured by KLA-Tencor). As a result, 10 pieces were observed per wafer.

SiH ₂ Cl ₂ is used as the source gas on the silicon wafer surface by the reduced pressure CVD method (10.7 kPa (80 Torr)), and B ₂ H ₆ gas is used for adjusting the resistance of the epitaxial layer, and the growth temperature is 1080 ° C., An epitaxial layer having a thickness of 3 µm and a resistivity of 5 Ωcm was formed under conditions of a growth rate of 1 µm / min. This obtained the epitaxial wafer of the high resistance epitaxial layer on the low resistance board | substrate.

Size defects (including COP and L / D) of 0.09 μm or more on the surface of this epitaxial wafer were irradiated using the same laser particle counter as above. As a result, detection was impossible at 0.09 micrometers or more and less than 0.13 micrometers, and three pieces per wafer were observed at 0.13 micrometers or more.

<Example 2>

The ingot was pulled up so that the area corresponding to the position P ₃ shown in FIG. 3 was grown over the entire length of the ingot. At this time, B (boron) was doped at a density of 1 × 10 ¹⁹ atoms / cm 3 as a dopant. Silicon wafers sliced from the silicon single crystal ingot (wafer of Figure 3 W ₃₎ for wrapping, and all AD cutter after carrying out a processing by mirror-polishing a resistivity of 0.02 Ωcm, a diameter of preparing the silicon wafer 20.32 cm (8 in.) It was.

Size defects (including COP and L / D) of 0.09 μm or more on the surface of the silicon wafer serving as the substrate and the surface of the epitaxial wafer were investigated using the same laser particle counter as in Example 1. As a result, ten were observed on the silicon wafer surface serving as the substrate and seven per wafer on the epitaxial wafer surface.

Comparative Example 1

The ingot is pulled up to grow the area corresponding to position P ₄ shown in FIG. 3 over the entire length of the ingot, and in the same manner as in Example, a silicon wafer (wafer W ₄ of FIG. 3) having a diameter of 20.32 cm (8 inches) is obtained. Got it. When pulled up, B (boron) was doped in the same manner as in the example. Otherwise, an epitaxial wafer was produced in the same manner as in Example.

Size defects (including COP and L / D) of 0.09 μm or more on the surface of the silicon wafer serving as the substrate and the surface of the epitaxial wafer were examined using the same laser particle counter as in the example. As a result, 100 wafers per wafer were observed on the silicon wafer surface and the epitaxial wafer surface serving as substrates, respectively.

<Example 3>

At the same time, the temperature gradient in the axial direction at the center of the ingot is made Ga and the temperature gradient in the axial direction at the periphery of the ingot is made Gb so that the area corresponding to the position P ₀ shown in FIG. 3 is grown over the entire length of the ingot. At that time, the ingot was pulled up so that V / Ga and V / Gb were about 0.25 mm 2 / min. 占 폚, respectively. At this time, in order to control the oxygen density in the ingot, the flow rate of argon was about 110 liters / minute, the rotation speed of the quartz crucible storing the silicon melt was about 5 to 10 rpm, and the pressure in the hot zone furnace was about 8.0 kPa (60 Torr). ).

The silicon wafer sliced from the ingot thus pulled up was wrapped, edge-cut and mirror polished to prepare a silicon wafer having a diameter of 20.32 cm (8 inches) and a thickness of 740 µm. Five silicon wafers were prepared for the measurement of COP number, and another five sheets were used for measuring the oxygen density in the wafer.

<Example 4>

The silicon wafer obtained in the same manner as in Example 3 was used to investigate whether the OSF was present. In addition, for each of the five separate silicon wafers, silicon tetrachloride (SiCl ₄ ) was reduced to hydrogen (H ₂ ) gas on each surface by a reduced pressure CVD method (10.7 kPa (80 Torr)). An epitaxial layer of was formed.

The number of COP of 0.12 micrometers or more in the circle | round | yen of 200 mm of surface diameter of each of the 5 silicon wafers of Example 3 and Example 4 was investigated using the laser particle counter (SFS 6200 by KLA-Tencor). The number of COPs of less than 0.12 μm in a circle of 200 mm in diameter on the surface of each of the same five silicon wafers was measured using the same laser particle counter based on the "Method for Detecting Fine Pits of Silicon Wafers" of Patent No. 2520316 described above. . The results are shown in Table 1.

When measuring using the same laser particle counter for comparison, a silicon wafer in which the number of COPs having a size of less than 0.1 micrometer is 5 / cm2 and the number of COPs having at least 0.1 micrometer is 1 / cm2 is present It was set to two. An epitaxial layer having a thickness of 1 μm was formed on the surface of the silicon wafer in the same manner as in Example 1. The silicon wafer with this epitaxial layer was set as Comparative Example 3.

Oxygen density of 5 占 퐉 depth from each of the five separate silicon wafer surfaces of Example 3 and Comparative Example 2 was measured by secondary ion mass spectrometry (SIMS). The average value is shown in Table 1. The average of each of these is shown in Table 1.

COP number (pcs / cm ² ) Oxygen Density × 10 ¹⁸ (Atom / cm ³ ) (Old ASTM) OSF presence Before epitaxial layer formation After epitaxial layer formation <0.12 μm ≥0.12 μm <0.12 μm ≥0.12 μm Example 3 6.5 0.35 - - 1.32 - Example 4 - - 0 0 - none Comparative Example 2 5 One - - 1.34 - Comparative Example 3 - - 0 0.5 - none

As is clear from Table 1, the COP number of less than 0.12 µm was 5 pieces / cm 2 in the silicon wafer of Comparative Example 2, while the average was 6.5 pieces / cm 2 in the silicon wafer of Example 3. In addition, the number of COPs of 0.12 micrometers or more was 1 / cm <2> in the silicon wafer of the comparative example 2, but was 0.35 pieces / cm <2> in average on the silicon wafer of Example 3. Both the silicon wafers of Example 3 and Comparative Example 2 had an oxygen density of about 1.3 × 10 ¹⁸ atoms / cm 3, which was suitable for IG wafers.

In addition, the OSF of the silicon wafer of Comparative Example 3 is current, and at the same time, the average number of COPs of less than 0.1 micrometer of O.12 / cm2 and the average number of COPs of 0.12 micrometer or more are 0.5 units / cm2. In the silicon wafer of Example 4, the OSF was not currentized, and at the same time, the wafer was not detected for COP of 0.12 µm or more and of COP of less than 0.12 µm.

That is, COP of less than 0.12 탆 existing in the wafer of Comparative Example 2 was not lost in the wafer of Comparative Example 3 in which the epitaxial layer was formed. This is considered to be because the COP of the wafer of Comparative Example 2 is larger than the COP of the wafer of Example 3, so that only an epitaxial layer having a thickness of about 1 μm is formed and is not completely lost.

<Example 5 and Comparative Example 4>

It is necessary to use the reduced pressure CVD method for formation of a thin film epitaxial layer. When the wafers of Example 1 and Comparative Example 1 were used under reduced pressure (10.7 kPa (80 Torr)) and the thickness of the epitaxial layer was changed to 0.2 µm, 3 µm, 5 µm, 7 µm and 10 µm, The number of each COP per wafer was obtained. The results are shown in FIG. As is clear from Fig. 11, when the epitaxial layer was formed on the wafer surface of Example 5, all of the COP was lost from the 0.2 mu m thickness and COP-free, whereas the epitaxial layer was formed on the wafer surface of Comparative Example 4. When it formed, it turned out that COP only disappeared at 5 micrometers.

<Example 6>

V / G is set so that D ₁ / D ₀ shown in FIG. 13 when the dopant is not doped is 0.9, and the dopant B is doped at a density of 9 × 10 ¹⁸ atoms / cm 3 at this V / G. Silicon single crystal ingots were pulled up. The silicon wafer sliced from this ingot was wrapped, and the surface was polished and subjected to mirror polishing to prepare a p ⁺⁺ type silicon wafer having a resistivity of 0.01 Ωcm and a size of 15.24 cm (6 inches). When the wafer was heat-treated at 1100 ° C. for 1 hour in an oxygen atmosphere, no OSF occurred in the ring shape or the disk shape.

SiHCl ₃ is used as the source gas on the silicon wafer surface by atmospheric pressure CVD (101.3 kPa (760 Torr)), and B ₂ H ₆ gas is used for adjusting the resistance of the epitaxial layer. An epitaxial layer having a thickness of 5 µm and a resistivity of 10 OMEGA cm was formed under the condition of 3 µm / min. This obtained the epitaxial wafer of a low resistance board | substrate and a high resistance epitaxial layer.

According to the semiconductor device manufacturing process, this epitaxial wafer was heat-processed at 750 degreeC for 8 hours, and then at 1000 degreeC for 16 hours. After the heat treatment, the wafer was cleaved and again, the epitaxial layer and the wafer surface below it were selectively etched with a bright etching solution, and observed from an optical microscope from the wafer center to the periphery of the wafer at a depth of 300 μm. The BMD of was measured and the density was calculated | required. The results are shown in Fig. 12 (a).

Comparative Example 5

Except for doping B (boron) at a density of 2 x 10 ¹⁷ atoms / cm 3, the silicon single crystal ingot was pulled up at the same V / G as in Example 6, and in the same manner as in Example 6, the resistivity was 0.15 Ωcm and the size was A p ⁺ type silicon wafer having a thickness of 15.24 cm (6 inches) was fabricated. When the wafer was heat-treated under the same conditions as in Example 6, the OSF appeared on the periphery side of the wafer (D ₁ / D ₀ = 0.9) in a ring shape.

An epitaxial layer having a thickness of 5 µm and a resistivity of 10 Ωcm was formed on the surface of this silicon wafer under the same conditions as in Example 6 to obtain an epitaxial wafer. This epitaxial wafer was heat-treated in the same manner as in Example 6 to determine the BMD density from the center of the wafer to the periphery. The results are shown in Figure 12 (b).

Comparative Example 6

When pulled up, B (boron) was doped to have the same density (9 × 10 ¹⁸ atoms / cm 3) as in Example 6, and the silicon single crystal ingot was pulled up so that V / G was large (D ₁ / D ₀ = 0.3). Otherwise, in the same manner as in Example 6, a p ⁺⁺ type silicon wafer having a resistivity of 0.01 Ωcm and a size of 15.24 cm (6 inches) was obtained. When the wafer was heat-treated under the same conditions as in Example 6, the OSF appeared in the center of the wafer in a ring shape. An epitaxial wafer having a thickness of 5 µm and a resistivity of 10 Ωcm was formed on the silicon wafer surface under the same conditions as in Example 6 to obtain an epitaxial wafer. This epitaxial wafer was heat-treated in the same manner as in Example 6 to determine the BMD density from the center of the wafer to the periphery. The results are shown in FIG. 12 (c).

Comparative Example 7

When doping B (boron) at a density of 1.4 × 10 ¹⁵ atoms / cm 3 and reducing the V / G and thermally oxidizing it as compared with Example 6, V / G in which the OSF generated in the ring phase disappears at the center of the wafer The silicon single crystal ingot was pulled up, and a p ⁻ type silicon wafer having a resistivity of 10 Ωcm was produced in the same manner as in Example 6. An epitaxial layer having a thickness of 5 m, a resistivity of 10 Ωcm, and a size of 15.24 cm (6 inches) was formed on the silicon wafer surface under the same conditions as in Example 6 to obtain an epitaxial wafer. This epitaxial wafer was heat-treated in the same manner as in Example 6 to determine the BMD density from the center of the wafer to the periphery. The results are shown in Fig. 12 (d).

Comparative Evaluation

As Jean's also apparent from 12 (a), an embodiment in a laminated epitaxial wafer of hexavalent BMD density has an approximately 1.3 × ¹⁰ 10 gae / ㎤ a high density between the to the periphery from the center of the wafer, and also uniformity It was. Thus, in a multilayer epitaxial layer according to Comparative Example 5 for the BMD density in the wafer, but the wafer periphery winning about 0.5 × ¹⁰ 10 gae / ㎤, that the other part BMD is not rare (12 (b) too). Further, in the wafer on which the epitaxial layer of Comparative Example 6 was laminated, the BMD density of the portion corresponding to the OSF ring was about 1.8 × 10 ¹⁰ / cm 3, but the BMD density at the center of the wafer was about 1.0 × 10 ¹⁰ / It was cm 3 and the BMD density of the wafer peripheral portion was about 0.6 × 10 ¹⁰ / cm 3, which was uneven in the wafer surface (FIG. 12 (c)). Moreover, in the wafer which laminated | stacked the epitaxial layer of the comparative example 7, hardly BMD generate | occur | produced over the whole wafer surface (FIG. 12 (d)). As a result, the epitaxial wafers of Comparative Examples 5 and 7 had a low IG effect, and the epitaxial wafers of Comparative Example 6 had a nonuniform IG effect in the wafer plane. On the other hand, it was found that the epitaxial wafer of Example 6 had a high IG effect.

Each epitaxial wafer of Example 6 and Comparative Examples 5 to 7 was immersed in a Secco etchant without stirring for 2 minutes, and after finding the presence or absence of a specific flow pattern which appeared accordingly, the part which becomes the source of this trace was Observation with an optical microscope examined the presence or absence of traces of transcription of L / D. As a result, there was no trace of L / D transfer over the entire epitaxial wafer surface of Example 6 and Comparative Example 6 having a relatively high B density. In contrast, traces of L / D were observed on the epitaxial wafers of Comparative Example 7 in which the B density was relatively low and the ring-shaped OSF was extinguished in the center portion. In particular, in Comparative Example 7 with a B density of 10 ¹⁵ atoms / cm 3, 20 to 300 wafers were observed per wafer.

As described above, according to the present invention, when the epitaxial layer of the thin film is formed by using a silicon wafer which hardly generates COP or L / D in the wafer surface, the epitaxial layer is formed. Almost no COP or L / D is generated on the surface, and the surface is OSF free.

In addition, when the heat treatment is performed in the semiconductor device manufacturing process, oxygen precipitation nuclei may be uniformly distributed from the center of the wafer to the periphery, thereby producing a silicon wafer for IG, which may be a source of inherent gettering (IG).

Further, since the silicon wafer whose resistivity is 0.02 Ωcm or less and the oxidation-induced stacking defect occurring on the ring during thermal oxidation disappears at the center of the wafer is used as the epitaxial layer lamination substrate, the epitaxial layer is formed on the wafer surface. When the heat treatment is performed, uniformly high density BMD is generated in the wafer surface, and a uniform IG effect can be obtained in the wafer surface. When the epitaxial layer is formed, no trace of L / D transfer occurs on the epitaxial layer. As a result, an epitaxial wafer can be obtained which further improves electrical characteristics and has a large yield at the same time.

Claims (11)

The ingot is pulled up from a silicon melt in a hot zone furnace by a Czochralski method to a predetermined pulling speed profile, and then manufactured by slicing the ingot. The predetermined pull rate profile is such that the ratio of pull rate (V / G) to temperature gradient when the ingot is pulled from the silicon melt in the hot zone furnace prevents the formation of agglomerates of lattice Si type defects. first critical ratio ((V / G) ₁₎ above, and the second critical ratio ((V / G) ₂₎ for restricting into the gap-shaped region which point defects exist dominantly in the aggregate of the air gap-type point defects at the center of the ingot Determined to remain below, and An epitaxial layer lamination silicon wafer having a resistivity of 0.02 Ωcm or less and a diameter of 30.48 cm (12 inches) or less, each having particles of 10 to 10 per wafer due to crystals and interstitial dislocations. After the ingot is pulled from the silicon melt in the hot zone furnace by the Czochralski method to a predetermined pulling speed profile, the resistivity is 0.1? Is formed an epitaxial layer of silicon single crystal having a thickness of 0.2 to 5 μm, The predetermined pull rate profile is such that the ratio of pull rate (V / G) to temperature gradient when the ingot is pulled from the silicon melt in the hot zone furnace prevents the formation of agglomerates of lattice Si type defects. first critical ratio ((V / G) ₁₎ above, and the second critical ratio ((V / G) ₂₎ for restricting into the gap-shaped region which point defects exist dominantly in the aggregate of the air gap-type point defects at the center of the ingot Determined to remain below, and The silicon wafer has an resistivity of 0.02 Ωcm or less and a diameter of 30.48 cm (12 inches) or less, and an epitaxial wafer having 0 to 10 particles per particle and breakthrough potential due to crystals, respectively. A silicon wafer that does not cause oxidation-induced lamination defects when the heat treatment is performed in an oxygen atmosphere at a temperature range of 1000 ° C. ± 30 ° C. for 2 to 5 hours followed by a heat treatment of 1130 ° C. ± 30 ° C. for 1 to 16 hours, and the silicon An epitaxial wafer comprising an epitaxial layer of silicon single crystals having a thickness of 0.2 to 5 탆 formed on a wafer, wherein the number of particles due to crystals of the entire surface of the epitaxial layer is zero. The epitaxial wafer according to claim 3, wherein the oxygen density in the silicon wafer is 1.2 x 10 ¹⁸ atoms / cm 3 to 1.6 x 10 ¹⁸ atoms / cm 3 (formerly ASTM), and oxygen atoms are distributed throughout the silicon wafer. 4. The epitaxial wafer according to claim 3, wherein the oxygen density in the silicon wafer is less than 1.2 x 10 &lt; ¹⁸ &gt; atoms / cm &lt; 3 &gt; (formerly ASTM), and an aggregate of void point defects is distributed throughout the silicon wafer. Pulling up a silicon single crystal ingot, slicing the ingot to manufacture a silicon wafer, and forming an epitaxial layer of silicon single crystal on the silicon wafer by chemical vapor deposition; The pulling rate is V (mm / min), and the temperature gradient in the axial direction at the center of the ingot is Ga (° C / mm) in the temperature range from the melting point of silicon to 1300 ° C, respectively, and the axis at the periphery of the ingot. When the temperature gradient in the direction is Gb (° C./mm), the ingot is pulled up so that V / Ga and V / Gb are 0.23 to 0.50 mm 2 / min · ° C., respectively. A method of manufacturing an epitaxial wafer, characterized in that the epitaxial layer of silicon single crystal having a thickness of 0.2 to 5 ㎛ is formed on the surface of the silicon wafer. Oxidation-induced lamination defects do not occur at the center of the wafer when heat treated for 2 to 5 hours in an oxygen atmosphere at a temperature range of 1000 ° C. ± 30 ° C., and then heat treated for 1 to 16 hours at a temperature range of 1130 ° C. ± 30 ° C. A silicon wafer for epitaxial layer lamination having a resistivity of 0.02 Ωcm or less. The resistivity of the silicon wafer is 0.02 Ωcm or less, and at the same time, heat treatment is performed for 2 to 5 hours in an oxygen atmosphere at a temperature range of 1000 ° C ± 30 ° C, followed by heat treatment for 1 to 16 hours at a temperature range of 1130 ° C ± 30 ° C. An epitaxial wafer, wherein an epitaxial layer of silicon single crystal having a resistivity of at least 0.1 Ωcm and a thickness of 0.2 to 5 탆 is formed on a silicon wafer by chemical vapor deposition, characterized in that defects do not occur at the center of the wafer. pulling up a silicon single crystal ingot while doping a p-type impurity to a predetermined density or more, slicing the ingot to manufacture a silicon wafer, and forming an epitaxial layer of silicon single crystal on the silicon wafer by chemical vapor deposition. Including steps When the pulling speed is V (mm / min) and the temperature gradient in the axial direction at the center of the ingot is G (° C / mm) in the temperature range from the melting point of silicon to 1300 ° C, 1000 ° C ± When heat-treated for 2 to 5 hours at a temperature range of 30 ° C., and then heat-treated for 1 to 16 hours at a temperature range of 1130 ° C. ± 30 ° C., the ingot at a predetermined V / G so as not to cause an oxidation-induced stacking defect in the center of the wafer. Method for producing an epitaxial wafer, characterized in that to raise the. 10. The method according to claim 9, wherein the predetermined V / G heat-treats at a temperature range of 1000 ° C. ± 30 ° C. for 2 to 5 hours in an oxygen atmosphere when doping the p-type impurity below a predetermined density, and then 1130 ° C. ± 30 ° C. A method of producing an epitaxial wafer, wherein the oxidative-induced lamination defect occurs in the wafer in a ring shape or a disk shape when the heat treatment is performed for 1 to 16 hours in a temperature range of ° C. The method of manufacturing an epitaxial wafer according to claim 9, wherein the boron as a p-type impurity is doped to a density of 4 x 10 ¹⁸ atoms / cm 3 or more.