KR100369767B1 - Silicon Wafer, Heat Treatment Method of the Same, and the Heat-treated Silicon Wafer - Google Patents

Abstract

In the present invention, particles and invasive dislocations due to crystals do not occur in the wafer surface, and a thickness of 0.1 to 1.6 µm is provided on the back surface of the silicon wafer having an oxygen concentration of 1.2 x 10 ¹⁸ atoms / cm 3 or less (formerly ASTM). Forming a polysilicon layer by chemical vapor deposition at a temperature of 670 ° C. ± 30 ° C., heat-treating the silicon wafer with the polysilicon layer at a temperature of 1000 ° C. ± 30 ° C. under an oxygen atmosphere for 2 to 5 hours, Subsequently, the present invention relates to a heat treatment method of a silicon wafer, which includes a step of heat treatment for 1 to 16 hours at a temperature of 1130 ° C ± 30 ° C. When the silicon wafer without the polysilicon layer is formed as described above, an oxide induced stacking defect (OSF) appears in the center of the wafer. Even when OSF appearance heat treatment is performed, there is no OSF and COP, and evenly deposits oxygen on all sides of the wafer, thereby providing a uniform gettering effect without variation between the wafer edge and the center of the wafer.

Description

Silicon Wafer, Heat Treatment Method of the Same, and the Heat-treated Silicon Wafer

The present invention relates to a heat treatment method of a silicon wafer made by the Czochralski method (hereinafter referred to as a CZ method) and used for manufacturing a semiconductor integrated circuit, a wafer used in the method, and a wafer heat treated by the method. will be.

As a cause of lowering the yield in the process of manufacturing a semiconductor integrated circuit in recent years, micro-defects of oxygen precipitates, which are nuclei of an oxide induced stacking fault (OSF), and particles due to crystals (Crystal Originated Particle) , Hereinafter referred to as COP), and the presence of interstitial-type large dislocation (hereinafter referred to as L / D). The OSF is introduced in a microdefect that becomes its nucleus at the time of crystal growth and appears in an oxidation process or the like when manufacturing a semiconductor device, and causes a defect such as an increase in leakage current of the manufactured device. When the silicon wafer after the mirror polishing is washed with a mixture of ammonia and hydrogen peroxide, pits are formed on the wafer surface. When the wafer is measured by a particle counter, pits are also detected as particles with the original particles. The pit is due to the crystal and is called COP to distinguish it from the original particle. COP, which is a pit on the wafer surface, causes damage to electrical characteristics, for example, time-dependent dielectric breakdown (TDDB), oxide breakdown voltage (TZDB), and the like of the oxide film. In addition, if COP exists on the wafer surface, a step is generated in the wiring process of the device, and this step may cause disconnection. In addition, leakage of the device may also cause leakage of the device, thereby reducing the yield of the product.

L / D is also called dislocation cluster, or it is also called dislocation pit because pit is generated when the silicon wafer which caused this defect is immersed in the selective etching liquid containing hydrofluoric acid as a main component. L / D also impairs electrical characteristics, such as leakage characteristics and insulation characteristics.

For this reason, it is desired to reduce OSF, COP and L / D from silicon wafers used in the manufacture of semiconductor integrated circuits.

A method for producing a defect-free silicon single crystal that does not generate OSF, dislocation clusters (L / D), and the like is disclosed in Japanese Patent Laid-Open Nos. 8-330316 and 11-1393. In the method disclosed in Japanese Patent Application Laid-Open No. 8-330316, the OSF generated in a ring form when thermal oxidation is performed on a silicon wafer is extinguished at the center of the wafer, and at a low speed so that dislocation clusters (L / D) are removed from the front surface of the wafer. It is a method of growing a silicon single crystal.

However, in this method, both the range of the pulling rate of the silicon single crystal and the range of the temperature gradient in the axial direction of the silicon single crystal for producing an intact silicon single crystal are relatively narrow and the diameter of the pulling silicon single crystal increases as the diameter increases. It is difficult to produce a defect-free silicon single crystal, and when the wafer is formed into a wafer due to fluctuations in pulling speed or the like, OSFs sometimes appear in the center of the wafer rather than in a ring shape. As described above, the OSF deteriorates the junction leakage characteristic, and thus improvement has been desired.

Moreover, the method disclosed by Unexamined-Japanese-Patent No. 11-1393 consists of a perfect area [P], when the perfect area | region where an aggregate of a gap type | mold defect and an aggregate of a lattice silicon type point defect do not exist respectively is called [P]. It is a method of pulling a silicon single crystal ingot from a silicon melt. The silicon wafer sliced from this ingot consists of a perfect region [P]. The perfect region [P] is sandwiched between the region [I] where the interstitial silicon type defects dominate, and the region [V] where the gap type defects dominate in the silicon single crystal ingot. In the silicon wafer composed of the perfect region [P], the pulling speed of the ingot is V (mm / min), and the temperature gradient in the ingot vertical direction near the interface between the silicon melt and the ingot is G (° C / mm). In this case, the value of V / G (mm 2 / min · ° C.) is determined so that the OSF generated in a ring shape during thermal oxidation treatment disappears at the center of the wafer.

Some semiconductor device manufacturers, on the other hand, require silicon wafers that do not have OSF, COP, and LD, as well as the ability to getter metal contamination from device processes. If the wafer is not sufficiently equipped with gettering capability, contamination by metal in the device process may result in defects in operation of the device due to junction leakage or trap levels caused by metal impurities, and the yield of the product may be lowered. In order to solve this problem, a silicon wafer that exhibits an intrinsic gettering (IG) effect by heat treatment in a device process of a device maker is desired.

However, the silicon wafer cut out from the ingot made of the perfect region [P] described above does not have OSF, COP, and L / D, but oxygen precipitation does not necessarily occur inside the wafer due to the heat treatment of the device manufacturing process, thus IG There was a drawback that the effect was not sufficiently obtained.

In the conventional device process, a silicon wafer treatment method for exerting an IG effect on a silicon wafer is a method in which defects or impurities are deliberately added to the inside of the wafer in advance. Silicon wafers treated in this way absorb the contamination that occurs during subsequent processes around defects previously made in the wafer. As a result, defects or contaminations can be prevented from occurring in the vicinity of the wafer surface from which the device is made.

On the other hand, in recent years, due to the high integration of devices, the heat treatment temperature in the device process tends to be lowered to 1000 ° C. or lower, and as a result of this low temperature, a low temperature is strongly demanded even in the pre-process IG treatment.

For this reason, the step of introducing a precipitation nuclei of oxygen into the wafer by holding the silicon wafer immediately after being cut out from the silicon single crystal ingot and ground and polished at 500 to 800 ° C. for 0.5 to 20 hours, and the oxygen A step of rapidly heating a silicon wafer containing precipitated nuclei from room temperature to 800 to 1000 ° C. for 0.5 to 20 minutes, and a step of leaving the silicon wafer rapidly heated to 0.5 room temperature for 20 minutes to cool to room temperature, and thus An IG treatment method is disclosed that includes heating a cooled silicon wafer from 500 to 700 ° C. at a rate of 2 to 10 ° C./minute and maintaining it at that temperature for 2 to 48 hours. 45945).

In this processing method, when rapidly heated at the above temperature conditions, not only the surface of the wafer but also the inside of the wafer are temporarily below the thermal equilibrium concentration, and interstitial silicon atoms are deficient, resulting in stable oxygen precipitation nuclei. It is easy to grow. At the same time, the lattice silicon atoms are generated on the wafer surface in order to compensate for these deficient interstitial silicon atoms and become stable, and the resulting interstitial silicon atoms begin to diffuse into the wafer. The vicinity of the wafer surface, which was in the state of lack of interstitial silicon atoms, becomes saturated immediately due to the formation of interstitial silicon atoms, and the oxygen precipitate nuclei start to disappear. However, the interstitial silicon atoms generated on the wafer surface require some time to diffuse to the inside of the wafer, so that the environment where the oxygen precipitation nuclei tend to grow longer as the deeper from the wafer surface goes into the inside. Therefore, the closer to the wafer surface, the lower the density of the oxygen precipitation nuclei, and the longer the heat treatment time (0.5 to 20 minutes), the thickness of the oxygen precipitation nuclei, i.e., the layer where defects are not formed (hereinafter referred to as DZ). Becomes large. In addition, the higher the temperature in the range of 800 to 1000 ° C., the larger the diffusion coefficient of interstitial silicon atoms is, so that the thickness of DZ increases in a short time.

When heated rapidly and left at room temperature to cool, and then heated again to 800 to 1100 ° C., oxygen precipitate nuclei in the wafer survived by rapid heating grow to become oxygen precipitates, and become stable IG sources. In the present specification, the oxygen precipitate is hereinafter referred to as BMD (Bulk Micro Defect).

However, the IG treatment method is a pretreatment for generating an IG source, and requires a step of introducing oxygen precipitation nuclei into the wafer by maintaining the silicon wafer immediately after grinding and polishing at 500 to 800 ° C. for 0.5 to 20 hours, and further rapidly. After heating, heat treatment for growing oxygen precipitated nuclei in the wafer into BMD was required. For this reason, there existed a problem that the frequency | count of heat processing in a wafer state has many.

A first object of the present invention is to provide a heat treatment method for a silicon wafer without COP, which does not generate OSF due to thermal oxidation, even when a wafer in which OSFs are collected at the center of a wafer when a conventional OSF appearance heat treatment is used. .

A second object of the present invention is silicon with a polysilicon layer, in which the deposition of oxygen is uniform on all sides of the wafer and a uniform gettering effect is obtained without variation between the edge of the wafer and the center of the wafer. It is to provide a wafer and a method of manufacturing the same.

A third object of the present invention is a silicon wafer cut out from an ingot having an oxygen concentration of 0.8 × 10 ¹⁸ to 1.4 × 10 ¹⁸ atoms / cm 3 (formerly ASTM), which consists of a mixed region of region [P _v ] and region [P _I ]. Even if the aggregate of point defects does not exist, an oxygen precipitation nucleus is fully expressed and the heat processing method of the silicon wafer which exhibits the IG effect by the heat processing of a device manufacturing process is provided.

A fourth object of the present invention is to provide a heat treatment method for a silicon wafer that does not require an oxygen donor killer treatment step.

A fifth object of the present invention is to provide a heat treatment method for a silicon wafer which has a minimum number of heat treatments in a silicon wafer state and exhibits a high IG effect by heat treatment at 950 ° C. or lower.

A sixth object of the present invention is to provide a silicon wafer exhibiting a high IG effect made by this method.

A seventh object of the present invention is to provide a silicon single crystal ingot that produces a silicon wafer exhibiting this high IG effect.

BRIEF DESCRIPTION OF THE DRAWINGS The figure which shows the relationship between V / G ratio, gap type defect defect, or interstitial silicon type defect defect concentration based on the theory of Voronkov of 1st Embodiment of this invention.

Fig. 2 is a characteristic diagram showing a change in pulling speed for determining a pulling speed profile of interest.

Fig. 3 is a schematic diagram of X-ray tomography showing a region where the gap type point defect of the reference ingot is predominant, the area where the lattice silicon type point defect is predominant and the perfect area according to the first embodiment of the present invention.

FIG. 4 is a diagram illustrating a situation in which OSF appears in a silicon wafer W ₁ corresponding to the position P ₁ in FIG. 3.

5 is a cross-sectional view cut axially past the axial center of the ingot corresponding to position P ₂ of FIG. 3.

FIG. 6 is a view showing a situation in which OSF appears in the center of the silicon wafer W ₂ corresponding to the position P ₂ of FIG. 3.

Fig. 7 shows the relationship between the V / G ratio and the interstitial point defect concentration or interstitial silicon type point defect concentration, based on the theory of the boronkov of the second and third embodiments of the present invention.

Fig. 8 is a schematic diagram of X-ray tomography showing a region where the gap type point defects prevail in the reference ingot, the area where the lattice silicon type point defects prevail, and the perfect area according to the second and third embodiments of the present invention.

9 is a plan view of a silicon wafer W ₃ corresponding to position P ₃ of FIG. 8.

Fig. 10 is a schematic diagram of an X-ray tomography showing a region where the gap type point defects of the reference ingot predominate, the area where the lattice silicon type point defects prevail, and the perfect area according to the fourth embodiment of the present invention.

FIG. 11 is a view showing a situation in which an OSF ring appears in a silicon wafer W ₁ corresponding to position P ₁ in FIG. 10.

12 is a cross-sectional view cut axially past the axis center of the ingot corresponding to position P ₂ of FIG. 10.

FIG. 13 is a view showing a situation in which OSF appears in the center of the silicon wafer W ₂ corresponding to the position P ₂ in FIG. 10.

FIG. 14 is a diagram showing a situation of Δ [Oi] in the wafer surface before and after the first heat treatment, in which the heat treatment in the semiconductor device process is performed for each silicon wafer of Example 1 and Comparative Example 1. FIG.

Fig. 15 is a diagram showing a situation of Δ [Oi] in the wafer surface before and after the second heat treatment in which the silicon wafers of Example 1 and Comparative Example 1 are subjected to heat treatment in a semiconductor device process.

FIG. 16A is an optical micrograph showing the presence or absence of haze after Fe contamination of the wafer W ₃ of Example 2 and dispersion of Fe in the bulk; FIG.

16B is an optical micrograph showing the presence or absence of haze after Cr contamination of the wafer W ₃ of Example 2 and the dispersion of Cr into bulk;

FIG. 16C is an optical micrograph showing the presence or absence of haze after Ni contamination of the wafer W ₃ of Example 2 and dispersion of Ni in the bulk; FIG.

16D is an optical micrograph showing the presence or absence of haze after Cu contamination of the wafer W ₃ of Example 2 and dispersion of Cu in the bulk;

FIG. 17A is an optical micrograph showing the presence or absence of haze after Fe contamination of wafer W ₃ of Comparative Example 2 and dispersion of Fe in bulk; FIG.

FIG. 17B is an optical micrograph showing the presence or absence of haze after Cr contamination of the wafer W ₃ of Comparative Example 2 and dispersion of Cr into bulk; FIG.

FIG. 17C is an optical micrograph showing the presence or absence of haze after Ni contamination of wafer W ₃ of Comparative Example 2 and dispersion of Ni into bulk; FIG.

FIG. 17D is an optical micrograph showing the presence or absence of haze after Cu contamination of wafer W ₃ of Comparative Example 2 and dispersion of Cu in bulk; FIG.

18 is a micrograph showing the state of oxygen precipitates (BMD) in the wafer after accelerated heating in Example 18. FIG.

The first aspect of the present invention is a back surface of a silicon wafer in which particles and intrusive potentials due to crystals do not occur in the wafer surface, and the oxygen concentration is 1.2 × 10 ¹⁸ atoms / cm 3 or less (old ASTM). Forming a polysilicon layer having a thickness of 0.1 to 1.6 μm by chemical vapor deposition at a temperature of 670 ° C. ± 30 ° C., and forming the silicon wafer with the polysilicon layer at a temperature of 1000 ° C. ± 30 ° C. under an oxygen atmosphere. A heat treatment method for a silicon wafer including the step of heat treatment for 5 hours and then heat treatment for 1 to 16 hours at a temperature of 1130 ° C ± 30 ° C.

When the silicon wafer in which the polysilicon layer is not formed is heat treated as described above, OSF appears in the center of the wafer.

In the second aspect of the present invention, particles and interstitial dislocations due to crystals do not occur in the wafer surface, and the oxygen concentration is 1.2 × 10 ¹⁸ atoms / cm 3 or less (old ASTM), and under oxygen atmosphere After annealing for 2 to 5 hours at a temperature of 1000 ° C. ± 30 ° C., and subsequently heat treating for 1 to 16 hours at a temperature of 1130 ° C. ± 30 ° C., a thickness of 0.1 to 1.6 μm on the back surface of the silicon wafer, in which an oxidation-induced lamination defect appears at the center of the wafer A silicon wafer with a polysilicon layer on which a polysilicon layer is formed.

The silicon wafers according to the first and second aspects of the present invention are wafers made by the CZ method under the condition that OSF appears in the center thereof, and the centers have a relatively large amount of oxygen precipitation nuclei, and in other parts, the oxygen precipitation nuclei. Rarely have There is no COP outside the center. When a polysilicon layer is formed on the back side of the silicon wafer, BMD is formed on the front side of the wafer during the CVD process. As a result, the deposition of oxygen is uniform on all the surfaces of the wafer, thereby exhibiting a uniform IG effect without variation between the center of the wafer and other portions.

In the third aspect of the present invention, the region where the interstitial silicon type defects predominantly exist in the silicon single crystal ingot is referred to as [I], and the region in which the interstitial type defects predominantly exist is referred to as [V], and the lattice The perfect region in which the aggregates of interstitial silicon-type defects and the aggregates of gap type defects do not exist is called [P], adjacent to the region [I], and belonging to the perfect region [P] to form an invasive dislocation. A region below the lowest interstitial silicon concentration is referred to as [P _I ], and a region below the gap concentration capable of forming COP or FPD adjacent to the region [V] and belonging to the perfect region [P] is [P _v]. ]

It is a method of heat-processing the silicon wafer in which the aggregate of the point defects cut out from the ingot which consists of said perfect region [P] does not exist.

This method is characterized by a silicon single crystal ingot with a mixed region of the region [P _v ] and region [P _I ] and having an oxygen concentration of 0.8 × 10 ¹⁸ to 1.4 × 10 ¹⁸ atoms / cm 3 (formerly ASTM). and,

The silicon wafer cut out from the ingot is kept at 600 to 850 ° C. for 30 to 90 minutes under nitrogen, argon, hydrogen, oxygen or a mixed gas atmosphere thereof.

A fourth aspect of the present invention is a silicon single crystal composed of a mixed region of the region [P _v ] and the region [P _I ] and having an oxygen concentration of 0.8 × 10 ¹⁸ to 1.4 × 10 ¹⁸ atoms / cm 3 (formerly ASTM). Raise the ingot,

The silicon wafer cut out from the ingot is held at 600 to 850 ° C. for 120 to 250 minutes in an atmosphere of nitrogen, argon, hydrogen, oxygen or a mixed gas thereof.

A fifth aspect of the present invention is a silicon single crystal composed of a mixed region of the region [P _v ] and the region [P _I ] and having an oxygen concentration of 0.8 × 10 ¹⁸ to 1.4 × 10 ¹⁸ atoms / cm 3 (formerly ASTM). Raise the ingot,

The silicon wafer cut out from the ingot was heated at a temperature rising rate of 10 to 150 ° C / sec from room temperature to 1150 to 1200 ° C under nitrogen, argon, hydrogen, oxygen or a mixed gas atmosphere thereof, and held at 1150 to 1200 ° C for 0 to 30 seconds. It is.

In the invention according to the third to fifth aspects of the present invention, when the oxygen concentration of the ingot is 0.8 × 10 ¹⁸ to 1.4 × 10 ¹⁸ atoms / cm 3 (formerly ASTM), the silicon wafer has a region [P _v ] and a region [ When the silicon wafer cut out from this ingot is heat-treated under the above conditions when the mixed region of P _I ] is formed, oxygen precipitated nuclei are expressed in the region [P _I ] where oxygen precipitated nuclei are not introduced during crystal growth, and at the same time, In [P _v ] in which the oxygen precipitation nuclei are introduced, the density of the oxygen precipitation nuclei increases. Therefore, when the wafer subjected to the heat treatment is subjected to heat treatment in a device manufacturing process of a semiconductor device manufacturer, the oxygen precipitate nuclei grow into BMD, and even a wafer including a mixed region of the region [P _v ] and the region [P _I ] is spread over the entire wafer surface. It has an IG effect.

According to a sixth aspect of the present invention, an oxygen-induced lamination defect occurs at 25% or more of the total area of the wafer when the silicon single crystal ingot is pulled from the silicon melt, and the thermal oxidation treatment causes oxygen that does not cause dislocations. Manufacturing a silicon wafer containing precipitates from 1 × 10 ⁵ to 3 × 10 ⁷ / cm 3 from the ingot, and rapidly heating the silicon wafer from room temperature to 650 to 950 ° C. at a temperature rising rate of 10 ° C./min or more, It is a heat treatment method of a silicon wafer including the process hold | maintained for 0.5 to 30 minutes.

In the method according to the sixth aspect of the present invention, a pre-heat treatment step for introducing oxygen precipitation nuclei into a conventional wafer and oxygen precipitation by using an ingot containing a BMD having a predetermined density in the OSF region present at the ratio when the wafer becomes a wafer The process of growing a nucleus into BMD is unnecessary, and a high IG effect is exerted by rapidly heating the wafer immediately after cutting out from the ingot and grinding and polishing.

[A] First embodiment of the present invention

The silicon wafers of the first to fourth embodiments of the present invention are obtained by pulling ingots from a silicon melt in a high-temperature band furnace by a CZ method at a predetermined pulling speed profile based on the theory of Boronkov. Then, this ingot is cut and produced.

In general, when a silicon single crystal ingot is pulled from a silicon melt in a hot zone furnace by the CZ method, agglomerates of point defects and point defects as defects in the silicon single crystal are three-dimensional defects. ) Occurs. There are two general types of point defects: gap point defects and interstitial silicon type point defects. Gap type defects are those in which one silicon atom deviates from one of its normal positions in the silicon crystal lattice. This gap becomes a gap type point defect. On the other hand, if atoms are found at positions other than the lattice points of the silicon crystals (inter-lattice positions), they become interstitial silicon type defects.

Point defects are generally formed at the contact surface between the silicon melt (melted silicon) and the ingot (solid silicon). However, by continuously pulling the ingot, the portion that was the contact surface begins to cool at the same time as the pull. During cooling, the interstitial agglomerates or interstitial silicon type defects merge with each other by diffusion, thereby forming vacancy agglomerates or interstitial agglomerates of interstitial silicon type defects. In other words, aggregates are three-dimensional structures that arise due to the merging of point defects.

In addition to the COP described above, the agglomerates of the gap type defects include defects called Laser Scattering Tomograph Defects (LSTD) or Flow Pattern Defects (FPD), and the agglomerates of interstitial silicon type defects include the defects described above L / D. FPD is a silicon wafer made by cutting an ingot without etching for 30 minutes by unstirring (Secco etching, K ₂ Cr ₂ O ₇ : 50% HF: pure water = 44 g: 2000 cc: 1000 cc: mixed by a mixed solution) It is the source of traces that show the unusual flow pattern that appears. LSTD is a cause of scattered light having a refractive index different from that of silicon when irradiated with infrared rays in a silicon single crystal.

Boronkov's theory is that in order to grow a high-purity ingot with a small number of defects, the pulling speed of the ingot is V (mm / min), and the temperature gradient of the contact surface of the ingot-silicon melt in a high temperature band structure is G (° C / mm). In this case, V / G (mm 2 / min · ° C.) is controlled. In this theory, as shown in Fig. 1, V / G is taken as the horizontal axis, and the gap type point defect concentration and the interstitial silicon type point defect concentration are set as the same longitudinal axis, and the relationship between V / G and the point defect concentration is shown schematically. In the description, the boundary between the gap region and the lattice silicon region is determined by V / G. More specifically, an ingot having a predominantly gap-type point defect concentration is formed at a V / G ratio above a critical point, while an ingot having a predominantly silicon-type point defect concentration between lattice is formed at a V / G ratio below a critical point.

The predetermined pulling rate profile of the first embodiment is such that the ratio (V / G) of the pulling rate to the temperature gradient prevents the occurrence of interstitial silicon type point defect agglomerates when the ingot is pulled from the silicon melt in the hot zone furnace. Above the first critical ratio (V / G) ₁ , below the second critical ratio (V / G) ₂ , which limits the interstitial point defect aggregates into the region where the interstitial point defects predominantly exist in the center of the ingot. Is determined to remain.

The profile of this pulling speed is determined based on the theory of the Voronkov by simulation by experimentally cutting the reference ingot axially, experimentally cutting the reference ingot with a wafer, or by combining these techniques. In other words, this determination is made by checking the axial pieces of the ingot and the cut wafer after the simulation and repeating the simulation again. Various kinds of pulling speeds are determined in a predetermined range for the simulation, and several reference ingots are grown. As shown in Fig. 2, the pulling speed profile for the simulation is adjusted from a high pulling speed a, such as 1.2 mm / min, to a low pulling speed c of 0.5 mm / min, which in turn leads to a high pulling speed d. Adjusted. The low pulling speed may be 0.4 mm / min or less, and the change in the pulling speeds b and d is preferably linear.

At different speeds, several reference ingots are cut in different axial directions. The optimal V / G is determined from the correlation of the axial slice, the identification of the wafer and the simulation result, and then the optimum pulling speed profile is determined, from which the ingot is produced. Actual pull rate profiles include, but are not limited to, the diameter of the target ingot, the particular hot band furnace used and the quality of the silicon melt, and the like, but not limited to this.

It can be seen that when the pulling speed is gradually lowered and the cross section of the ingot is drawn when the V / G is continuously lowered, it is shown in FIG. 3. In FIG. 3, [V] represents a region where the gap type point defects dominate in the ingot and agglomerates of the gap type point defects exist, and [I] indicates the aggregates of the lattice silicon type point defects and the interstitial silicon type point defects. Denotes a region in which P is present, and [P] denotes a perfect region in which the aggregate of gap type point defects and the aggregate of interstitial silicon type point defects do not exist.

Moreover, the aggregate of point defects, such as COP or L / D, can show the value from which a detection sensitivity and a detection lower limit differ by a detection method. Therefore, in this specification, the meaning of "agglomerates of point defects does not exist" means that the product of the observation area and the etching removal value is measured by an optical microscope after unstirred saeco etching of the mirror-finished silicon single crystal. When observed, the lower limit value (1 ×) was detected in the case where one defect was detected for each of the aggregates of the flow pattern (gap defect) and dislocation cluster (silicon type interfacial lattice) at an inspection volume of 1 × 10 ⁻³ cm 3. 10 ³ pieces / cm 3), the number of the caking defect aggregates is less than or equal to the detection lower limit.

3, the axial position P ₁ of the ingot, and the central region comprises a gap-type point defects exist dominantly. The position P ₂ comprises a region in which a small gap type point defect predominantly exists in the center compared to P ₁ . The position P ₄ comprises a central perfect region and a ring region in which interstitial silicon type defects dominate. Further, the positions P ₃ are all perfect regions because there are no gap type defects in the center and no lattice type silicon defects in the edge portion.

As is apparent from FIG. 3, the wafer W ₁ corresponding to the position P ₁ includes a region where the gap type point defect predominantly exists in the center. The wafer W ₂ corresponding to the position P ₂ includes a region where the gap type point defects predominantly exist in a small area in the center of the wafer W ₁ . Wafer W ₄ corresponding to position P ₄ includes a central perfect region and a ring in which interstitial silicon type defects predominantly exist. In addition, a wafer W ₃ corresponding to the position P ₃ is no gap-type point defects at the center, since there is also a silicon type point defects in the interstitial rim portion all perfect area.

Some of the areas in contact with the perfect areas of the areas where the gap type point defects predominantly exist are areas in which neither COP nor L / D occurs in the wafer surface. However, when the silicon wafer is heat-treated for 2 to 5 hours at a temperature of 1000 ° C. ± 30 ° C. under an oxygen atmosphere according to the conventional OSF appearance heat treatment, and subsequently heat-treated for 1 to 16 hours at a temperature range of 1130 ° C. ± 30 ° C., the OSF becomes Occurs. As shown in FIG. 4, in the wafer W ₁ , an OSF ring is generated near half of the wafer radius. The predominantly located gap-type point crystal surrounded by the OSF ring tends to exhibit COP. In contrast, in the wafer W ₂ , the OSF does not become ring-shaped, but only occurs in the center of the wafer. The silicon wafer used in the first embodiment is this wafer W ₂ . That is, the first embodiment of a silicon wafer W ₂ is produced to cut the ingot is grown at a pulling rate profile is determined as the OSF ring type, selected so that only the center appearance as shown in FIG. 6 is a plan view thereof. In this silicon wafer W ₂ , since OSF does not form a ring shape, there is no COP. There is no occurrence of an invasive potential.

In the silicon wafer of the first embodiment, the oxygen concentration in the wafer is also controlled. In the CZ method, the oxygen concentration in the wafer is controlled by changing the flow rate of argon supplied into the hot zone furnace, the rotational speed of the quartz crucible storing the silicon melt, the pressure in the hot zone furnace, and the like. The oxygen concentration inside the wafer is controlled to 1.2 × 10 ¹⁸ atoms / cm 3 or less (formerly ASTM). In order to achieve this oxygen concentration, for example, the flow rate of argon is controlled to be 80 to 150 liters / minute, the rotation speed of the quartz crucible for storing the silicon melt is 4 to 9 rpm, and the pressure in the high temperature zone furnace is 15 to 60 Torr. . The silicon wafer of the first embodiment has an oxygen concentration of 1.2 × 10 ¹⁸ atoms / cm 3 or less (formerly ASTM) in order to prevent excessive precipitation of oxygen precipitation nuclei.

On the surface of the silicon wafer cut out of the ingot pulled under the above conditions, a polysilicon layer was formed with a thickness of 0.1 to 1.6 mu m at a temperature of 670 ° C ± 30 ° C by, for example, SiH ₄ by CVD. If the thickness of the polysilicon layer is less than 0.1 μm, the effect of the polysilicon layer is inferior. If the thickness of the polysilicon layer is more than 1.6 μm, the productivity is lowered. Preferably it is 1.0-1.6 micrometers. Even before the polysilicon layer was formed, even if the oxygen concentration was uniform in the wafer surface, oxygen precipitation was likely to occur at the center of the wafer, and oxygen precipitation was not well performed at other portions. Thus, the oxygen precipitation situation in the wafer surface was formed by forming the polysilicon layer. Is homogenized.

Accordingly, when the silicon wafer with the polysilicon layer is thermally treated in the semiconductor device process, even if oxygen precipitate nuclei exist in the wafer, the nuclei do not grow, and the OSF does not occur even when the conventional OSF appearance heat treatment is performed. do.

[B] Second Embodiment of the Present Invention

In the second embodiment of the present invention, similarly to the first embodiment, the silicon ingot is pulled out of the silicon melt based on the theory of boronkop. As shown in Fig. 7, the predetermined pulling speed profile according to the second embodiment of the present invention shows that when the ingot is pulled from the silicon melt in the high temperature zone furnace, the ratio (V / G) of the pulling speed to the temperature gradient is between the lattice. A fourth threshold ratio ((V / G) ₃ ) or more, which prevents the occurrence of agglomerates of silicon type defects, wherein the fourth limiting the agglomerates of the gap type defects into a region where the gap type defects in the center of the ingot predominantly exist; It is determined to remain below the threshold ratio (V / G) ₄ . In Fig. 7, [I] denotes an area where interstitial silicon type defects are dominant and interstitial silicon type defects are present ((V / G) ₃ or less), and [V] denotes a gap type defect in an ingot. And a region in which agglomerates of interstitial point defects are present ((V / G) ₄ or more), and [P] indicates a perfect region ((V / G) in which agglomerates of interstitial point defects and agglomerates of interstitial silicon type point defects do not exist. ) ₃ to (V / G) ₄ ). In the region [V] adjacent to the region [P], there are regions [OSF] ((V / G) ₄ to (V / G) ₅ ) which form an OSF nucleus.

The perfect region [P] is further classified into a region [P _I ] and a region [P _v ]. [P _I ] is the area from the above (V / G) ₃ to the critical point, and [Pv] is the area from the critical point to the above (V / G) ₄ . That is, [P _I ] is a region adjacent to the region [I] and having a lattice silicon type defect defect concentration below the lowest interstitial silicon type defect defect concentration capable of forming an invasive potential, and [Pv] is an area [ It is a region adjacent to V] and having a gap type defect defect concentration below the lowest gap type defect defect concentration capable of forming OSF.

Drawing the cross sectional view of the ingot when the pulling speed is gradually lowered and the V / G is continuously lowered, the fact shown in FIG. 8 is understood. Fig. 8 shows the region in which the interstitial point defects predominantly exist in the ingot [V], the region in which the interstitial silicon point defects predominantly exist [I], and the aggregates of the interstitial point defects and the interstitial silicon type point defects. Perfect regions where no aggregates are present are indicated as [P], respectively. As described above, the perfect area [P] is further classified into an area [P _I ] and an area [P _v ]. Region [Pv] is a region in which interstitial point defects do not become aggregated in the perfect region [P], and region [P _I ] is a region in which lattice interstitial silicon defects do not form aggregates in the perfect region [P]. .

As shown in Figure 8, the axial position of the ingot P ₁ includes the area which is present in the predominant gap-type point defects at the center. The position P ₄ comprises a central perfect region and a ring region in which interstitial silicon type defects dominate. In position P ₃ is a second no aggregates of the gap-type point defects at the center according to the second embodiment, since there is also the aggregate of silicon type point defects in the interstitial rims of both the perfect area.

As can be seen in FIG. 8, the wafer W ₁ corresponding to the position P ₁ includes a region where a gap type point defect predominantly exists in the center. Wafer W ₄ corresponding to position P ₄ includes a central perfect region and a ring in which interstitial silicon type defects predominantly exist. In addition, the wafer W ₃ corresponding to the position P ₃ is the wafer according to the second embodiment, and there are no aggregates of interstitial point defects in the center, and there are no aggregates of interstitial silicon type defects in the edges, so all of them are perfect regions. _V ] and the region [P _I ] are mixed. Some regions ((V / G) ₄ to (V / G) _{5 in} FIG. 7) in contact with the perfect region of the region where the gap type defect defect predominantly exist are regions in which neither COP nor LD occurs in the wafer surface. . However, the silicon wafer W ₁ is heat-treated for 2 to 5 hours at a temperature of 1000 ° C. ± 30 ° C. under an oxygen atmosphere according to the conventional OSF appearance heat treatment, and then heat-treated for 1 to 16 hours at a temperature of 1130 ° C. ± 30 ° C. OSF occurs. As illustrated in FIG. 4 described in the first embodiment, in the wafer W ₁ , an OSF ring is generated in the vicinity of half the wafer radius. The region where the gap type point defect surrounded by this OSF ring predominantly exists tends to exhibit COP.

The silicon wafer of the second embodiment is the above-described wafer W ₃ , the plan view of which is shown in FIG. 9. Since the wafer W ₃ generates oxygen precipitation nuclei having a desired density or higher on the wafer W ₃ by the heat treatment of the second embodiment, the oxygen concentration is 0.8 × 10 ¹⁸ to 1.4 × 10 ¹⁸ atoms / cm 3 (old ASTM). It is necessary.

Next, the heat treatment of the silicon wafer W ₃ will be described. This heat treatment is performed by maintaining the wafer W ₃ for 30 to 90 minutes at 600 to 850 ° C. or 120 to 250 minutes at 600 to 850 ° C. under nitrogen, argon, hydrogen, oxygen or a mixed gas atmosphere thereof. The heating is preferably performed by introducing the wafer into a heat treatment furnace maintained at 600 to 850 ° C. at a rate of 50 to 100 ° C./min. If the holding temperature is less than 600 ° C. or the holding time is less than 30 minutes, the oxygen precipitation nuclei are not sufficiently increased, and the BMD density necessary for exerting the IG effect is not obtained when heat treatment is performed in the device manufacturing process of the semiconductor device manufacturer. When the holding temperature exceeds 850 ° C., the density of oxygen precipitation nuclei in the region [P _I ] is low, so that the BMD density necessary for exhibiting the IG effect is not obtained when the heat treatment is performed in the device manufacturing process. In the case where the holding temperature is 600 to 850 ° C. and the holding time is more than 90 minutes and less than 120 minutes, the excessive amount of interstitial lattice defects due to the formation of the oxygen cutting nuclei causes the suppression of the precipitation amount of the oxygen precipitation nuclei. Productivity will fall when holding time is 250 minutes or more.

These heat treatment conditions are included in heat treatment conditions (holding temperature 650 ° C. ± 30 ° C., holding time 5 to 300 minutes) when the polysilicon layer is formed on the back surface of the wafer by CVD. Therefore, when the polysilicon layer is formed on the back surface of the wafer by the CVD method according to the heat treatment conditions, the object of the second embodiment of the present invention can be achieved by forming the polysilicon layer. The thickness of the polysilicon layer at this time is 0.1-2.0 micrometers. By forming the polysilicon layer on the back side of the wafer, the oxygen precipitates are further increased in the vicinity of the back side of the wafer in contact with the polysilicon layer. The wafer may be left in the polysilicon layer as it is, or the polysilicon layer may be an acid etchant obtained by diluting a mixed acid of hydrofluoric acid and nitric acid with water or acetic acid, or an alkali etchant diluting KOH or NaOH in water. May be removed.

In addition, by performing the heat treatment, the oxygen donor killer treatment in the wafer process is unnecessary.

[C] Third Embodiment of the Invention

In the third embodiment of the present invention, similarly to the first embodiment, the silicon ingot is pulled from the silicon melt based on the theory of the boron cope. The predetermined pulling speed profile of the third embodiment of the present invention is the same as that of the second embodiment.

The silicon wafer of the third embodiment is a wafer W ₃ shown in Figs. The wafer W ₃ has an oxygen concentration of 0.8 × 10 ¹⁸ to 1.4 × 10 ¹⁸ atoms / cm 3 (formerly ASTM) in order to generate an oxygen dilution nucleus having a desired density or higher on the wafer W ₃ by the heat treatment of the third embodiment. It is necessary to be.

The heat treatment of the silicon wafer W ₃ heats the wafer W ₃ in a nitrogen, argon, hydrogen, oxygen or mixed gas atmosphere at a temperature rising rate of 10 to 150 ° C./sec from room temperature to 1150 to 1200 ° C., at 1150 to 1200 ° C. By holding for 0 to 30 seconds. That is, the heat treatment of the third embodiment is rapid heating. Here, the holding time for 0 seconds means that only the temperature is raised but not maintained. The heat is introduced into a heat treatment furnace maintained at room temperature, or in the case of continuous operation, in the heat treatment furnace which is several hundreds of degrees in excess heat, and a wafer of 10 to 150 deg. C / sec, preferably 50 to 100 deg. C / sec. It heats up to 1150-1200 degreeC by speed. Oxygen precipitation nuclei increase when the temperature increase rate is less than 10 ° C., but the treatment ability is poor, which is not practical. Moreover, if it is less than 1150 degreeC, oxygen precipitation nuclei will not fully increase and the BMD density required for exposing IG effect will not be obtained when heat processing in the device manufacturing process of a semiconductor device manufacturer is carried out. If the holding temperature exceeds 1200 ° C. or the holding time exceeds 30 seconds, a slip occurs or the productivity of the heat treatment decreases. Moreover, when a temperature increase rate exceeds 150 degree-C / sec, a problem arises that a slip generate | occur | produces by self-weight stress or the deviation of in-plane temperature distribution.

Further, the heat treatment eliminates the need for the oxygen donor killer treatment in the wafer process.

[D] Fourth Embodiment of the Invention

In the fourth embodiment of the present invention, similarly to the first embodiment, the silicon ingot is pulled out of the silicon melt based on the theory of boronkop. The predetermined pulling speed profile of the fourth embodiment of the present invention is the same as that of the first embodiment. In order to better describe 4th embodiment, FIG. 10 corresponding to FIG. 3 is shown. Each code in FIG. 10 corresponds to each code in FIG. A feature of the fourth embodiment is that the wafer W ₂ corresponding to the position P ₂ includes an area where the gap type point defect predominantly exists at an area (50%) of half the total area of the wafer as compared to the wafer W ₁ . .

Some of the areas in contact with the perfect areas of the areas where the gap point defects predominantly exist are areas in which neither COP nor LD occurs in the wafer surface. However, according to the conventional OSF appearance heat treatment method, the silicon wafer is heat-treated at an temperature of 1000 ° C. ± 30 ° C. for 2 to 5 hours, and subsequently heat-treated at 1130 ° C. ± 30 ° C. for 1 to 16 hours. Occurs. As shown in FIG. 11, in the wafer W ₁ , an OSF ring is generated near the edge of the wafer. The region where the gap type point defect surrounded by this OSF ring predominantly exists tends to exhibit COP. On the other hand, in the wafer W ₂ , the OSF does not have a ring shape, but only occurs in a disk shape at the center of the wafer. The silicon wafer used in the fourth embodiment is this wafer W ₂ , and OSF is generated in 25% or more of the total wafer area. If the OSF is less than 25% of the total wafer area, the generation area of the BMD is narrow and the IG effect is not sufficiently exhibited. Preferably it is 50 to 80%.

Fourth Embodiment As shown in the silicon wafer W ₂ is 12, and is cut making an ingot grown at a pulling rate profile as determined by the OSF selected to appear in the center, rather than a ring shape. Fig. 13 is a plan view thereof. In this silicon wafer W ₂ , since the OSF does not form a ring shape, there is no COP. Also, there is no occurrence of LD (intercalation potential). The ingot to produce a silicon wafer W ₂ of the present invention includes the BMD is not accompanied by a potential generated at a rate of 1 × 10 ⁵ to 3 × 10 ⁷ gae / ㎠. For this reason, as disclosed in Japanese Patent Laid-Open No. 8-45945, it is not necessary to maintain the wafer state at a relatively low temperature of 500 to 800 ° C. for 0.5 to 20 hours before rapid heating and introduce oxygen precipitate nuclei into the wafer at high density. When the BMD density is less than 1 × 10 ⁵ / cm 2, sufficient IG effect is hardly obtained when rapid heating is performed in a wafer state. 3 × 10 ⁷ cells / cm 2 is the maximum BMD density that can occur in the OSF region.

As for the heating method of 4th Embodiment, the method of quickly putting the silicon wafer of room temperature containing BMD which does not involve dislocation generation in the said ratio in the furnace heated at the temperature of 650-950 degreeC is preferable. In addition, a silicon wafer at room temperature containing BMDs with no potential generation in the above ratio is placed in a high-speed heating furnace using a lamp capable of generating high heat, the lamp is turned on to start heating, and rapidly heated to a temperature of 650 to 950 ° C. It is also possible to use a method. That is, the heat treatment of the fourth embodiment is also rapid heating. Rapid heating in 4th Embodiment means heat processing at the temperature increase rate of 10 degreeC / min or more, Preferably it is 30 degreeC / min or more. In the case of rapid heating by lamp light irradiation, since the wafer can be heated uniformly, there is an advantage in that the wafer is more difficult to be bent as compared with the case where the wafer is heated in advance. If the final temperature reached by rapid heating is less than 650 DEG C, the disappearance of BMD in the vicinity of the wafer surface is insufficient, and DZ cannot be sufficiently secured. If the temperature exceeds 950 ° C, dislocations are generated before the BMD near the wafer surface disappears, so that DZ cannot be sufficiently secured. Preferably it is 800-900 degreeC. If the holding time is less than 0.5 minutes, the time for reducing the BMD on the wafer surface is too short, and the disappearance of the BMD on the wafer surface is insufficient, so that DZ cannot be sufficiently secured. Moreover, if it exceeds 30 minutes, DZ of thickness more than necessary will be obtained, and it will adversely affect productivity. For this reason, the holding time is set at 0.5 to 30 minutes. Preferably it is 10 to 30 minutes. Rapid heating takes place in a nitrogen atmosphere, in an oxygen atmosphere or in the atmosphere. It is preferably carried out in a nitrogen atmosphere.

After the rapid heating, when the silicon wafer is left to cool to room temperature and cooled, DZ is formed on the surface of the wafer over a depth of 1 to 100 μm, and the BMD density of the portion deeper than this DZ is 1 × 10 ⁵ to 3 × 10 ⁷ / An IG wafer of cm 2 is obtained.

Next, the Example of this invention is described with a comparative example.

<Example 1>

The ingot was pulled up so that the area corresponding to the position P ₂ shown in FIG. 3 was grown over the entire length of the ingot. At this time, in order to suppress the oxygen concentration in the ingot, the flow rate of the argon was about 110 liters / minute, the rotation speed of the quartz crucible storing the silicon melt was maintained at about 5 to 10 rpm, and the pressure in the hot zone furnace was about 60 Torr. In this way, the silicon wafers cut from the raised ingots are wrapped, subjected to chamfer processing, and then the surface of the wafer is removed by chemical etching, and SiH ₄ is used on the back side of the wafer at 680 ° C. for 1.5 A polysilicon layer was formed to a thickness of 탆. Then, the silicon wafer of 8 inches in diameter and 725 micrometers in thickness was prepared by mirror-polishing.

Comparative Example 1

The same silicon wafer as in Example 1 was referred to as Comparative Example 1 except that no polysilicon layer was formed.

<Comparative Evaluation 1>

The silicon wafer of Example 1 and the silicon wafer of Comparative Example 1 were subjected to a first heat treatment in accordance with the heat treatment in a semiconductor device process. That is, the wafer was heat-treated at 800 ° C. for 4 hours in an oxygen atmosphere, and then heat-treated at 1000 ° C. for 16 hours. Oxygen concentration of the wafer surface from the center of the wafer to the edge portion of Example 1 and Comparative Example 1 was measured by Fuier transform infrared spectroscopy (FT-IR). Δ [Oi], which is the oxygen concentration difference before and after the heat treatment, is shown in FIG. 14.

The other silicon wafer of Example 1 and the other silicon wafer of Comparative Example 1 were subjected to a second heat treatment, which is modeled after the heat treatment in the semiconductor device process. That is, such a wafer was heat-treated at 700 ° C. for 8 hours in an oxygen atmosphere, and then heat-treated at 1000 ° C. for 12 hours. Oxygen concentrations of the wafer surface from the wafer center to the edge portion of these Example 1 and Comparative Example 1 were measured by FT-IR. Δ [Oi], which is the oxygen oxygen concentration difference before and after the heat treatment, is shown in FIG. 15.

As shown in FIG. 14 and FIG. 15, the oxygen concentration difference Δ [Oi] before and after the heat treatment of the silicon wafer of Comparative Example 1 varied greatly from the center of the wafer to 40 mm, whereas the heat treatment of the silicon wafer of Example 1 The oxygen concentration difference [Delta] [Oi] before and after decreased only gently between about 90 mm from the center of the wafer and was uniform in the wafer surface.

Further, another silicon wafer of Example 1 and another silicon wafer of Comparative Example 1 were heat-treated at a temperature of 1000 ° C. for 4 hours, and then heat-treated (thermal oxidation treatment) at 1130 ° C. for 3 hours to visually OSF. It was investigated whether or not was shown. As a result, a whitish OSF appeared in the center of the wafer of the silicon wafer of Comparative Example 1. In contrast, in the silicon wafer of Example 1, no OSF appeared in the wafer surface.

<Example 2>

A silicon single crystal pulling apparatus was used to pull up a p-type silicon ingot of 8 inches in diameter doped with boron (B). The ingot had a length of 1200 mm in diameter, a diameter direction of (100), a resistivity of about 10 Ωcm, and an oxygen concentration of 1.0 × 10 ¹⁸ atoms / cm 3 (old ASTM). Two ingots were grown under the same conditions while continuously decreasing V / G from 0.24 mm 2 / min ° C to 0.18 mm 2 / min ° C. One ingot cuts the center of the ingot in the pulling direction as shown in FIG. 8, examines the position of each region, and cuts the silicon wafer W ₃ at the position corresponding to P ₃ of FIG. 8 from the other to the specimen. I made it. In this example, the specimen wafer is a wafer W ₃ shown in FIG. 9 having a region [P _V ] at its center, a region [P _I ] at its periphery, and [P _V ] at its periphery.

The wafer W ₃ cut out from the ingot and subjected to mirror polishing was subjected to a heat treatment for 30 minutes at 650 ° C. under a nitrogen atmosphere.

<Example 3>

The heat treatment was carried out in the same manner as in Example 2 except that the heat treatment temperature of the wafer W ₃ cut out from the same ingot as in Example 2 was 650 ° C and the holding time was 90 minutes.

<Example 4>

The heat treatment was carried out in the same manner as in Example 2 except that the heat treatment temperature of the wafer W ₃ cut out from the same ingot as in Example 2 was 650 ° C and the holding time was 120 minutes.

Example 5

The heat treatment was carried out in the same manner as in Example 2 except that the heat treatment temperature of the wafer W ₃ cut out from the same ingot as in Example 2 was 750 ° C and the holding time was 60 minutes.

<Example 6>

The heat treatment was carried out in the same manner as in Example 2 except that the heat treatment temperature of the wafer W ₃ cut out from the same ingot as in Example 2 was 750 ° C and the holding time was 90 minutes.

<Example 7>

The heat treatment was carried out in the same manner as in Example 2 except that the heat treatment temperature of the wafer W ₃ cut out from the same ingot as in Example 2 was 850 ° C and the holding time was 30 minutes.

<Example 8>

The heat treatment was carried out in the same manner as in Example 2 except that the heat treatment temperature of the wafer W ₃ cut out from the same ingot as in Example 2 was 850 ° C and the holding time was 120 minutes.

Comparative Example 2

The heat treatment of the wafer W ₃ cut out from the same ingot as in Example 2 and mirror-polished was not performed.

Comparative Example 3

The heat treatment was performed in the same manner as in Example 2 except that the heat treatment temperature of the wafer W ₃ cut out from the same ingot as in Example 2 was 650 ° C and the holding time was 100 minutes.

<Comparative Example 4>

The heat treatment was carried out in the same manner as in Example 2 except that the heat treatment temperature of the wafer W ₃ cut out from the same ingot as in Example 2 was 750 ° C and the holding time was 20 minutes.

Comparative Example 5

The heat treatment was carried out in the same manner as in Example 2 except that the heat treatment temperature of the wafer W ₃ cut out from the same ingot as in Example 2 was 800 ° C and the holding time was 100 minutes.

<Comparative Evaluation 2>

Four wafers W ₃ of Examples 2 to 8 and Comparative Examples 2 to 5 were prepared, and four kinds of solutions containing metal elements of Fe, Cr, Ni, and Cu, respectively, on the surfaces of these four wafers W ₃ . By dropping and spin-coating respectively, the four wafer front surfaces were forcibly contaminated with Fe, Cr, Ni, and Cu, respectively. All the contaminated wafers W ₃ were heat-treated at 900 ° C. for 2 hours, and then heat-treated at 1000 ° C. for 0.5 hours and again at 800 ° C. for 1.5 hours to disperse each metal element in the bulk of the wafer. The heat treatment after this contamination corresponds to the heat treatment of the device manufacturing process of the semiconductor device maker.

In order to confirm the IG effect of the contaminated metal, these wafers were etched only about 2 μm in thickness with a sachet etching solution, and the presence or absence of haze was observed under the light collecting lamp. The situation with or without the haze of Examples 2-8 and Comparative Examples 2-5 was shown in Table 1. Moreover, the optical micrograph of Example 2 was shown to FIG. 16A-FIG. 16B, and the optical micrograph of the comparative example 2 was shown to FIG. 17A-FIG. 17B, respectively. 16A and 17A show a quarter of the wafers of Fe-contaminated Example 2 and Comparative Example 2, respectively. Likewise, FIGS. 16B and 17B show Cr contamination, FIGS. 16C and 17C show Ni contamination, and FIGS. 16D and 17D show one-fourth the wafers of Example 2 and Comparative Example 2, respectively, which are Cu-contaminated.

Heat treatment condition Haze presence Temperature (℃) Time (min) Area (P _V ) Area P _I Example 2 650 30 none none Example 3 650 90 none none Example 4 650 210 none none Example 5 750 60 none none Example 6 750 90 none none Example 7 850 30 none none Example 8 850 120 none none Comparative Example 2 - - none has exist Comparative Example 3 650 100 none has exist Comparative Example 4 750 20 none has exist Comparative Example 5 800 100 none has exist

As can be seen from Table 1, FIGS. 16A to 16D, and FIGS. 17A to 17D, haze appeared only in the wafer region [P _I ] of Comparative Examples 2 to 5. FIG. It is considered that this is because under the heat treatment conditions of Comparative Examples 2 to 5, the oxygen precipitation nuclei density of the wafer is low, so that the IG effect is not exerted by the heat treatment after contamination. On the other hand, it was found that the wafers of Examples 2 to 8 had no haze and high oxygen precipitation nuclei density over the entire areas [P _V ] and [P _I ], thereby exhibiting the IG effect.

Example 9

A silicon single crystal pulling apparatus was used to pull up a p-type silicon ingot of 8 inches in diameter doped with boron (B). The ingot had a length of 1200 mm in diameter, a diameter direction of (100), a resistivity of about 10 Ωcm, and an oxygen concentration of 1.0 × 10 ¹⁸ atoms / cm 3 (old ASTM). Two ingots were grown under the same conditions while continuously decreasing V / G from 0.24 mm 2 / min ° C to 0.18 mm 2 / min ° C. As shown in FIG. 8, one of the ingots was cut in the ingot in the pulling direction to examine the position of each region, and the silicon wafer W ₃ at the position corresponding to P ₃ of FIG. 8 was cut out from the other one as a sample. . In this example, the wafer serving as the sample is a wafer W ₃ shown in FIG. 9 having a region [P _V ] at the center, a region [P _I ] at the periphery thereof, and [P _V ] at the periphery thereof.

By heating the wafer W ₃ that is cut from the ingot surface mirror polished to about 50 ℃ / sec rate of temperature rise up to 1150 ℃ at room temperature in a nitrogen atmosphere, was subjected to heat treatment without maintaining at 1150 ℃.

<Example 10>

The heat treatment was carried out at 1150 ° C. in the same manner as in Example 9 except that the holding time of the heat treatment time of the wafer W ₃ cut out from the ingot same as that of Example 9 and mirror-polished was 5 seconds.

<Example 11>

The heat treatment was carried out at 1150 ° C. in the same manner as in Example 9 except that the holding time of the heat treatment time of the wafer W ₃ cut out from the ingot same as that of Example 9 and mirror-polished was 30 seconds.

<Example 12>

The heat treatment was carried out in the same manner as in Example 9, except that the heat treatment temperature of the wafer W ₃ cut out from the same ingot as in Example 9 was changed to 1200 ° C.

Example 13

The heat treatment was performed in the same manner as in Example 9 except that the heat treatment time of the wafer W ₃ cut out from the same ingot as in Example 9 and the mirror surface polishing was 1200 ° C. and the holding time was 5 seconds.

<Example 14>

The heat treatment was performed in the same manner as in Example 9 except that the heat treatment temperature of the wafer W ₃ cut out from the ingot same as that of Example 9 was 1200 ° C and the holding time was 30 seconds.

Comparative Example 6

The heat treatment of the wafer W ₃ which was cut out from the same ingot as in Example 9 and mirror-polished was not performed.

Comparative Example 7

The heat treatment was performed in the same manner as in Example 9 except that the heat treatment temperature of the wafer W ₃ cut out from the same ingot as in Example 9 was 1100 ° C and the holding time was 5 seconds.

<Comparative Example 8>

The heat treatment was performed in the same manner as in Example 9 except that the heat treatment temperature of the wafer W ₃ cut out from the ingot same as that of Example 9 was 1100 ° C and the holding time was 30 seconds.

Comparative Example 9

The heat treatment was performed in the same manner as in Example 9 except that the heat treatment temperature of the wafer W ₃ cut out from the ingot same as that of Example 9 was 1100 ° C and the holding time was 60 seconds.

Comparative Example 10

The heat treatment was performed at 1150 ° C. in the same manner as in Example 9 except that the heat treatment time of the wafer W ₃ cut out from the same ingot as in Example 9 and mirror-polished was 60 seconds.

Comparative Example 11

The heat treatment was performed in the same manner as in Example 9 except that the heat treatment temperature of the wafer W ₃ cut out from the same ingot as in Example 9 and the mirror surface polished was 1200 ° C and the holding time was 60 seconds.

Comparative Example 12

The heat treatment was performed in the same manner as in Example 9 except that the heat treatment temperature of the wafer W ₃ cut out from the same ingot as in Example 9 was 1250 ° C and the holding time was 5 seconds.

Comparative Example 13

The heat treatment was performed in the same manner as in Example 9 except that the heat treatment temperature of the wafer W ₃ cut out from the same ingot as in Example 9 was 1250 ° C and the holding time was 30 seconds.

<Comparative Evaluation 3>

The wafers of Examples 9 to 14 and Comparative Examples 6 to 13 are each held at 800 ° C. under an oxygen atmosphere for 4 hours, and then held at 1000 ° C. for 16 hours in an oxygen atmosphere. Heat treatment was performed. After the heat treatment, each wafer was cleaved, and the wafer surface was again selectively etched with a bright etching solution and corresponded to an area [P _v ] and an area [P ₁ ] at a depth of 350 μm from the wafer surface by observation with an optical microscope. The BMD area density and the presence or absence of the slip of the part to be measured were measured. These results are shown in Table 2.

Heat treatment condition BMD area density (/ ㎠) Whether slip Temperature (℃) Time in seconds Area (P _V ) Area P _I Example 9 1150 0 3.6 x 10⁴ 3.5 x 10⁴ none Example 10 1150 5 2.4 x 10⁴ 2.3 x 10⁴ none Example 11 1150 30 1.2 x 10⁴ 1.0 x 10⁴ none Example 12 1200 0 532.0 x 10⁴ 411.0 x 10⁴ none Example 13 1200 5 412.0 x 10⁴ 356.0 x 10⁴ none Example 14 1200 30 37.7 x 10⁴ 77.3 x 10⁴ none Comparative Example 6 Untreated 40.0 x 10⁴ 0.1 x 10⁴ none Comparative Example 7 1100 5 1.0 x 10⁴ 0.1 x 10⁴ none Comparative Example 8 1100 30 2.2 x 10⁴ 0.1 x 10⁴ none Comparative Example 9 1100 60 2.2 x 10⁴ 0.1 x 10⁴ none Comparative Example 10 1150 60 0.5 x 10⁴ 0.1 x 10⁴ has exist Comparative Example 11 1200 60 125.0 x 10⁴ 0.5 x 10⁴ has exist Comparative Example 12 1250 5 73.5 x 10⁴ 68.5 x 10⁴ has exist Comparative Example 13 1250 30 65.4 x 10⁴ 58.8 x 10⁴ has exist

As shown in Table 2, in the portion corresponding to the wafer region [P _I ] in Comparative Examples 6 to 11, the BMD area density (1 × 10 ⁴ pieces / cm 2, preferably 2) indicates that the BMD area density exhibits the IG effect. X10 ⁴ pieces / cm 2). In Comparative Examples 12 and 13, although the BMD area density of the portions corresponding to the regions [P _v ] and the regions [P ₁ ] exceeded 2 × 10 ⁴ pieces / cm 2, slip occurred. In addition, the wafers of Comparative Examples 10 and 11 also exhibited slip. In contrast, in the wafers of Examples 9, 10 and 12 to 14, the BMD area density of the portions corresponding to the regions [P _v ] and the regions [P ₁ ] exceeded 2 × 10 ⁴ / cm 2, and no slip occurred. . In particular, higher BMD area densities were obtained with the wafers of Examples 12-14. Further, in the wafer of Example 11, the BMD area density was lower than 2 × 10 ⁴ / cm 2, but the deposition distribution in the wafer surface was uniform.

<Example 15>

The V / G shown in FIG. 1 is greater than or equal to the threshold point so that OSF is generated at 25% of the total area of the wafer when heat-treated at 1000 ° C. in an oxygen atmosphere for 2 hours in a wafer state, and subsequently heat-treated at 12 ° C. for 12 hours. ) In the region of ₁ or more (V / G) ₂ or less, the silicon single crystal ingot was pulled up from the silicon melt. This ingot corresponds to the position P ₂ whose total length is shown in FIG. The silicon wafer sliced in the ingot which was raised was wrapped, the chamfering process was performed, and the impact of the wafer surface was removed by chemical etching treatment to obtain a mirror surface wafer.

This mirror surface wafer was heated up from room temperature to 850 degreeC at the temperature increase rate of 30 degree-C / min, hold | maintained for 5 minutes, and cooled to room temperature.

<Example 16>

A wafer processed in the same manner as in Example 15 was heated at 850 ° C. for 5 minutes at the same heating rate as in Example 15, except that the ingot was raised to generate OSF in 50% of the total wafer area.

<Example 17>

After raising the ingot so that OSF was generated in 80% of the total wafer area, the wafer processed in the same manner as in Example 15 was heated at 850 ° C. for 0.5 minutes at the same heating rate as in Example 15.

Example 18

After raising the ingot so that OSF was generated in 80% of the total wafer area, the wafer processed in the same manner as in Example 15 was heated at 850 ° C. for 5 minutes at the same heating rate as in Example 15.

Example 19

After raising the ingot so that OSF was generated in 80% of the total wafer area, the wafer processed in the same manner as in Example 15 was heated at 850 ° C. for 10 minutes at the same heating rate as in Example 15.

Example 20

After raising the ingot so that OSF was generated in 80% of the total wafer area, the wafer processed in the same manner as in Example 15 was heated at 850 ° C. for 20 minutes at the same heating rate as in Example 15.

Example 21

After raising the ingot so that OSF was generated in 80% of the total wafer area, the wafer processed in the same manner as in Example 15 was heated at 850 ° C. for 30 minutes at the same heating rate as in Example 15.

<Example 22>

After raising the ingot so that OSF was generated in 80% of the total wafer area, the wafer processed in the same manner as in Example 15 was heated at 700 ° C. for 5 minutes at the same heating rate as in Example 15.

<Example 23>

After raising the ingot so that OSF was generated in 80% of the total wafer area, the wafer processed in the same manner as in Example 15 was heated at 800 ° C. for 5 minutes at the same heating rate as in Example 15.

<Example 24>

After raising the ingot so that OSF was generated in 80% of the total wafer area, the wafer processed in the same manner as in Example 15 was heated at 950 ° C. for 5 minutes at the same heating rate as in Example 15.

Comparative Example 14

After raising the ingot so that OSF was generated in 15% of the total wafer area, the wafer processed in the same manner as in Example 15 was heated at 850 ° C. for 5 minutes at the same heating rate as in Example 15.

Comparative Example 15

After raising the ingot so that OSF was generated in 80% of the total wafer area, the wafer processed in the same manner as in Example 15 was heated at 640 ° C. for 5 minutes at the same heating rate as in Example 15.

Comparative Example 16

After raising the ingot so that OSF was generated in 80% of the total wafer area, the wafer processed in the same manner as in Example 15 was heated at 1000 ° C. for 5 minutes at the same heating rate as in Example 15.

Comparative Example 17

After raising the ingot so that OSF was generated in 80% of the total wafer area, the wafer processed in the same manner as in Example 15 was heated at 850 ° C. for 40 minutes at the same heating rate as in Example 15.

<Comparative Evaluation 4>

Each of the silicon wafers of Examples 15 to 24 and Comparative Examples 14 to 17 was cleaved, and the wafer surface was then selectively etched with a bright etching solution, and observed by an optical microscope at a width of DZ and a depth of 250 μm at the wafer surface. The BMD density of was measured. These results are shown in Table 3. Moreover, the microscope picture which expanded 50,000 times the BMD in the wafer after the rapid heating of Example 18 was shown in FIG.

% Of total immunity in OSF sector IG heat treatment condition BMD density (x10 ⁶ / cm 3) Width of DZ (μm) Temperature (℃) Time (min) Example 15 25 850 5 2.6 40 Example 16 50 850 5 3.4 40 Example 17 80 850 0.5 10.0 15 Example 18 80 850 5 10.0 35 Example 19 80 850 10 11.0 45 Example 20 80 850 20 10.0 65 Example 21 80 850 30 12.0 85 Example 22 80 700 5 23.0 20 Example 23 80 800 5 22.0 35 Example 24 80 950 5 24.0 55 Comparative Example 14 15 850 5 Less than 1.0 More than 100 Comparative Example 15 80 640 5 20.0 0 Comparative Example 16 80 1000 5 5.0 More than 100 Comparative Example 17 80 850 40 12.0 More than 100

As shown in Table 3, in Comparative Example 14 after the IG heat treatment, the OSF region was so small as 15% that the BMD density did not become 10 ⁶ / cm 3, which shows the IG effect. In Comparative Example 15, DZ could not be formed on the wafer surface because the heat treatment temperature was too low at 640 ° C. In Comparative Example 16, since the heat treatment temperature was too high at 1000 ° C, a wider DZ was formed than necessary. In Comparative Example 17, since the heat treatment time was too long (40 minutes), too wide DZ was formed.

In contrast, the silicon wafers of Examples 15 to 24 exhibited a band of 10 ⁶ to 10 ⁷ / cm 3, in which the BMD density exhibits the IG effect. In particular, in Examples 17 to 22 having an OSF area of 80%, the BMD density was in the range of 10 ⁷ / cm 3, among which Examples 19 to 21 having a heat treatment time of 10 to 30 minutes and Examples 24 to 45 in a heat treatment temperature of 950 ° C. A wide DZ of 85 μm was obtained.

Moreover, the micrograph of FIG. 18 showed that BMD which exists in the wafer after rapid heating process is accompanied by electric potential.

In the present invention, the heat treatment method of the silicon wafer has no OSF and COP even after heat treatment to generate OSF, and evenly precipitates oxygen on all sides of the wafer, thus providing a uniform gettering effect without deviation between the wafer edge and the center of the wafer. Exert.

Claims (12)

Particles and interstitial dislocations due to crystals do not occur in the wafer surface, and the oxygen concentration is 1.2 × 10 ¹⁸ atoms / cm 3 or less (old ASTM), and at an oxygen atmosphere of 1000 ° C. ± 30 ° C., 2 After the heat treatment for 5 hours to continue the heat treatment for 1 to 16 hours at a temperature of 1130 ℃ ± 30 ℃ to prepare a silicon wafer in which the oxidation induced lamination defect appears in the center of the wafer, Forming a polysilicon layer having a thickness of 0.1 to 1.6 μm on the back side of the silicon wafer by chemical vapor deposition at a temperature of 670 ° C. ± 30 ° C., Heat-treating the silicon wafer with the polysilicon layer under an oxygen atmosphere for 2 to 5 hours at a temperature of 1000 ° C. ± 30 ° C., and then for 1 to 16 hours at a temperature of 1130 ° C. ± 30 ° C. Heat treatment method of a silicon wafer comprising a. Particles and interstitial dislocations due to crystals do not occur in the wafer surface, and the oxygen concentration is 1.2 × 10 ¹⁸ atoms / cm 3 or less (old ASTM), and at an oxygen atmosphere of 1000 ° C. ± 30 ° C., 2 After the heat treatment for 5 hours and then heat treatment for 1 to 16 hours at a temperature of 1130 ℃ ± 30 ℃ poly-silicon layer having a thickness of 0.1 to 1.6 ㎛ formed on the back surface of the silicon wafer where the oxidation induced lamination defects appear in the center of the wafer Silicon wafer with a silicon layer. Particles and interstitial dislocations due to crystals do not occur in the wafer surface, and the oxygen concentration is 1.2 × 10 ¹⁸ atoms / cm 3 or less (old ASTM), and at an oxygen atmosphere of 1000 ° C. ± 30 ° C., 2 After the heat treatment for 5 hours to continue the heat treatment for 1 to 16 hours at a temperature of 1130 ℃ ± 30 ℃ to prepare a silicon wafer in which the oxidation induced lamination defect appears in the center of the wafer, Forming a polysilicon layer having a thickness of 0.1 to 1.6 ㎛ on the back surface of the silicon wafer by chemical vapor deposition Method for producing a silicon wafer with a polysilicon layer comprising a. The region where the interstitial silicon type defects predominantly exist in the silicon single crystal ingot is called [I], and the region where the interstitial type defects predominantly exist is called [V]. A perfect region where no aggregate of point defects is present is called [P], and a region below the lowest interstitial silicon concentration that is adjacent to the region [I] and belongs to the perfect region [P] to form an invasive dislocation. When [P _I ] is called, [P _v ] is a region below the gap concentration adjacent to the region [V] and belonging to the perfect region [P] to form COP or FPD. A silicon single crystal ingot composed of a mixed region of the region [P _v ] and the region [P _I ] and having an oxygen concentration of 0.8 × 10 ¹⁸ to 1.4 × 10 ¹⁸ atoms / cm 3 (old ASTM), The silicon wafer cut out from the ingot is cut out from the ingot composed of the perfect region [P], which is maintained for 30 to 90 minutes at 600 to 850 ° C. under nitrogen, argon, hydrogen, oxygen or a mixed gas atmosphere thereof. A method of heat treatment of a silicon wafer in which no aggregates exist. The heat treatment method according to claim 4, wherein the heat treatment is a heat treatment at the time of forming a polysilicon layer on the back side of the silicon wafer by chemical vapor deposition. The region where the interstitial silicon type defects predominantly exist in the silicon single crystal ingot is called [I], and the region where the interstitial type defects predominantly exist is called [V]. A perfect region where no aggregate of point defects is present is called [P], and a region below the lowest interstitial silicon concentration that is adjacent to the region [I] and belongs to the perfect region [P] to form an invasive dislocation. When [P _I ] is called, [P _v ] is a region below the gap concentration adjacent to the region [V] and belonging to the perfect region [P] to form COP or FPD. A silicon single crystal ingot composed of a mixed region of the region [P _v ] and the region [P _I ] and having an oxygen concentration of 0.8 × 10 ¹⁸ to 1.4 × 10 ¹⁸ atoms / cm 3 (old ASTM), The silicon wafer cut out from the ingot is cut out from the ingot composed of the perfect region [P], which is maintained at 600 to 850 ° C. for 120 to 250 minutes in a nitrogen, argon, hydrogen, oxygen or mixed gas atmosphere thereof. A method of heat treatment of a silicon wafer in which aggregates do not exist. The heat treatment method according to claim 6, wherein the heat treatment is a heat treatment at the time of forming a polysilicon layer on the back surface of the silicon wafer by chemical vapor deposition. The region where the interstitial silicon type defects predominantly exist in the silicon single crystal ingot is called [I], and the region where the interstitial type defects predominantly exist is called [V]. A perfect region where no aggregate of point defects is present is called [P], and a region below the lowest interstitial silicon concentration that is adjacent to the region [I] and belongs to the perfect region [P] to form an invasive dislocation. When [P _I ] is called, [P _v ] is a region below the gap concentration adjacent to the region [V] and belonging to the perfect region [P] to form COP or FPD. A silicon single crystal ingot composed of a mixed region of the region [P _v ] and the region [P _I ] and having an oxygen concentration of 0.8 × 10 ¹⁸ to 1.4 × 10 ¹⁸ atoms / cm 3 (old ASTM), The silicon wafer cut out from the ingot was heated at a temperature rising rate of 10 to 150 ° C / sec from room temperature to 1150 to 1200 ° C under nitrogen, argon, hydrogen, oxygen or a mixed gas atmosphere thereof, and held at 1150 to 1200 ° C for 0 to 30 seconds. The method of heat-treating a silicon wafer which does not have an aggregate of point defects cut out from the ingot which consists of said perfect region [P] containing the thing. Pulling up the silicon single crystal ingot from the silicon melt; Oxidation-induced lamination defects occur at 25% or more of the total wafer area during thermal oxidation, and ingots of silicon wafers containing 1 × 10 ⁵ to 3 × 10 ⁷ pieces / cm 3 of oxygen precipitates not accompanied by dislocations Manufacturing process from Rapid heating of the silicon wafer from room temperature to 650 to 950 ° C. at a rate of temperature rise of 10 ° C./min or more and holding for 0.5 to 30 minutes Heat treatment method of a silicon wafer comprising a. 10. The method according to claim 9, wherein when the silicon single crystal ingot is thermally oxidized in a silicon wafer state, an oxide-induced lamination defect occurs at 25% or more of the total area of the wafer, and an oxygen precipitate containing 1 to 10 ⁵ to no dislocations is generated. Pulling from the silicon melt to contain 3 × 10 ⁷ pieces / cm 3. Oxygen precipitate formed by pulling a silicon single crystal ingot from a silicon melt, rapidly heating a silicon wafer fabricated from this ingot at a temperature rising rate of 10 ° C./min or more from room temperature to 650 to 950 ° C., and holding for 0.5 to 30 minutes. Wherein the unused layer is formed over a depth of 1 to 100 μm from the wafer surface, and has an oxygen precipitate of 1 × 10 ⁵ to 3 × 10 ⁷ atoms / cm 3 at a portion deeper than the layer. Oxidation-induced lamination defects occur at 25% or more of the total wafer area when thermal oxidation is performed in a silicon wafer state, and the silicon melt contains 1 × 10 ⁵ to 3 × 10 ⁷ atoms / cm 3 without oxygen generation. Single crystal silicon ingot prepared by pulling from.