JP4380162B2 - SOI wafer and method for manufacturing the same - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an SOI wafer, in particular, a high-quality SOI wafer with extremely high electrical reliability and a method for manufacturing the same.
[0002]
[Prior art]
Conventionally, an SOI wafer in which a silicon active layer (SOI layer) is formed on a support substrate has been widely used as a device substrate. As a method for manufacturing such an SOI wafer, for example, a so-called bonding method in which two silicon wafers are bonded to each other via an oxide film is known.
[0003]
In the ion implantation separation method, which is one of the bonding methods, an oxide film (buried oxide film, interlayer) is formed as an insulating layer on the surface of a silicon wafer (bond wafer) serving as a silicon active layer or a silicon wafer (base wafer) serving as a support substrate. An ion-implanted layer (microbubble layer) is formed inside the wafer by ion-implanting ions such as hydrogen from the surface of one side of the bond wafer. Further, after bonding the ion-implanted surface of the bond wafer to the base wafer through an oxide film, the bond wafer is peeled off by using the ion-implanted layer as a boundary. As a result, an SOI wafer in which a thin silicon active layer is formed on the base wafer via the oxide film can be obtained. Note that after the peeling, a heat treatment (bonding heat treatment) for increasing the bonding force between the silicon active layer and the base wafer, or a hydrofluoric acid cleaning for removing an oxide film on the surface may be performed.
[0004]
As a silicon wafer used for manufacturing such an SOI wafer, a silicon single crystal grown by the Czochralski method (CZ method) can be generally used. However, in recent years, a silicon active layer or a buried oxide film has been used. Therefore, the demand for quality of silicon wafers to be used has become stricter.
In particular, as for a bond wafer to be a silicon active layer, it has been proposed to grow a silicon single crystal with few defects and use a high-quality silicon wafer obtained therefrom.
[0005]
Here, the relationship between the pulling speed when growing a silicon single crystal by the Czochralski method and the defects of the grown silicon single crystal will be described.
When the growth rate V is changed from high to low in the direction of the crystal axis in a CZ pulling machine using a furnace internal structure (hot zone: HZ) having a large temperature gradient G in the vicinity of the solid-liquid interface in the crystal, FIG. It is known to be obtained as a defect distribution map as shown.
[0006]
In FIG. 8, the V region is a vacancy, that is, a region in which there are many such as recesses and holes generated due to a shortage of silicon atoms, and the I region is an interstitial silicon that is an extra silicon atom. This is a region where there are many dislocations and excess lumps of silicon atoms. There is a neutral (Neutral, hereinafter abbreviated as N) region where there is no shortage or excess of atoms between the V region and the I region, and the OSF is near the boundary of the V region. It has also been confirmed that defects called oxidation induced stacking faults (Oxidation Induced Stacking Faults) are distributed in a ring shape (hereinafter sometimes referred to as OSF rings) when viewed in a cross section perpendicular to the crystal growth axis. ing.
[0007]
When the growth rate is relatively high, there are high density of grown-in defects such as FPD, LSTD, COP, etc., which are attributed to voids in which vacancy-type point defects are gathered. The region where the defect exists is the V region. As the growth rate decreases, an OSF ring is generated from the periphery of the crystal, an N region is generated outside the ring (low speed side), and when the growth rate is reduced, the OSF ring is placed at the center of the wafer. It shrinks and disappears, and the entire surface becomes an N region. At even lower speeds, defects (giant dislocation clusters) of L / D (Large Dislocation: abbreviations for interstitial dislocation loops, LSEPD, LFPD, etc.) that are thought to be caused by dislocation loops in which interstitial silicon aggregates exist at low density A region where these defects exist is an I region (sometimes referred to as an L / D region).
[0008]
The N region outside the OSF ring between the V region and the I region is a region in which neither FPD, LSTD, or COP caused by holes nor LSEPD or LFPD caused by interstitial silicon exists. Recently, when the N region is further classified, as shown in FIG. 8, an Nv region (region with many vacancies) adjacent to the outside of the OSF ring and an Ni region (interstitial silicon) adjacent to the I region are provided. It is known that in the Nv region, the amount of precipitated oxygen is large when thermal oxidation is performed, and in the Ni region, there is almost no oxygen precipitation.
[0009]
Conventionally, such an N region was present only partially in the wafer plane, but the V / G, which is the ratio between the pulling rate (V) and the temperature gradient (G) in the crystal solid-liquid interface axial direction, is controlled. Thus, as shown in FIG. 8, a crystal in which the N region spreads over the entire lateral surface (the entire wafer surface) can be manufactured.
Therefore, a method of using a silicon single crystal wafer that forms the entire N region as a bond wafer has also been proposed in the manufacture of SOI wafers. For example, when a silicon single crystal is pulled by the Czochralski method, the ratio (V / G) between the pulling speed V and the temperature gradient G at the crystal solid-liquid interface in the pulling axis direction is controlled within a predetermined range. An SOI wafer using an N region silicon wafer as a bond wafer has been proposed (see, for example, Patent Document 1 and Patent Document 2).
[0010]
On the other hand, the base wafer is originally necessary for supporting the SOI layer with the insulating film interposed therebetween, and the element is not directly formed on the surface. For this reason, it has also been proposed to use a dummy grade silicon wafer whose resistance value deviates from the product standard as the base wafer (see Patent Document 3).
[0011]
In general, the base wafer includes a V region grown at a high pulling rate as shown in FIG. 8, or an OSF region and an Nv region in consideration of improvement in quality and productivity. A silicon wafer obtained by growing a silicon single crystal of a certain degree and processing the silicon single crystal grown at such a high speed into a mirror surface is widely used.
[0012]
[Patent Document 1]
JP 2001-146498 A (page 5-8)
[Patent Document 2]
JP 2001-44398 A (page 2-4, FIG. 1)
[Patent Document 3]
Japanese Patent Laid-Open No. 11-40786
[0013]
[Problems to be solved by the invention]
As described above, the surface of the silicon wafer obtained from the silicon single crystal grown at a high speed and the inside of the bulk are formed with high density of vacancy defects such as COP in which vacancies are gathered, and the surface has a size of 50 nm or more. There are many micro pit defects. When an SOI wafer is manufactured using a silicon wafer having a large number of such minute pit defects as a base wafer, high insulation properties can be obtained particularly when the insulating oxide film thickness required in recent years is formed thin. There has been a problem that it is not maintained and the electrical reliability is impaired.
[0014]
Therefore, the present invention has been made in view of such problems. Even when the interlayer insulating oxide film is formed to be extremely thin, for example, to a thickness of 100 nm or less, high insulation is maintained, and a device manufacturing process is performed. It is an object to provide an SOI wafer with high electrical reliability at low cost.
[0015]
[Means for Solving the Problems]
  In order to achieve the above object, according to the present invention, a silicon active layer is formed by bonding a base wafer made of silicon single crystal and a bond wafer through an oxide film, and then thinning the bond wafer. A formed SOI wafer, wherein the base wafer is a silicon single crystal grown by the Czochralski method, the entire surface of the wafer is outside the OSF region, and is a defect region detected by the Cu deposition method SOI wafer characterized by comprising an I region in which dislocation clusters due to interstitial silicon are presentButProvided.
[0016]
Thus, a CZ silicon single crystal in which the entire surface of the base wafer is outside the OSF region, does not include a defect region detected by a Cu deposition method, and includes an I region where dislocation clusters due to interstitial silicon exist. In the case of an SOI wafer made of the above, since there are no minute vacancy defects on the surface of the base wafer, the vacancies on the surface of the base wafer can be obtained even when the thickness of the insulating oxide film on the base wafer is as thin as less than 100 nm, for example. An SOI wafer that is extremely high in electrical reliability without being broken down due to the influence of defects. In addition, since the silicon wafer constituting the base wafer, for example, the entire surface of the wafer is the I region, can be manufactured relatively easily, so that it becomes inexpensive.
[0017]
  In this case, the SOI wafer is preferably formed by an ion implantation separation method in which the bond wafer is thinned by performing ion implantation on the bond wafer and peeling off the formed ion implantation layer..
  As a bonding method, after bonding the bond wafer and the base wafer, the bond wafer can be thinned by grinding and polishing to form an SOI wafer. In this case, the SOI layer is relatively thick. . On the other hand, according to the ion implantation delamination method, the depth of the ion implantation layer, that is, the thickness of the SOI layer can be set to an extremely thin level that has been required in recent years, and an extremely high quality SOI wafer can be obtained.
[0018]
  The thickness of the oxide film can be in the range of 10 to 100 nm..
  In recent years, the thickness of an interlayer insulating oxide film has been required to be, for example, about 50 nm. However, the SOI wafer according to the present invention has deteriorated dielectric breakdown characteristics even when such an extremely thin oxide film is formed. Therefore, high insulation is maintained.
[0019]
  The silicon active layer is a silicon single crystal grown by the Czochralski method, is an N region outside the OSF region over the entire surface, and does not include a defect region detected by the Cu deposition method. Preferably.
  In this way, if the entire surface of the silicon active layer is an N region outside the OSF region and is made of a CZ silicon single crystal that does not include a defect region detected by the Cu deposition method, a defect is present in the device formation region. In addition, even if hydrofluoric acid cleaning is performed, the silicon active layer and the buried oxide film are not destroyed due to defects in the silicon active layer, so that an extremely high quality SOI wafer is obtained.
[0020]
  Furthermore, according to the present invention, a method for manufacturing the SOI wafer as described above is also provided. That is, at least a step of forming an oxide film on at least one of a base wafer and a bond wafer each made of a silicon single crystal, a step of forming an ion implantation layer by ion implantation into the bond wafer, and an ion of the bond wafer In a method for manufacturing an SOI wafer, which includes a step of bonding an implanted surface to a base wafer through the oxide film, and a step of peeling with the ion implantation layer as a boundary, as the base wafer, Czochralski is used as the base wafer. This is a silicon single crystal grown by the method, and is detected by the Cu deposition method at a lower speed side than the OSF region generated in a ring shape when the pulling speed is gradually decreased from a high speed to a low speed during the growth. There is a dislocation cluster that does not include a defect region and is caused by interstitial silicon Method for manufacturing an SOI wafer is provided, wherein the use of those containing I region.
[0021]
When manufacturing an SOI wafer by the ion implantation delamination method, the base wafer does not include a defect region detected by the Cu deposition method as described above, and includes an I region in which dislocation clusters due to interstitial silicon exist. If a CZ silicon single crystal wafer is used, even if the interlayer insulating oxide film is formed to a thickness of less than 100 nm, the dielectric breakdown of the oxide film is caused by vacancy defects existing in the base wafer during the bonding heat treatment or the like. The characteristics are not deteriorated, and a high-quality SOI wafer with high electrical reliability can be manufactured. In addition, a silicon wafer used as a base wafer, for example, a silicon wafer whose entire surface is an I region can be manufactured relatively easily because the control range can be widened, so that a high-quality SOI wafer can be manufactured easily and at low cost. Can be manufactured.
[0022]
  In this case, the bond wafer is a silicon single crystal grown by the Czochralski method. When the entire surface of the wafer is gradually reduced from a high speed to a low speed during the growth, the OSF is generated in a ring shape. It is preferable to use an N region at a lower speed side than the region and not including a defect region detected by the Cu deposition method..
  Thus, if an SOI wafer is manufactured using a defect-free bond wafer, the device formed in the SOI layer is not adversely affected, and the deterioration of the dielectric breakdown characteristics of the interlayer oxide film is surely prevented. An extremely high quality SOI wafer can be manufactured.
[0023]
Recently, when an SOI wafer is manufactured by an ion implantation separation method, a method of reclaiming the peeled bond wafer (peeled wafer) and reusing it as a base wafer (or bond wafer) has been proposed (for example, a special wafer). (See Kaihei 11-297583). Therefore, if a defect-free bond wafer as described above is used, and then the peeled wafer is regenerated and reused as a bond wafer, a high-quality SOI wafer can be manufactured at a low cost.
[0024]
Hereinafter, the present invention will be described in more detail.
The present inventors conducted a detailed investigation on the influence of the base wafer of the SOI wafer by the bonding method on the buried oxide film. As a result, when an SOI wafer is manufactured using a silicon single crystal that has been conventionally grown at a high speed, that is, a silicon wafer having a large number of vacancy-type micro defects of 50 nm or more on the surface, When the insulating oxide film has a sufficient thickness of several hundreds of nanometers or more, problems such as deterioration of the dielectric breakdown characteristics due to the influence of the base wafer hardly occur, but when the thin film is less than 100 nm. It has been found that there is a possibility that the maintenance of the insulation due to the influence of the base wafer may be disturbed. In particular, in the case of a 50 nm level buried oxide film that has been demanded in recent years, the conventional V-rich base wafer affects the interlayer insulating oxide film during the bonding heat treatment and the like, and high insulation cannot be maintained. It has been found that there is an extremely high possibility of impairing reliability.
[0025]
Accordingly, the present inventors can reduce the micro defects of the base wafer to make an SOI wafer with high electrical reliability that does not cause deterioration of dielectric breakdown characteristics even when the insulating oxide film is formed to 100 nm or less. The following surveys and examinations were conducted.
First, when pulling up a silicon single crystal, when gradually decreasing from a high speed to a low speed from the crystal shoulder to the straight tail, the OSF shrinks when reaching a certain growth rate as described above, and thereafter, the Nv is further reduced in the low speed region. It is known that each phase is formed in the order of Ni, I (large dislocation cluster generation) region. Recently, as shown in FIG. 2, a part of the Nv region where defects are detected by the Cu deposition method immediately after the disappearance of the OSF (hereinafter sometimes referred to as Cu deposition defect region) exists. It was also found out (see, for example, JP-A-2002-201093).
[0026]
The Cu deposition method is an evaluation of a wafer that can accurately measure the position of defects in a semiconductor wafer, improve the detection limit for defects in a semiconductor wafer, and accurately measure and analyze even finer defects. Is the law.
A specific method for evaluating a wafer is to form an insulating film having a predetermined thickness on the wafer surface, destroy the insulating film on the defect site formed near the wafer surface, and electrolyze the defect site with Cu or the like. The substance is deposited (deposited). In other words, in the Cu deposition method, when a potential is applied to an oxide film formed on the wafer surface in a liquid in which Cu ions are dissolved, a current flows through a portion where the oxide film is degraded, and the Cu ions become Cu. This is an evaluation method using the precipitation. It is known that a defect such as COP exists in a portion where the oxide film easily deteriorates.
[0027]
The defect portion of the Cu-deposited wafer can be analyzed under a condenser lamp or directly with the naked eye to evaluate its distribution and density. Further, it can be observed with a microscope, a transmission electron microscope (TEM) or It can also be confirmed with a scanning electron microscope (SEM).
[0028]
The inventors then further investigated the defects in these areas.
Specifically, when the silicon single crystal growth is gradually reduced from a high speed to a low speed, a focused ion beam (FIB) processing is performed after coordinate identification of the V region immediately before the disappearance of OSF by a surface inspection device (MAGICS; product name). As a result of TEM observation of the point, the presence of a minute pit defect of about 20 nm was confirmed. In the V region, voids become finer as the region immediately before the disappearance of the OSF, but even if the minute pit defects in the V region are quite fine, the initial oxide film breakdown voltage (TZDB) time remarkably deteriorates. Let
[0029]
On the other hand, when the silicon single crystal growth is gradually reduced from a high speed to a low speed, the Cu deposition defect region immediately after the disappearance of the OSF does not have a significant deterioration in breakdown voltage level as in the V region, and the TZDB characteristic is almost 100% in the plane. Although the C mode was shown in the region, there was a slight deterioration in the time dependent dielectric breakdown (TDDB) characteristics.
[0030]
As a result of such investigations and examinations, as the interlayer insulating oxide film required for some devices has recently been made thinner, bond wafers, that is, silicon active layers, have been used in V regions and OSFs conventionally used. In addition to the silicon single crystal wafer in which the Cu deposition defect region exists also in the region or the N region, even when such a silicon wafer is used as the base wafer, it becomes an obstacle to the insulating properties of the oxide film, and the electrical characteristics It has been found that defects related to can occur.
In addition, the vacancy type defects existing in these regions may cause deterioration of the quality of the insulating oxide film during the bonding heat treatment, and particularly in the case of a thin film whose film thickness is less than 100 nm, excellent insulation It was found that it was impossible to maintain the property, causing electrical failure and significantly reducing the reliability.
[0031]
In order to avoid such an electrical failure, it is conceivable to use an N region specular wafer having no defect region detected by the Cu deposition method as the base wafer of the SOI wafer. However, in order to grow a silicon single crystal having an N region and no Cu deposition defect region, the growth rate is limited to a narrow range, and V / G is kept at a predetermined value. Since advanced crystal growth technology is required, productivity and manufacturing yield are low, resulting in an increase in cost.
[0032]
Therefore, the present inventors can use the CZ silicon wafer including the I region as a base wafer that can be easily manufactured at a low speed without using an advanced crystal growth technique. Even if the thickness is 100 nm or less, it has been found that an SOI wafer having excellent electrical characteristics can be produced at low cost, and the present invention has been completed.
[0033]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be specifically described with reference to the accompanying drawings, but the present invention is not limited thereto.
FIG. 1 is a flowchart showing an example of a process for manufacturing an SOI wafer according to the present invention by an ion implantation separation method.
First, in the first step (a), two silicon mirror wafers, that is, a bond wafer 21 serving as an SOI layer and a base wafer 22 serving as a support substrate are prepared. Here, in the present invention, the base wafer 22 is a silicon single crystal grown by the Czochralski method, and the OSF region generated in a ring shape when the pulling rate is gradually reduced from high to low during the growth. A wafer is used which is on the lower speed side, does not include a defect region detected by the Cu deposition method, and includes an I region where dislocation clusters due to interstitial silicon exist.
[0034]
On the other hand, the bond wafer 21 may be used according to the quality required for the silicon active layer. However, since a device is formed on the silicon active layer, if there is a defect in the silicon active layer, the device It will affect the quality. Accordingly, it is preferable to use a bond wafer 21 made of a silicon single crystal having no micro defects. Therefore, as the bond wafer 21, it is desirable to use a wafer which is the N region on the lower speed side than the OSF region where the entire surface of the wafer is generated in a ring shape and does not include a defect region detected by the Cu deposition method.
[0035]
Each silicon single crystal used as the bond wafer 21 or the base wafer 22 as described above can be grown using, for example, a single crystal manufacturing apparatus 30 as shown in FIG.
This single crystal pulling apparatus 30 includes a pulling chamber 31, a crucible 32 provided in the pulling chamber 31, a heater 34 disposed around the crucible 32, a crucible holding shaft 33 for rotating the crucible 32, and a rotation mechanism thereof. (Not shown), a seed chuck 6 that holds a seed crystal of silicon, a wire 7 that pulls up the seed chuck 6, and a winding mechanism (not shown) that rotates or winds the wire 7. A heat insulating material 35 is disposed around the outside of the heater 34.
[0036]
The crucible 32 is provided with a quartz crucible on the inner side containing the silicon melt (hot water) 2 and on the outer side with a graphite crucible.
Recently, a magnet (not shown) is installed outside the pulling chamber 31 in the horizontal direction, and a magnetic field in the horizontal direction or the vertical direction is applied to the silicon melt 2 to suppress convection of the melt, thereby The so-called MCZ method is often used to achieve stable growth.
[0037]
Further, a cylindrical graphite tube (heat shield plate) 12 is provided so as to surround the grown silicon single crystal 1, and an annular outer heat insulating material 10 is provided on the outer periphery in the vicinity of the solid-liquid interface 4 of the crystal. . In some cases, an inner heat insulating material is also provided inside the graphite tube 12. Such a heat insulating material 10 is installed with a space of 2 to 20 cm between its lower end and the molten metal surface 3 of the silicon melt 2. By doing so, the difference between the temperature gradient Gc [° C./cm] in the crystal center portion and the temperature gradient Ge in the crystal periphery portion becomes small, and for example, the furnace temperature so that the temperature gradient around the crystal is lower than the crystal center. Can also be controlled.
Further, a cooling cylinder 14 is provided on the graphite cylinder 12 and forced cooling is performed by flowing a cooling medium. Further, a cylindrical cooling means for blowing a cooling gas or blocking the radiant heat to cool the single crystal may be provided.
[0038]
In order to manufacture a silicon single crystal using such a single crystal pulling apparatus 30, first, a high-purity polycrystalline silicon raw material of silicon is heated to a melting point (about 1420 ° C.) or higher in a crucible 32 to be melted. Next, the tip of the seed crystal is brought into contact with or immersed in the approximate center of the surface of the melt 2 by unwinding the wire 7. Thereafter, the crucible holding shaft 33 is rotated and the wire 7 is wound while being rotated. As a result, the seed crystal is pulled up while rotating, and the growth of the single crystal is started. Thereafter, the single crystal rod 1 having a substantially cylindrical shape can be obtained by appropriately adjusting the pulling speed and temperature.
[0039]
In order to grow a silicon single crystal that is an N region and does not include a Cu deposition defect region used as the bond wafer 21, for example, the growth rate (pulling rate) of the silicon single crystal being pulled is increased from a high speed. The growth rate at the boundary where the defect region detected by the Cu deposition method disappears after the OSF region generated in the ring shape disappears when gradually decreasing to a low speed, and the lattice when the growth rate is further decreased The crystal is grown by controlling the growth rate between the growth rate of the boundary where the interphase loop is generated.
[0040]
That is, when the growth rate of the silicon single crystal being pulled is gradually decreased from the high speed to the low speed from the crystal shoulder to the straight trunk, the V region, the OSF ring region, Each phase is formed in the order of the Cu deposition defect region, the Nv region, the Ni region, and the I region (giant dislocation cluster generation region). Among the N regions, defects detected by Cu deposition remaining after the OSF ring disappears. A single crystal is grown by controlling the growth rate between the growth rate at the boundary where the region disappears and the growth rate at which the I region is generated when the growth rate is further reduced. According to such a method, a V region defect such as FPD, an I region defect such as a giant dislocation cluster (LSEPD, LFPD), an OSF defect, and an N region that has no defect detected by the Cu deposition method. A silicon single crystal can be grown.
[0041]
Then, after processing the silicon single crystal grown as described above into a mirror-polished wafer (PW), the PW is arbitrarily extracted from the unit lot for each ingot block, and then evaluated by the Cu deposition method. If it is free, it may be adopted as the bond wafer 21.
[0042]
However, in order to manufacture a silicon wafer having no defect on the entire surface of the wafer, V / G must be uniformly controlled so as to be an N region in the crystal diameter direction throughout the entire process of growing a silicon single crystal. In addition, the setting range of the growth rate is very limited, and a very advanced crystal growth technique is required, resulting in an increase in manufacturing cost.
Therefore, in the present invention, as described above, the base wafer 22 is located on the lower speed side than the OSF region generated in a ring shape when the pulling speed is gradually decreased from the high speed to the low speed during the growth. A silicon wafer made of a CZ silicon single crystal that does not include a defect region detected by the position method and includes an I region in which a dislocation cluster due to interstitial silicon exists is used.
[0043]
Such a silicon single crystal can be grown without using an advanced crystal growth technique as in the case of growing a silicon single crystal in which the entire wafer surface is defect-free. For example, in order to grow a silicon single crystal that becomes the entire I region, it is relatively easy to grow on the low speed side without being restricted to uniformly control V / G in the crystal diameter direction during crystal growth. be able to. Even if V / G in the crystal diameter direction is non-uniform, in the case of I region crystal production, G is higher than the hot zone used for N region crystal production, that is, the temperature gradient near the solid-liquid interface in the crystal is large. Use of hot zones is possible. Therefore, depending on the design of the hot zone, it is possible to pull up the single crystal serving as the entire I region at a higher speed than when growing the single crystal serving as the entire N region. This is because it is not necessary to make the V / G value in the crystal plane uniform.
[0044]
The base wafer 22 used in the present invention is not limited to a wafer whose entire surface is an I region, and includes a Ni region where interstitial silicon is dominant in addition to the I region, as shown in FIG. You may use the wafer which consists of a silicon single crystal which does not contain Cu deposition defect area | region. Since such a wafer also has no defects due to vacancies in the surface, even if the insulating film is thin, its dielectric breakdown characteristics are not deteriorated.
[0045]
Next, in the step (b) of FIG. 1, the surface of at least one of the bond wafer 21 and the base wafer 22 is oxidized. Here, the bond wafer 21 is thermally oxidized to form an oxide film 23 on the surface thereof. At this time, the oxide film 23 has a thickness that can maintain the required insulating properties. However, in the present invention, an extremely thin oxide film having a thickness in the range of 10 to 100 nm can be formed.
[0046]
As a base wafer, if a silicon wafer that has been used in the past, for example, a silicon wafer having a large number of vacancy-type microdefects of 50 nm or more on the surface is used and an SOI wafer is manufactured with a buried oxide film thickness of 100 nm or less, the oxide film becomes Under the influence of vacancy defects present on the surface of the base wafer, there is a risk of destruction by subsequent bonding heat treatment or heat treatment in the device process. However, in the present invention, a silicon wafer made of a CZ silicon single crystal that does not include a defect region detected by the Cu deposition method and includes an I region where dislocation clusters due to interstitial silicon exist is used as the base wafer 22. Therefore, even if the evaluation by the Cu deposition method is performed, the oxide film does not break down. For example, even if the thickness of the oxide film 23 is set to 100 nm or less, there is no problem such as deterioration of the dielectric breakdown characteristics. .
Note that if the thickness of the oxide film 23 is less than 10 nm, it takes time to form the oxide film, but the insulation may not be maintained.
[0047]
In the step (c), hydrogen ions are ion-implanted from the surface on one side of the bond wafer 21 having the oxide film 23 formed on the surface. Note that rare gas ions or mixed gas ions of hydrogen ions and rare gas ions may be ion-implanted. Thereby, the ion implantation layer 24 parallel to the surface can be formed inside the wafer at the average ion penetration depth. Note that the depth of the ion implantation layer at this time is reflected in the thickness of the finally formed SOI layer. Therefore, the thickness of the SOI layer can be controlled by performing ion implantation by controlling the implantation energy and the like, for example, an SOI layer having a thickness of 200 nm or less can be obtained.
[0048]
In the step (d), the ion-implanted surface of the bond wafer 21 and the surface of the base wafer 22 are bonded together via the oxide film 23. For example, by bringing the surfaces of the two wafers 21 and 22 into contact with each other in a clean atmosphere at room temperature, the wafers are bonded to each other without using an adhesive or the like.
[0049]
Next, in step (e), a part of the bond wafer 21 is peeled off by the ion implantation layer 24 by heat treatment. For example, if a bond wafer 21 and a base wafer 22 are bonded and bonded to each other and subjected to a heat treatment at a temperature of about 500 ° C. or higher in an inert gas atmosphere, the separation wafer 25 is caused by crystal rearrangement and bubble aggregation. And SOI wafer 26 (SOI layer 27 + buried oxide film 23 + base wafer 22).
[0050]
Here, with respect to the peeled wafer 25 produced as a by-product, recently, a method has been proposed in which the peeled surface is subjected to a regeneration process such as polishing and reused as a base wafer or a bond wafer. As described above, since the bond wafer 21 is a silicon wafer which is an N region and does not include a Cu deposition defect region, a silicon wafer obtained by reprocessing the separation wafer 25 is, for example, a bond wafer. By reusing as 21, the same high quality SOI wafer can be manufactured. That is, the SOI wafer according to the present invention is substantially manufactured from one silicon wafer, and the manufacturing cost can be further reduced.
[0051]
In step (f), a bonding heat treatment is applied to the SOI wafer 26. In this step (f), the bonding strength between the wafers adhered in the bonding step and the peeling heat treatment step in the steps (d) and (e) is weak to use in the device manufacturing step as it is. The SOI wafer 26 is subjected to a high temperature heat treatment so that the bond strength is sufficient. For example, the heat treatment can be performed in an inert gas atmosphere at 1050 ° C. to 1200 ° C. for 30 minutes to 2 hours.
Even if heat treatment is performed at such a high temperature, since there are no void-type micro defects on the entire surface of the base wafer 22, the dielectric breakdown characteristics of the buried oxide film 23 are not deteriorated, and high insulation is maintained. can do.
[0052]
In step (g), the oxide film formed on the surface of the SOI wafer 26 is removed by hydrofluoric acid cleaning. At this time, if there is a vacancy type defect in the silicon active layer 27, there is a possibility that pits are generated by HF reaching the buried oxide film through the defect. However, the silicon active layer 27 is an N region over the entire surface. In addition, since it is composed of a silicon single crystal that does not include a defect region detected by the Cu deposition method, the pits are enlarged and the SOI layer 27 and the buried oxide film 23 are destroyed even if hydrofluoric acid cleaning is performed. Nor.
[0053]
Further, in step (h), oxidation for adjusting the thickness of the SOI layer 27 is performed as necessary. Next, in step (I), so-called sacrificial oxidation for removing the oxide film 28 by hydrofluoric acid cleaning is performed.
[0054]
In the SOI wafer 26 manufactured through the steps (a) to (I) as described above, the base wafer 22 includes a defect region that is entirely outside the OSF region and detected by the Cu deposition method. And a CZ silicon single crystal including an I region where dislocation clusters due to interstitial silicon exist. On the other hand, the silicon active layer 27 is composed of a CZ silicon single crystal that is an N region outside the OSF region over the entire surface and does not include a defect region detected by the Cu deposition method. That is, since there are no hole-type minute defects on the surface of the base wafer 22, high insulation is maintained and the electrical reliability is extremely high even though the buried oxide film 23 is extremely thin. In addition, since the SOI layer 27 is defect-free, when a device is formed, a very high yield can be achieved.
[0055]
【Example】
EXAMPLES Hereinafter, although an Example and a comparative example are given and this invention is demonstrated, this invention is not limited to this.
(Experiment 1): Confirmation of pulling conditions
Using the single crystal manufacturing apparatus 30 of FIG. 3, the crystal growth rate was gradually reduced as follows, and the growth rate at the boundary of each region was examined.
First, 150 kg of polycrystalline silicon as a raw material was charged in a quartz crucible having a diameter of 24 inches (600 mm) to grow a silicon single crystal having a diameter of 210 mm. The oxygen concentration was set to 23 to 26 ppma (ASTM'79 value). When growing a single crystal, as shown in FIG. 4 (A), the growth rate was controlled to gradually decrease linearly in the range of 0.80 mm / min to 0.40 mm / min from the crystal head to the tail. .
[0056]
Then, as shown in FIGS. 4 (A) and 4 (B), a vertically split cut was made in the crystal axis direction from the head to the tail of the pulled single crystal, and then a wafer-shaped mirror-finished sample with a diameter of 200 mm was produced.
One of the samples was measured for wafer lifetime (WLT) after oxygen precipitation heat treatment (measuring instrument: SEMILAB WT-85), and the distribution of each region in the V region, OSF region, and I region, and the growth rate of each region boundary. It was confirmed. The detailed evaluation method in this experiment is as follows.
[0057]
(A) An ingot with a diameter of 210 mm is cut into blocks with a length of every 10 cm in the crystal axis direction, and then cut into pieces in the crystal axis direction, and then, as shown in FIG. An 8-inch wafer-shaped mirror-finished sample was finished.
(B) Of the above samples, the first sample was heat treated in a wafer heat treatment furnace at 620 ° C. for 2 hours (nitrogen atmosphere), followed by 800 ° C. for 4 hours (nitrogen atmosphere) and 1000 ° C. for 16 hours (dry oxygen atmosphere). After performing the step heat treatment, it was cooled and a WLT map by SEMILAB WT-85 was prepared.
[0058]
Experimental result
From the above experiment, the growth rate of each region boundary of the V region, the OSF region, the N region, and the I region was confirmed.
V region / OSF region boundary: 0.595 mm / min
OSF region / N region boundary: 0.587 mm / min
N region / I region boundary: 0.579 mm / min
[0059]
(Experiment 2): Production of SOI wafer
With the same pulling apparatus as in Experiment 1 as shown in FIG. 3, 150 kg of raw material polycrystalline silicon was charged into a 24-inch quartz crucible, and two ingots with a diameter of 210 mm were pulled up based on the results of Experiment 1.
At that time, as shown in FIG. 6, the first growth is set so that the growth rate is constant at 0.65 mm / min from the crystal head to the tail, and is pulled up so that a V region is formed in the entire surface. It was. In the second line, the growth rate was set to be constant at 0.55 mm / min from the crystal head to the tail, and this time it was pulled up so that the I region was formed over the entire surface. The oxygen concentration was prepared so as to aim at 24-26 ppma (ASTM '79). A mirror wafer processed from each ingot was used as a base wafer.
[0060]
On the other hand, as a bond wafer, a silicon single crystal which is an N region and does not include a defect region detected by a Cu deposition method in different hot zones was grown, and a mirror wafer obtained from this single crystal was used.
Using the base wafer having the entire V region or I region as described above and a defect-free bond wafer, SOI wafers having an insulating oxide film thickness of 70 nm and a silicon active layer thickness of 200 nm are manufactured. did.
[0061]
The silicon active layer was removed from the manufactured SOI wafer by selective etching with a potassium hydroxide solution. Next, the base wafer having the remaining insulating oxide film layer was evaluated by a Cu deposition method with an electrolytic strength of 6 MV / cm.
As a result, in the case of the insulating oxide film after the bonding oxidation, as shown in FIG. 7A, the destruction of the oxide film was confirmed in the base wafer whose entire in-plane region was the V region. On the other hand, in the case of the base wafer in which the entire in-plane region is the I region, no oxide film breakdown occurred as seen in FIG.
[0062]
The present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and the present invention has substantially the same configuration as the technical idea described in the claims of the present invention, and any device that exhibits the same function and effect is the present invention. It is included in the technical scope of the invention.
[0063]
For example, in the above-described embodiment, the case where an SOI wafer is manufactured by an ion implantation separation method using two silicon wafers has been described. However, in the present invention, after bonding, the back surface side of the bond wafer is ground or polished. The present invention can also be applied to SOI wafers manufactured by thinning.
[0064]
【The invention's effect】
As described above, according to the present invention, the entire surface of the base wafer is outside the OSF region, does not include the defect region detected by the Cu deposition method, and there are dislocation clusters caused by interstitial silicon. An SOI wafer including an I region is provided. Such an SOI wafer maintains excellent insulation characteristics even if the thickness of the buried oxide film is 100 nm or less. If a device is manufactured using this, a device with excellent electrical characteristics can be obtained. It can be produced with a yield. Further, since the base wafer can be manufactured relatively easily, the manufacturing cost can be kept low.
[Brief description of the drawings]
FIG. 1 is a flowchart showing an example of a manufacturing process of an SOI wafer according to the present invention.
FIG. 2 is an explanatory diagram showing a region of a crystal used when manufacturing an SOI wafer according to the present invention.
FIG. 3 is an example of a CZ silicon single crystal manufacturing apparatus that can be used in the present invention.
FIG. 4A is a relationship diagram showing a relationship between a single crystal growth rate and a crystal cutting position.
(B) It is explanatory drawing which shows a growth rate and each area | region.
FIG. 5 is an explanatory diagram showing a method for producing an evaluation sample.
FIG. 6 is an explanatory diagram showing the growth rate of each grown silicon single crystal.
FIG. 7 is a diagram showing a defect distribution by a Cu deposition method.
(A) Base wafer in V region
(B) I-region base wafer (no Cu deposition defects)
FIG. 8 is an explanatory diagram for explaining a crystal defect region;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Growing single crystal rod, 2 ... Silicon melt, 3 ... Hot water surface, 4 ... Solid-liquid interface,
6 ... Seed chuck, 7 ... Wire, 10 ... Outer insulation, 12 ... Graphite tube,
21 ... Bond wafer, 22 ... Base wafer,
23 ... oxide film (insulating layer), 24 ... ion implantation layer, 25 ... peeling wafer,
26 ... SOI wafer, 27 ... Silicon active layer (SOI layer),
28 ... oxide film, 30 ... single crystal pulling device, 31 ... pulling chamber,
32 ... crucible, 33 ... crucible holding shaft, 34 ... heater, 35 ... heat insulating material.

Claims (3)

A silicon active layer was formed by thinning the bond wafer after bonding a base wafer made of silicon single crystal and a bond wafer through an oxide film having a thickness in the range of 10 to 100 nm . An SOI wafer, wherein the base wafer is a silicon single crystal grown by the Czochralski method, and the entire surface of the wafer is outside the OSF region and does not include a defect region detected by the Cu deposition method. And the bond wafer is a silicon single crystal grown by the Czochralski method and includes an N region outside the OSF region over the entire surface. And that does not include defect areas detected by the Cu deposition method. SOI wafer characterized by.   The SOI wafer is formed by an ion implantation delamination method in which the bond wafer is thinned by performing ion implantation on the bond wafer and delamination with the formed ion implantation layer. Item 4. The SOI wafer according to Item 1. Forming at least one of a base wafer and a bond wafer each made of a silicon single crystal, and forming an oxide film having a thickness in a range of 10 to 100 nm, and implanting ions into the bond wafer A step of forming an ion implantation layer, a step of bonding an ion-implanted surface of the bond wafer to a base wafer via the oxide film, and a step of peeling with the ion implantation layer as a boundary. In the method for manufacturing an SOI wafer having the above structure, the base wafer is a silicon single crystal grown by the Czochralski method, and is generated in a ring shape when the pulling speed is gradually decreased from a high speed to a low speed during the growth. Includes a defect area detected by the Cu deposition method on the lower speed side than the OSF area And a silicon single crystal grown by the Czochralski method as the bond wafer, wherein the bond wafer includes an I region where dislocation clusters due to interstitial silicon are present. When the pulling speed is gradually decreased from high speed to low speed, an N area on the lower speed side than the OSF area generated in a ring shape and not including a defect area detected by the Cu deposition method is used. A method for manufacturing an SOI wafer.

Images