FR2858461B1 - Realisation d'une structure comprenant une couche protegeant contre des traitements chimiques - Google Patents

Realisation d'une structure comprenant une couche protegeant contre des traitements chimiques

Info

Publication number
FR2858461B1
FR2858461B1 FR0309380A FR0309380A FR2858461B1 FR 2858461 B1 FR2858461 B1 FR 2858461B1 FR 0309380 A FR0309380 A FR 0309380A FR 0309380 A FR0309380 A FR 0309380A FR 2858461 B1 FR2858461 B1 FR 2858461B1
Authority
FR
France
Prior art keywords
implementing
protective layer
chemical treatments
layer against
against chemical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
FR0309380A
Other languages
English (en)
Other versions
FR2858461A1 (fr
Inventor
Bruno Ghyselen
Olivier Rayssac
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Priority to FR0309380A priority Critical patent/FR2858461B1/fr
Priority to US10/686,082 priority patent/US7169683B2/en
Priority to JP2006521625A priority patent/JP2007500436A/ja
Priority to EP04767815A priority patent/EP1649509A2/fr
Priority to PCT/FR2004/002040 priority patent/WO2005013338A2/fr
Priority to KR1020067001850A priority patent/KR100751619B1/ko
Priority to CNB2004800223396A priority patent/CN100401499C/zh
Publication of FR2858461A1 publication Critical patent/FR2858461A1/fr
Application granted granted Critical
Publication of FR2858461B1 publication Critical patent/FR2858461B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Element Separation (AREA)
  • Weting (AREA)
  • Led Devices (AREA)
  • Photovoltaic Devices (AREA)
FR0309380A 2003-07-30 2003-07-30 Realisation d'une structure comprenant une couche protegeant contre des traitements chimiques Expired - Lifetime FR2858461B1 (fr)

Priority Applications (7)

Application Number Priority Date Filing Date Title
FR0309380A FR2858461B1 (fr) 2003-07-30 2003-07-30 Realisation d'une structure comprenant une couche protegeant contre des traitements chimiques
US10/686,082 US7169683B2 (en) 2003-07-30 2003-10-14 Preventive treatment method for a multilayer semiconductor structure
EP04767815A EP1649509A2 (fr) 2003-07-30 2004-07-29 Realisation d'une structure comprenant une couche protegeant contre des traitements chimiques
PCT/FR2004/002040 WO2005013338A2 (fr) 2003-07-30 2004-07-29 Realisation d’une structure comprenant une couche protegeant contre des traitements chimiques
JP2006521625A JP2007500436A (ja) 2003-07-30 2004-07-29 耐化学処理保護層を有する積層構造体の製造法
KR1020067001850A KR100751619B1 (ko) 2003-07-30 2004-07-29 화학적 처리에 대한 보호층을 포함하는 구조체 제조방법
CNB2004800223396A CN100401499C (zh) 2003-07-30 2004-07-29 制造包括抗化学处理保护层的结构及可分离结构的方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0309380A FR2858461B1 (fr) 2003-07-30 2003-07-30 Realisation d'une structure comprenant une couche protegeant contre des traitements chimiques

Publications (2)

Publication Number Publication Date
FR2858461A1 FR2858461A1 (fr) 2005-02-04
FR2858461B1 true FR2858461B1 (fr) 2005-11-04

Family

ID=34043671

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0309380A Expired - Lifetime FR2858461B1 (fr) 2003-07-30 2003-07-30 Realisation d'une structure comprenant une couche protegeant contre des traitements chimiques

Country Status (7)

Country Link
US (1) US7169683B2 (fr)
EP (1) EP1649509A2 (fr)
JP (1) JP2007500436A (fr)
KR (1) KR100751619B1 (fr)
CN (1) CN100401499C (fr)
FR (1) FR2858461B1 (fr)
WO (1) WO2005013338A2 (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7235461B2 (en) * 2003-04-29 2007-06-26 S.O.I.Tec Silicon On Insulator Technologies Method for bonding semiconductor structures together
FR2858461B1 (fr) * 2003-07-30 2005-11-04 Soitec Silicon On Insulator Realisation d'une structure comprenant une couche protegeant contre des traitements chimiques
EP1831922B9 (fr) * 2004-12-28 2010-02-24 S.O.I.Tec Silicon on Insulator Technologies Procede servant a obtenir une couche mince possedant une densite faible de trous
US8273636B2 (en) 2006-10-27 2012-09-25 Soitec Process for the transfer of a thin layer formed in a substrate with vacancy clusters
US7678668B2 (en) * 2007-07-04 2010-03-16 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of SOI substrate and manufacturing method of semiconductor device
FR2926672B1 (fr) * 2008-01-21 2010-03-26 Soitec Silicon On Insulator Procede de fabrication de couches de materiau epitaxie
US20110180896A1 (en) * 2010-01-25 2011-07-28 International Business Machines Corporation Method of producing bonded wafer structure with buried oxide/nitride layers
JP6248458B2 (ja) * 2013-08-05 2017-12-20 株式会社Sumco 貼り合わせウェーハの製造方法および貼り合わせウェーハ

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4771016A (en) * 1987-04-24 1988-09-13 Harris Corporation Using a rapid thermal process for manufacturing a wafer bonded soi semiconductor
US5362667A (en) * 1992-07-28 1994-11-08 Harris Corporation Bonded wafer processing
JP3214631B2 (ja) * 1992-01-31 2001-10-02 キヤノン株式会社 半導体基体及びその作製方法
US6004865A (en) * 1993-09-06 1999-12-21 Hitachi, Ltd. Method of fabricating multi-layered structure having single crystalline semiconductor film formed on insulator
US5882532A (en) * 1996-05-31 1999-03-16 Hewlett-Packard Company Fabrication of single-crystal silicon structures using sacrificial-layer wafer bonding
CA2225131C (fr) * 1996-12-18 2002-01-01 Canon Kabushiki Kaisha Procede de production d'articles semi-conducteurs
JPH11111839A (ja) * 1997-10-01 1999-04-23 Denso Corp 半導体基板およびその製造方法
JP3358550B2 (ja) * 1998-07-07 2002-12-24 信越半導体株式会社 Ｓｏｉウエーハの製造方法ならびにこの方法で製造されるｓｏｉウエーハ
JP3887973B2 (ja) * 1998-10-16 2007-02-28 信越半導体株式会社 Ｓｏｉウエーハの製造方法及びｓｏｉウエーハ
JP3537690B2 (ja) * 1998-12-25 2004-06-14 京セラ株式会社 化合物半導体装置およびその製造法
JP2000315727A (ja) * 1999-03-02 2000-11-14 Rohm Co Ltd 半導体装置の製造方法
US6902987B1 (en) * 2000-02-16 2005-06-07 Ziptronix, Inc. Method for low temperature bonding and bonded structure
FR2835096B1 (fr) 2002-01-22 2005-02-18 Procede de fabrication d'un substrat auto-porte en materiau semi-conducteur monocristallin
US6583440B2 (en) * 2000-11-30 2003-06-24 Seiko Epson Corporation Soi substrate, element substrate, semiconductor device, electro-optical apparatus, electronic equipment, method of manufacturing the soi substrate, method of manufacturing the element substrate, and method of manufacturing the electro-optical apparatus
US6410938B1 (en) * 2001-04-03 2002-06-25 Advanced Micro Devices, Inc. Semiconductor-on-insulator device with nitrided buried oxide and method of fabricating
FR2823599B1 (fr) * 2001-04-13 2004-12-17 Commissariat Energie Atomique Substrat demomtable a tenue mecanique controlee et procede de realisation
FR2835095B1 (fr) * 2002-01-22 2005-03-18 Procede de preparation d'ensembles a semi-conducteurs separables, notamment pour former des substrats pour l'electronique, l'optoelectrique et l'optique
US6902656B2 (en) * 2002-05-24 2005-06-07 Dalsa Semiconductor Inc. Fabrication of microstructures with vacuum-sealed cavity
US6979630B2 (en) * 2002-08-08 2005-12-27 Isonics Corporation Method and apparatus for transferring a thin layer of semiconductor material
FR2858461B1 (fr) * 2003-07-30 2005-11-04 Soitec Silicon On Insulator Realisation d'une structure comprenant une couche protegeant contre des traitements chimiques
FR2866983B1 (fr) * 2004-03-01 2006-05-26 Soitec Silicon On Insulator Realisation d'une entite en materiau semiconducteur sur substrat
FR2867310B1 (fr) * 2004-03-05 2006-05-26 Soitec Silicon On Insulator Technique d'amelioration de la qualite d'une couche mince prelevee
US7087134B2 (en) * 2004-03-31 2006-08-08 Hewlett-Packard Development Company, L.P. System and method for direct-bonding of substrates

Also Published As

Publication number Publication date
EP1649509A2 (fr) 2006-04-26
FR2858461A1 (fr) 2005-02-04
US20050026391A1 (en) 2005-02-03
CN100401499C (zh) 2008-07-09
CN1833315A (zh) 2006-09-13
JP2007500436A (ja) 2007-01-11
KR20060033917A (ko) 2006-04-20
KR100751619B1 (ko) 2007-08-22
WO2005013338A3 (fr) 2005-06-30
WO2005013338A2 (fr) 2005-02-10
US7169683B2 (en) 2007-01-30

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Effective date: 20120423

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