FR2883659B1 - Procede de fabrication d'une hetero-structure comportant au moins une couche epaisse de materiau semi-conducteur - Google Patents

Procede de fabrication d'une hetero-structure comportant au moins une couche epaisse de materiau semi-conducteur

Info

Publication number
FR2883659B1
FR2883659B1 FR0502923A FR0502923A FR2883659B1 FR 2883659 B1 FR2883659 B1 FR 2883659B1 FR 0502923 A FR0502923 A FR 0502923A FR 0502923 A FR0502923 A FR 0502923A FR 2883659 B1 FR2883659 B1 FR 2883659B1
Authority
FR
France
Prior art keywords
hetero
manufacturing
semiconductor material
thick layer
thick
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR0502923A
Other languages
English (en)
Other versions
FR2883659A1 (fr
Inventor
Ian Cayrefourcq
Fabrice Letertre
Bruno Ghyselen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Priority to FR0502923A priority Critical patent/FR2883659B1/fr
Priority to US11/147,575 priority patent/US7601611B2/en
Priority to JP2008500217A priority patent/JP5053252B2/ja
Priority to EP06725289A priority patent/EP1861873A1/fr
Priority to KR1020077020396A priority patent/KR100951839B1/ko
Priority to PCT/EP2006/061012 priority patent/WO2006100301A1/fr
Priority to CN2006800092191A priority patent/CN101147253B/zh
Publication of FR2883659A1 publication Critical patent/FR2883659A1/fr
Application granted granted Critical
Publication of FR2883659B1 publication Critical patent/FR2883659B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
FR0502923A 2005-03-24 2005-03-24 Procede de fabrication d'une hetero-structure comportant au moins une couche epaisse de materiau semi-conducteur Active FR2883659B1 (fr)

Priority Applications (7)

Application Number Priority Date Filing Date Title
FR0502923A FR2883659B1 (fr) 2005-03-24 2005-03-24 Procede de fabrication d'une hetero-structure comportant au moins une couche epaisse de materiau semi-conducteur
US11/147,575 US7601611B2 (en) 2005-03-24 2005-06-07 Method of fabricating a semiconductor hetero-structure
EP06725289A EP1861873A1 (fr) 2005-03-24 2006-03-23 Procede de fabrication d'une hetero-structure comportant au moins une couche epaisse de materiau semi-conducteur
KR1020077020396A KR100951839B1 (ko) 2005-03-24 2006-03-23 적어도 하나의 두꺼운 반도체 물질층을 포함하는헤테로-구조 제조 방법
JP2008500217A JP5053252B2 (ja) 2005-03-24 2006-03-23 半導体材料の少なくとも１つの厚い層を含むヘテロ構造の製造方法
PCT/EP2006/061012 WO2006100301A1 (fr) 2005-03-24 2006-03-23 Procede de fabrication d'une hetero-structure comportant au moins une couche epaisse de materiau semi-conducteur
CN2006800092191A CN101147253B (zh) 2005-03-24 2006-03-23 包括至少一个厚半导体材料膜的异质结构的制作工艺

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0502923A FR2883659B1 (fr) 2005-03-24 2005-03-24 Procede de fabrication d'une hetero-structure comportant au moins une couche epaisse de materiau semi-conducteur

Publications (2)

Publication Number Publication Date
FR2883659A1 FR2883659A1 (fr) 2006-09-29
FR2883659B1 true FR2883659B1 (fr) 2007-06-22

Family

ID=34955095

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0502923A Active FR2883659B1 (fr) 2005-03-24 2005-03-24 Procede de fabrication d'une hetero-structure comportant au moins une couche epaisse de materiau semi-conducteur

Country Status (7)

Country Link
US (1) US7601611B2 (fr)
EP (1) EP1861873A1 (fr)
JP (1) JP5053252B2 (fr)
KR (1) KR100951839B1 (fr)
CN (1) CN101147253B (fr)
FR (1) FR2883659B1 (fr)
WO (1) WO2006100301A1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2977069B1 (fr) 2011-06-23 2014-02-07 Soitec Silicon On Insulator Procede de fabrication d'une structure semi-conductrice mettant en oeuvre un collage temporaire
FR3078822B1 (fr) * 2018-03-12 2020-02-28 Soitec Procede de preparation d’une couche mince de materiau ferroelectrique a base d’alcalin
FR3079531B1 (fr) * 2018-03-28 2022-03-18 Soitec Silicon On Insulator Procede de fabrication d'une couche monocristalline de materiau pzt et substrat pour croissance par epitaxie d'une couche monocristalline de materiau pzt

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2812405B2 (ja) * 1991-03-15 1998-10-22 信越半導体株式会社 半導体基板の製造方法
FR2777115B1 (fr) * 1998-04-07 2001-07-13 Commissariat Energie Atomique Procede de traitement de substrats semi-conducteurs et structures obtenues par ce procede
JP3358550B2 (ja) * 1998-07-07 2002-12-24 信越半導体株式会社 Ｓｏｉウエーハの製造方法ならびにこの方法で製造されるｓｏｉウエーハ
FR2835096B1 (fr) * 2002-01-22 2005-02-18 Procede de fabrication d'un substrat auto-porte en materiau semi-conducteur monocristallin
EP1482548B1 (fr) * 2003-05-26 2016-04-13 Soitec Procédé pour la fabrication de disques de semiconducteur
EP1542275A1 (fr) * 2003-12-10 2005-06-15 S.O.I.TEC. Silicon on Insulator Technologies S.A. Méthode d'amélioration de la qualité d'une structure hétérogène

Also Published As

Publication number Publication date
EP1861873A1 (fr) 2007-12-05
US7601611B2 (en) 2009-10-13
KR20070107111A (ko) 2007-11-06
US20060216907A1 (en) 2006-09-28
FR2883659A1 (fr) 2006-09-29
JP5053252B2 (ja) 2012-10-17
WO2006100301A1 (fr) 2006-09-28
KR100951839B1 (ko) 2010-04-12
JP2008532328A (ja) 2008-08-14
CN101147253B (zh) 2011-10-12
CN101147253A (zh) 2008-03-19

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