JP5372493B2 - デュアル歪みチャネル半導体デバイスを製造する方法 - Google Patents

デュアル歪みチャネル半導体デバイスを製造する方法 Download PDF

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Publication number
JP5372493B2
JP5372493B2 JP2008504047A JP2008504047A JP5372493B2 JP 5372493 B2 JP5372493 B2 JP 5372493B2 JP 2008504047 A JP2008504047 A JP 2008504047A JP 2008504047 A JP2008504047 A JP 2008504047A JP 5372493 B2 JP5372493 B2 JP 5372493B2
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layer
region
nmos
pmos
forming
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Expired - Fee Related
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Japanese (ja)
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JP2008535245A (ja
JP2008535245A5 (enExample
Inventor
ジー． サダカ、マリアム
エル． バール、アレクサンドル
ジョバノビッチ、デジャン
ニュエン、ビチ−エン
セアン、ブーン−ユウ
ジー． トーマス、ショーン
アール． ホワイト、テッド
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NXP USA Inc
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NXP USA Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0188—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
  • Thin Film Transistor (AREA)
JP2008504047A 2005-03-30 2006-02-16 デュアル歪みチャネル半導体デバイスを製造する方法 Expired - Fee Related JP5372493B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/093,801 US7282402B2 (en) 2005-03-30 2005-03-30 Method of making a dual strained channel semiconductor device
US11/093,801 2005-03-30
PCT/US2006/005471 WO2006107419A2 (en) 2005-03-30 2006-02-16 Method of making a dual strained channel semiconductor device

Publications (3)

Publication Number Publication Date
JP2008535245A JP2008535245A (ja) 2008-08-28
JP2008535245A5 JP2008535245A5 (enExample) 2009-04-09
JP5372493B2 true JP5372493B2 (ja) 2013-12-18

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JP2008504047A Expired - Fee Related JP5372493B2 (ja) 2005-03-30 2006-02-16 デュアル歪みチャネル半導体デバイスを製造する方法

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Country Link
US (1) US7282402B2 (enExample)
JP (1) JP5372493B2 (enExample)
TW (1) TWI389258B (enExample)
WO (1) WO2006107419A2 (enExample)

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US7282402B2 (en) 2007-10-16
JP2008535245A (ja) 2008-08-28
WO2006107419A2 (en) 2006-10-12
WO2006107419A3 (en) 2008-01-10
TW200711045A (en) 2007-03-16
US20060228851A1 (en) 2006-10-12
TWI389258B (zh) 2013-03-11

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