JP2008535245A5 - - Google Patents

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Publication number
JP2008535245A5
JP2008535245A5 JP2008504047A JP2008504047A JP2008535245A5 JP 2008535245 A5 JP2008535245 A5 JP 2008535245A5 JP 2008504047 A JP2008504047 A JP 2008504047A JP 2008504047 A JP2008504047 A JP 2008504047A JP 2008535245 A5 JP2008535245 A5 JP 2008535245A5
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Japan
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region
forming
channel region
insulator
nmos
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JP2008504047A
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Japanese (ja)
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JP5372493B2 (ja
JP2008535245A (ja
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Priority claimed from US11/093,801 external-priority patent/US7282402B2/en
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JP2008504047A 2005-03-30 2006-02-16 デュアル歪みチャネル半導体デバイスを製造する方法 Expired - Fee Related JP5372493B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/093,801 US7282402B2 (en) 2005-03-30 2005-03-30 Method of making a dual strained channel semiconductor device
US11/093,801 2005-03-30
PCT/US2006/005471 WO2006107419A2 (en) 2005-03-30 2006-02-16 Method of making a dual strained channel semiconductor device

Publications (3)

Publication Number Publication Date
JP2008535245A JP2008535245A (ja) 2008-08-28
JP2008535245A5 true JP2008535245A5 (enExample) 2009-04-09
JP5372493B2 JP5372493B2 (ja) 2013-12-18

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JP2008504047A Expired - Fee Related JP5372493B2 (ja) 2005-03-30 2006-02-16 デュアル歪みチャネル半導体デバイスを製造する方法

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US (1) US7282402B2 (enExample)
JP (1) JP5372493B2 (enExample)
TW (1) TWI389258B (enExample)
WO (1) WO2006107419A2 (enExample)

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