JP5348362B2 - 薄膜トランジスタ基板の製造方法 - Google Patents

薄膜トランジスタ基板の製造方法 Download PDF

Info

Publication number
JP5348362B2
JP5348362B2 JP2006183068A JP2006183068A JP5348362B2 JP 5348362 B2 JP5348362 B2 JP 5348362B2 JP 2006183068 A JP2006183068 A JP 2006183068A JP 2006183068 A JP2006183068 A JP 2006183068A JP 5348362 B2 JP5348362 B2 JP 5348362B2
Authority
JP
Japan
Prior art keywords
semiconductor layer
film
gate insulating
ion implantation
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2006183068A
Other languages
English (en)
Japanese (ja)
Other versions
JP2007053343A (ja
JP2007053343A5 (enExample
Inventor
慶 ミン 朴
春 基 柳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Display Co Ltd
Original Assignee
Samsung Display Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Display Co Ltd filed Critical Samsung Display Co Ltd
Publication of JP2007053343A publication Critical patent/JP2007053343A/ja
Publication of JP2007053343A5 publication Critical patent/JP2007053343A5/ja
Application granted granted Critical
Publication of JP5348362B2 publication Critical patent/JP5348362B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/431—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having different compositions, shapes, layouts or thicknesses of gate insulators in different TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP2006183068A 2005-08-13 2006-07-03 薄膜トランジスタ基板の製造方法 Active JP5348362B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020050074582A KR101239889B1 (ko) 2005-08-13 2005-08-13 박막 트랜지스터 기판 및 그 제조 방법
KR10-2005-0074582 2005-08-13

Publications (3)

Publication Number Publication Date
JP2007053343A JP2007053343A (ja) 2007-03-01
JP2007053343A5 JP2007053343A5 (enExample) 2009-08-20
JP5348362B2 true JP5348362B2 (ja) 2013-11-20

Family

ID=37722024

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006183068A Active JP5348362B2 (ja) 2005-08-13 2006-07-03 薄膜トランジスタ基板の製造方法

Country Status (4)

Country Link
US (2) US7682881B2 (enExample)
JP (1) JP5348362B2 (enExample)
KR (1) KR101239889B1 (enExample)
CN (1) CN1913163B (enExample)

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101267499B1 (ko) * 2005-08-18 2013-05-31 삼성디스플레이 주식회사 박막 트랜지스터 기판의 제조 방법 및 그에 의해 제조된박막 트랜지스터
JP5005302B2 (ja) * 2006-09-19 2012-08-22 株式会社ジャパンディスプレイイースト 表示装置の製造方法
KR100917654B1 (ko) * 2006-11-10 2009-09-17 베이징 보에 옵토일렉트로닉스 테크놀로지 컴퍼니 리미티드 박막트랜지스터 액정 디스플레이 화소 구조 및 그 제조방법
KR101576813B1 (ko) * 2007-08-17 2015-12-11 가부시키가이샤 한도오따이 에네루기 켄큐쇼 표시 장치
KR101836067B1 (ko) * 2009-12-21 2018-03-08 가부시키가이샤 한도오따이 에네루기 켄큐쇼 박막 트랜지스터와 그 제작 방법
TWI535028B (zh) * 2009-12-21 2016-05-21 半導體能源研究所股份有限公司 薄膜電晶體
US8476744B2 (en) 2009-12-28 2013-07-02 Semiconductor Energy Laboratory Co., Ltd. Thin film transistor with channel including microcrystalline and amorphous semiconductor regions
JP5948025B2 (ja) 2010-08-06 2016-07-06 株式会社半導体エネルギー研究所 液晶表示装置
US9230826B2 (en) 2010-08-26 2016-01-05 Semiconductor Energy Laboratory Co., Ltd. Etching method using mixed gas and method for manufacturing semiconductor device
US8704230B2 (en) 2010-08-26 2014-04-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
WO2012153498A1 (ja) * 2011-05-09 2012-11-15 シャープ株式会社 半導体装置の製造方法
WO2012160800A1 (ja) 2011-05-24 2012-11-29 シャープ株式会社 半導体装置の製造方法
KR101185165B1 (ko) 2011-05-30 2012-09-24 순천대학교 산학협력단 산화물 박막 트랜지스터 및 그 제조방법
CN202549848U (zh) 2012-04-28 2012-11-21 京东方科技集团股份有限公司 显示装置、阵列基板和薄膜晶体管
TW201413825A (zh) * 2012-09-17 2014-04-01 Ying-Jia Xue 薄膜電晶體的製作方法
CN102856260B (zh) * 2012-09-26 2015-08-19 京东方科技集团股份有限公司 一种cmos晶体管及其制造方法
US9279983B1 (en) * 2012-10-30 2016-03-08 Google Inc. Image cropping
CN103258827B (zh) * 2013-04-28 2016-03-23 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
KR20150000215A (ko) * 2013-06-24 2015-01-02 삼성디스플레이 주식회사 표시 장치 및 그 제조 방법
KR102091664B1 (ko) * 2013-09-27 2020-03-23 삼성디스플레이 주식회사 유기 발광 표시 장치 및 이의 제조방법
CN104103584A (zh) * 2014-06-25 2014-10-15 京东方科技集团股份有限公司 阵列基板制作方法
CN104465405B (zh) * 2014-12-30 2017-09-22 京东方科技集团股份有限公司 薄膜晶体管的制作方法及阵列基板的制作方法
CN104716092B (zh) * 2015-04-02 2017-11-10 京东方科技集团股份有限公司 阵列基板的制造方法及制造装置
CN105140124B (zh) * 2015-07-29 2018-12-11 武汉华星光电技术有限公司 一种多晶硅薄膜晶体管的制作方法
KR20170080996A (ko) * 2015-12-31 2017-07-11 삼성디스플레이 주식회사 표시 장치용 박막 트랜지스터 및 이를 포함하는 유기 발광 표시 장치
CN105514119A (zh) * 2016-01-04 2016-04-20 武汉华星光电技术有限公司 Tft基板的制作方法及tft基板
KR102568776B1 (ko) * 2016-03-28 2023-08-22 삼성디스플레이 주식회사 유기 발광 표시 장치
KR102586938B1 (ko) 2016-09-05 2023-10-10 삼성디스플레이 주식회사 박막 트랜지스터 표시판 및 그 제조 방법
CN106531690B (zh) * 2016-12-19 2020-03-10 武汉新芯集成电路制造有限公司 一种轻掺杂漏区的形成方法
CN106910712B (zh) * 2017-03-03 2019-09-24 厦门天马微电子有限公司 阵列基板的制作方法
CN107464836B (zh) * 2017-07-19 2020-04-10 深圳市华星光电半导体显示技术有限公司 一种顶栅型薄膜晶体管的制作方法及顶栅型薄膜晶体管
US10957713B2 (en) * 2018-04-19 2021-03-23 Wuhan China Star Optoelectronics Technology Co., Ltd. LTPS TFT substrate and manufacturing method thereof
CN108565247B (zh) * 2018-04-19 2020-09-29 武汉华星光电技术有限公司 Ltps tft基板的制作方法及ltps tft基板
CN108511464B (zh) * 2018-04-20 2020-07-28 武汉华星光电技术有限公司 Cmos型ltps tft基板的制作方法
WO2020177057A1 (zh) * 2019-03-04 2020-09-10 京东方科技集团股份有限公司 Cmos结构及cmos结构的制造方法
CN114267684B (zh) * 2020-09-25 2025-04-29 武汉天马微电子有限公司 薄膜晶体管基板及薄膜晶体管基板的制造方法
CN112542516B (zh) * 2020-11-03 2024-01-30 北海惠科光电技术有限公司 一种主动开关及其制作方法和显示面板
JP7623864B2 (ja) 2021-03-22 2025-01-29 武漢天馬微電子有限公司 薄膜トランジスタ基板
US11798983B2 (en) 2021-07-19 2023-10-24 United Semiconductor Japan Co., Ltd. Semiconductor device with deeply depleted channel and manufacturing method thereof

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07131018A (ja) * 1993-06-23 1995-05-19 Sanyo Electric Co Ltd 薄膜トランジスタ及びその製造方法
JPH09252136A (ja) * 1996-03-15 1997-09-22 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法とアクティブマトリックスアレイ基板およびそれを用いた液晶表示装置
JP2002217419A (ja) * 2001-01-23 2002-08-02 Hitachi Ltd 薄膜トランジスタ基板とその製法
JP2002016261A (ja) 2001-05-07 2002-01-18 Seiko Epson Corp 相補性薄膜半導体装置の製造方法
JP4439766B2 (ja) * 2001-08-02 2010-03-24 シャープ株式会社 薄膜トランジスタ装置及びその製造方法
KR100815894B1 (ko) * 2001-09-21 2008-03-21 엘지.필립스 엘시디 주식회사 Ｌｄｄ구조의 ｃｍｏｓ 다결정 실리콘 박막트랜지스터의제조방법
JP3626734B2 (ja) * 2002-03-11 2005-03-09 日本電気株式会社 薄膜半導体装置
JP2003282880A (ja) 2002-03-22 2003-10-03 Hitachi Displays Ltd 表示装置
TW544941B (en) * 2002-07-08 2003-08-01 Toppoly Optoelectronics Corp Manufacturing process and structure of thin film transistor
KR20040060501A (ko) 2002-12-30 2004-07-06 엘지.필립스 엘시디 주식회사 액정표시장치용 박막 트랜지스터의 제조방법
US20050074914A1 (en) * 2003-10-06 2005-04-07 Toppoly Optoelectronics Corp. Semiconductor device and method of fabrication the same
KR101018752B1 (ko) * 2003-12-19 2011-03-04 삼성전자주식회사 박막 트랜지스터 표시판 및 그의 제조 방법
TWI401802B (zh) * 2005-06-30 2013-07-11 Samsung Display Co Ltd 薄膜電晶體板及其製造方法
US7592628B2 (en) * 2006-07-21 2009-09-22 Tpo Displays Corp. Display with thin film transistor devices having different electrical characteristics in pixel and driving regions

Also Published As

Publication number Publication date
KR20070019914A (ko) 2007-02-16
US8253202B2 (en) 2012-08-28
US7682881B2 (en) 2010-03-23
US20070045627A1 (en) 2007-03-01
JP2007053343A (ja) 2007-03-01
CN1913163B (zh) 2010-06-16
US20100127329A1 (en) 2010-05-27
KR101239889B1 (ko) 2013-03-06
CN1913163A (zh) 2007-02-14

Similar Documents

Publication Publication Date Title
JP5348362B2 (ja) 薄膜トランジスタ基板の製造方法
KR101267499B1 (ko) 박막 트랜지스터 기판의 제조 방법 및 그에 의해 제조된박막 트랜지스터
KR100234892B1 (ko) 액정표시장치의 구조 및 그 제조방법
JP5138276B2 (ja) 表示装置の製造方法
JP5144903B2 (ja) 薄膜トランジスタ基板の製造方法
CN1222039C (zh) 互补金属氧化物半导体薄膜晶体管及其制造方法
US20100197059A1 (en) Array substrate for liquid crystal display device and method of fabricating the same
KR20030081992A (ko) 다결정 실리콘 박막트랜지스터와 그 제조방법
JP4377355B2 (ja) 半導体素子の製造方法
JP5111802B2 (ja) 薄膜トランジスタ基板、及びその製造方法
JP2001085695A (ja) 半導体装置の製造方法、アクティブマトリクス基板の製造方法および電気光学装置
JP2005150736A (ja) 薄膜トランジスタ表示板及びその製造方法
JP4669834B2 (ja) 液晶表示装置の製造方法
KR101188868B1 (ko) 박막 트랜지스터 기판 및 그 제조 방법
JP2006093714A (ja) 薄膜トランジスタ表示板及びその製造方法
JP2009200528A (ja) 薄膜トランジスタ装置及びその製造方法
KR101172015B1 (ko) 박막 트랜지스터 기판 및 그 제조 방법
JP2006259241A (ja) 電気光学装置の製造方法
KR20090050445A (ko) 액정표시장치의 제조방법

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090703

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20090703

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100624

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120605

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20120606

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120905

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20121213

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130312

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130326

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20130723

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20130806

R150 Certificate of patent or registration of utility model

Ref document number: 5348362

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250