JP5299678B2 - ピッチ増倍コンタクトを形成する方法 - Google Patents
ピッチ増倍コンタクトを形成する方法 Download PDFInfo
- Publication number
- JP5299678B2 JP5299678B2 JP2008529144A JP2008529144A JP5299678B2 JP 5299678 B2 JP5299678 B2 JP 5299678B2 JP 2008529144 A JP2008529144 A JP 2008529144A JP 2008529144 A JP2008529144 A JP 2008529144A JP 5299678 B2 JP5299678 B2 JP 5299678B2
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- spacer
- pitch
- layer
- contact
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 98
- 238000000206 photolithography Methods 0.000 claims abstract description 46
- 238000005530 etching Methods 0.000 claims abstract description 42
- 230000002829 reductive effect Effects 0.000 claims abstract description 20
- 125000006850 spacer group Chemical group 0.000 claims description 140
- 239000000463 material Substances 0.000 claims description 115
- 229920002120 photoresistant polymer Polymers 0.000 claims description 45
- 230000009467 reduction Effects 0.000 claims description 28
- 230000000873 masking effect Effects 0.000 claims description 27
- 239000011810 insulating material Substances 0.000 claims description 20
- 239000004020 conductor Substances 0.000 claims description 15
- 238000011049 filling Methods 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 239000006117 anti-reflective coating Substances 0.000 claims description 6
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 5
- 229910052799 carbon Inorganic materials 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 238000012546 transfer Methods 0.000 abstract description 19
- 239000010410 layer Substances 0.000 description 213
- 239000011295 pitch Substances 0.000 description 98
- 239000000758 substrate Substances 0.000 description 30
- 229910052751 metal Inorganic materials 0.000 description 10
- 239000002184 metal Substances 0.000 description 10
- 238000003491 array Methods 0.000 description 6
- 238000000151 deposition Methods 0.000 description 6
- 238000001459 lithography Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 230000004048 modification Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 238000000059 patterning Methods 0.000 description 5
- 239000011800 void material Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical class O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 239000000470 constituent Substances 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 239000002131 composite material Substances 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 230000005855 radiation Effects 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- KAKZBPTYRLMSJV-UHFFFAOYSA-N Butadiene Chemical compound C=CC=C KAKZBPTYRLMSJV-UHFFFAOYSA-N 0.000 description 2
- ATUOYWHBWRKTHZ-UHFFFAOYSA-N Propane Chemical compound CCC ATUOYWHBWRKTHZ-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000012993 chemical processing Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000018109 developmental process Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 2
- 238000009472 formulation Methods 0.000 description 2
- 230000003993 interaction Effects 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000002243 precursor Substances 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000005549 size reduction Methods 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 239000004215 Carbon black (E152) Substances 0.000 description 1
- 206010073306 Exposure to radiation Diseases 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- VZPPHXVFMVZRTE-UHFFFAOYSA-N [Kr]F Chemical compound [Kr]F VZPPHXVFMVZRTE-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- HSFWRNGVRCDJHI-UHFFFAOYSA-N alpha-acetylene Natural products C#C HSFWRNGVRCDJHI-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- ISQINHMJILFLAQ-UHFFFAOYSA-N argon hydrofluoride Chemical compound F.[Ar] ISQINHMJILFLAQ-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 239000001273 butane Substances 0.000 description 1
- 239000003575 carbonaceous material Substances 0.000 description 1
- 229910052729 chemical element Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000011231 conductive filler Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000001186 cumulative effect Effects 0.000 description 1
- 230000007850 degeneration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- TXKMVPPZCYKFAC-UHFFFAOYSA-N disulfur monoxide Inorganic materials O=S=S TXKMVPPZCYKFAC-UHFFFAOYSA-N 0.000 description 1
- 238000000609 electron-beam lithography Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 125000002534 ethynyl group Chemical group [H]C#C* 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 229930195733 hydrocarbon Natural products 0.000 description 1
- 150000002430 hydrocarbons Chemical class 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- IJDNQMDRQITEOD-UHFFFAOYSA-N n-butane Chemical compound CCCC IJDNQMDRQITEOD-UHFFFAOYSA-N 0.000 description 1
- OFBQJSOFQDEBGM-UHFFFAOYSA-N n-pentane Natural products CCCCC OFBQJSOFQDEBGM-UHFFFAOYSA-N 0.000 description 1
- 238000001127 nanoimprint lithography Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000000379 polymerizing effect Effects 0.000 description 1
- 239000001294 propane Substances 0.000 description 1
- QQONPFPTGQHPMA-UHFFFAOYSA-N propylene Natural products CC=C QQONPFPTGQHPMA-UHFFFAOYSA-N 0.000 description 1
- 125000004805 propylene group Chemical group [H]C([H])([H])C([H])([*:1])C([H])([H])[*:2] 0.000 description 1
- MWWATHDPGQKSAR-UHFFFAOYSA-N propyne Chemical compound CC#C MWWATHDPGQKSAR-UHFFFAOYSA-N 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- 239000011593 sulfur Substances 0.000 description 1
- XTQHKBHJIVJGKJ-UHFFFAOYSA-N sulfur monoxide Chemical compound S=O XTQHKBHJIVJGKJ-UHFFFAOYSA-N 0.000 description 1
- 125000000383 tetramethylene group Chemical group [H]C([H])([*:1])C([H])([H])C([H])([H])C([H])([H])[*:2] 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3088—Process specially adapted to improve the resolution of the mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Non-Volatile Memory (AREA)
Description
より高密度に配置されたフィーチャの作製を可能にすることができる。このような方法が図1A〜1Fに示されており、Lowreyらの米国特許第5328810号に記載されている。同文献の開示全体を参照により本明細書に組み込み、本明細書の一部とする。便宜上、その方法もまたここで簡単に概説する。
ができなかった。したがって、コンタクトフィーチャによって接続されるように意図されたフィーチャの密度に適合することが可能である、特に接続されるべきフィーチャを形成するためにピッチ増倍が用いられた場合に可能である、寸法が縮小されたコンタクトを形成する方法が必要とされている。
料を層状に積み重ねて絶縁層を形成すること、この絶縁層の上にある一時的な層、および一時的な層の上にある選択的に画定可能な第1の層を含むことができる。これらの層内に、選択的に画定可能な第1の層内の第1のパターンに対応するフィーチャを形成することができる。第1のパターンを一時的な層に転写することができ、一時的な層内のフィーチャの側壁上にスペーサを形成することができる。一時的な層のフィーチャを除去し、第2のパターンに対応するスペーサを後に残すことができる。さらに、このスペーサの上に選択的に画定可能な第2の層を付けることができ、この選択的に画定可能な第2の層内に、第3のパターンに対応するフィーチャを形成することができる。次に、第2および第3のパターン内の空所によって露出した下の層中に孔をエッチングすることができる。孔形成の後、導電材料が回路フィーチャを形成するように孔の中に導電材料を挿入することができ、各フィーチャは、第2のパターンの分解能によって決まる幅と、第3のパターンの分解能によって決まる長さとを有する。
ィーチャ222は、たとえば上記の米国特許出願第11/010752号、第10/934621号、および第10/933062号に開示されているように、ピッチ増倍法を用いて形成することができ、このピッチ増倍法は、ハード・マスク・スペーサを使用してフィーチャ密度を増大し、限界寸法を低減させる。
となったフィーチャと正確に似ていないとしても、別のパターンから得られると言われることがある。
要素(ビット線、または線242など)から分離するために使用される。ILDを貫通して延びるコンタクトが形成されて、下にある特定のフィーチャが上にある特定の導電要素と接続される。「レベル間誘電体」という用語は、ILD自体がレベルではなく、2つの導電レベルの間にあるだけということを暗示する可能性がある。しかし便宜上、本開示では、中間レベル230を「レベル」と呼ぶ。
したがって、図示のように、ピッチ増倍されていない一連のコンタクト232は、下にある1つおきのピッチ増倍フィーチャとだけ接触することができる。
板110の上にある。任意選択で、基板110がそれを介して処理されるマスクは、第2のハード・マスク層150内に形成される。図示の実施形態では、基板110は、コンタクトがそれによって形成される上部のレベル間誘電体(ILD)層を含み、さらに上部のエッチ・ストップ層または化学的機械的研磨(CMP)ストップ層を含むこともできる。しかし図示の実施形態では、ハード・マスク150は、導電充填材のエッチ・バック中にCMPストップとして働くことができる。
用して適用されてよい。
モルファス・カーボン層の化学的または物理的分裂を防止する。スピン・オン・コーティング法を用いて光画定可能層を形成することができる。さらに、アモルファス・カーボン層は、前駆物質として炭化水素複合物、またはこのような複合物の混合物を使用する化学気相成長によって形成することができる。例示的な前駆物質には、プロピレン、プロピン、プロパン、ブタン、ブチレン、ブタジエン、およびアセチレンが含まれる。アモルファス・カーボン層を形成する適切な方法は、2003年6月3日発行のFairbaimらの米国特許第6573030B1号に記載されている。同文献の開示全体を参照により本明細書に組み込み、本明細書の一部とする。加えて、アモルファス・カーボンをドープすることもできる。ドープ・アモルファス・カーボンを形成する適切な方法は、Yinらの米国特許出願第10/652174号に記載されている。同文献の開示全体を参照により本明細書に組み込み、本明細書の一部とする。
させる。したがって線124aの角部は実際には、図6に概略的に示されたよりも鋭さが少なく、良好に画定されうる。エッチングの程度は、以下の図9〜11についての議論から理解されるように、好ましくは線124aの幅が、後で形成されるスペーサ175の間の望ましい間隔とほぼ等しくなるように選択される。有利なことにこのエッチングは、線124aが、光画定可能層120をパターニングするために用いられるフォトリソグラフィ技術による別の方法で可能な線よりも狭くなることを可能にする。加えて、このエッチングは、線124aの縁部を平滑にし、それによってこれらの線の均一性を改善することができる。いくつかの実施形態では、線124を所望のサイズまで拡大することによって、線124aの間の空所を狭くすることができる。たとえば、追加の材料を線124の上に堆積させて、あるいはより大きい体積の材料を形成するように線124に化学反応を起こさせて、線124のサイズを増大させることができる。
名称のAbatchevらの米国特許出願第10/931772号(代理人整理番号MICRON.286A、Micron参照番号2003−1348)に記載されている。同文献の全体を参照により本明細書に組み込み、本明細書の一部とする。このSO2含有プラズマは同時に、一時的な層140をエッチングすることができ、残っている画定可能層120aを除去することもできる。その結果得られた線124bは、スペーサ175のパターン(図10)がそれに沿って形成されるプレースホルダすなわちマンドレルを構成する。
いるが、図14Aでは、第2のマスク480およびスペーサ175が単一の面での断面としては示されていない。(図14B参照。)第2のマスク480は、以下に説明する一連のコンタクトビアを画定するのに使用できる窓482を画定する。しかし、いくつかの実施形態では、細長いスペーサが好ましくはアレイの長さを伸長する。さらに、いくつかの実施形態では、窓482などの窓が、メモリ・アレイの長手方向に沿って数回繰り返すことができる。以下で論じる図には一列のコンタクトだけが示されているが、開示の実施形態による第2のマスクは、好ましくは、アレイ全体の複数列のコンタクトビアを同時にエッチングするための複数の窓を含む。
平坦化材料はスペーサの間の空所を充填して、スペーサの上部を覆う平坦な表面を生成することができる。次に、このハード・マスク(図示せず)は、その上面に生成された第2のマスク480とパターンが同じであるマスクを有することができる。ハード・マスク層が生成される場合には、ハード・マスク材料を除去するために追加のエッチング・ステップがその時になれば必要になる。したがって、図14Aのパターンは、示されたように、選択的に画定可能な層480を用いて直接作製することができ、あるいは第2のマスク・パターンを介在ハード・マスク層に転写して図14Aのパターンを実現することもできる。
い溝または空洞を形成する。この溝は、今では除去されている細長いスペーサのパターンに対して概して平行な次元に延びている。この溝は、従来のリソグラフィを用いてその寸法を画定したので、寸法が長い。各溝の底部にフィーチャ322があり、これはビア584が充填される前には、対応するビア584によって露出している。
Claims (28)
- 集積回路を作製する方法であって、
第1レベルにおいて導電フィーチャを形成することが、
複数のマンドレルを提供するステップと、
前記マンドレルの側面にスペーサの第1セットを形成するステップと、
前記スペーサの第1セットに対して選択的に前記マンドレルを除去するステップと、
前記スペーサの第1セットで画定されるパターンを下層材料に転写し、前記下層材料に複数の開口を形成するステップと、
前記開口を導電材料で充填することにより、前記導電材料が前記導電フィーチャを構成するステップと、
を含み、
前記第1レベルに配置される前記導電フィーチャに接続される複数のコンタクトを第2レベルにおいて形成することが、
フォトリソグラフィを用いて、前記複数のマンドレルとは異なる複数のマンドレルを構成する、あるピッチを有する複数の線をマスク材料中に形成するステップと、
前記複数の線の上にスペーサ材料を付けるステップと、
スペーサ・エッチングを実施して、前記複数の線と比べて縮小されたピッチを有し、スペーサ軸に沿って延びるスペーサの第2セットのパターンを生成するステップと、
前記スペーサの第2セットのパターンに、非ピッチ縮小フォトリソグラフィによって開口を有するマスク・パターンを付けるステップであって、前記開口が前記長いスペーサ軸と交差する長軸を有する、ステップと、
前記マスク・パターンまたは前記スペーサの第2セットのパターンのどちらによってもマスクされていない下にある層の一部分をエッチング除去して、前記下にある層内に溝を生成するステップと、
前記溝を導電材料で充填して前記導電フィーチャを生成するステップと、
前記マスキング材料およびスペーサ材料を選択的に除去するステップと、
1つの次元で縮小ピッチを有すると共に、前記非ピッチ縮小フォトリソグラフィによって画定可能な別の次元を有する複数の前記コンタクトを形成するステップと、
を含む、方法。 - エッチング除去するステップが、前記スペーサ軸に対して概して平行な次元で前記溝を長くするステップを含み、それに応じて前記導電フィーチャが、前記スペーサ軸に対して平行な軸に沿って長い、請求項1に記載の方法。
- フォトリソグラフィを用いて前記マスク材料中に前記複数の線を形成するステップが、
複数の第1の線をフォトレジスト内に形成するステップと、
前記複数の第1の線からなるパターンを前記マスク材料中に転写するステップとを含む、請求項1に記載の方法。 - 前記溝を充填するステップが、メモリ・アレイ内のビット線コンタクトを画定するステップを含む、請求項1に記載の方法。
- 前記溝を充填するステップが、NANDフラッシュ・メモリ内のコンタクトを画定するステップを含む、請求項1に記載の方法。
- フォトリソグラフィを用いるステップが、フォトレジスト内にパターンを画定するステップと、ハード・マスクを構成する前記マスク材料に前記パターンを転写するステップとを含む、請求項1に記載の方法。
- フォトリソグラフィを用いるステップが、フォトレジスト内にパターンを画定するステップと、誘電体反射防止膜を含む前記ハード・マスクに前記パターンを転写するステップとを含む、請求項6に記載の方法。
- フォトリソグラフィを用いるステップが、フォトレジスト内にパターンを画定するステップと、シリコンリッチのシリコン酸窒化物を含む前記ハード・マスクに前記パターンを転写するステップとを含む、請求項6に記載の方法。
- フォトリソグラフィを用いるステップが、フォトレジスト内にパターンを画定するステップと、アモルファス・カーボンを含む前記マスク材料に前記パターンを転写するステップとを含む、請求項1に記載の方法。
- 前記スペーサの第2セットのパターンに付けるステップが、複数の開口を有する前記フォトリソグラフィ・マスク・パターンを設けるステップを含み、それによって多数の列の溝を形成する、請求項1に記載の方法。
- 前記スペーサ材料を付ける前に前記複数の線を改変するステップをさらに含む、請求項1に記載の方法。
- 一部分をエッチング除去するステップが、溝のパターンを前記下層に転写する前にカーボン層の一部分をエッチング除去するステップを含む、請求項9に記載の方法。
- 前記溝のパターンを前記下層に転写するステップが、絶縁材料に転写するステップを含む、請求項12に記載の方法。
- 前記スペーサの第2セットのパターンに付けるステップが、前記開口の長軸に沿って少なくとも200nmの長さを有する前記開口を設けるステップを含む、請求項1に記載の方法。
- 前記溝を充填するステップが、前記導電フィーチャをメモリ・アレイ内のビット線コンタクトとして形成するステップを含む、請求項1に記載の方法。
- 前記溝を充填するステップが、前記導電フィーチャを、NANDフラッシュ・メモリ内で使用するために構成された電気コンタクトとして形成するステップを含む、請求項1に記載の方法。
- 前記溝を充填するステップが、前記導電フィーチャをメモリ・アレイ内部に形成される電気コンタクトとして形成するステップを含む、請求項1に記載の方法。
- 一部分をエッチング除去するステップが、前記スペーサの第2セットのパターンに重なる前記フォトリソグラフィ・マスク・パターンからフォトレジストを除去するステップを含む、請求項1に記載の方法。
- 前記溝を充填するステップが、70ナノメートル未満の限界寸法を有する前記導電フィーチャを形成するステップを含む、請求項1に記載の方法。
- 前記集積回路は、
一連のトランジスタと、
前記トランジスタの上にある一連のビット線と、を具備したコンピュータ・メモリ・アレイを含み、
前記レベル間コンタクトは、前記トランジスタと前記ビット線の間に配置される、請求項1に記載の方法。 - 前記ビット線が約70ナノメートル未満の限界寸法を有する、請求項20に記載の方法。
- 前記コンタクトが約70ナノメートルの限界寸法を有する、請求項20に記載の方法。
- 前記コンタクトが、前記トランジスタの限界寸法とほぼ同じ限界寸法を有する、請求項20に記載の方法。
- 前記コンタクトが、前記ビット線の限界寸法とほぼ同じ限界寸法を有する、請求項20に記載の方法。
- 前記コンタクトが、複数の位置合わせされた列をなすコンタクトを含む、請求項20に記載の方法。
- あるピッチ幅を有する多数のトランジスタと、
あるピッチ幅を有する、上にある多数のディジット線と、
前記トランジスタと前記ディジット線の間に垂直に延びる多数の電気コンタクトと、を含む集積回路を作製する方法であって、
第1レベルにおいてトランジスタを形成することであって、前記トランジスタを形成することは、
複数のマンドレルを提供するステップと、
前記マンドレルの側面にスペーサの第1セットを形成するステップと、
前記スペーサの第1セットに対して選択的に前記マンドレルを除去するステップと、
前記スペーサの第1セットで画定されるパターンを下層材料に転写し、前記下層材料に複数の開口を形成するステップと、
前記開口を導電材料で充填することにより、前記導電材料が前記トランジスタの一部を構成するステップと、
を含み、
前記第1レベルに配置される前記トランジスタに接続される複数の電気コンタクトを第2レベルにおいて形成することであって、前記電気コンタクトを形成することは、
フォトリソグラフィを用いて、前記複数のマンドレルとは異なる複数のマンドレルを構成する、あるピッチを有する複数の線をマスク材料中に形成するステップと、
前記複数の線の上にスペーサ材料を付けるステップと、
スペーサ・エッチングを実施して、前記複数の線と比べて縮小されたピッチを有し、スペーサ軸に沿って延びるスペーサのパターンを生成するステップと、
前記スペーサのパターンに、非ピッチ縮小フォトリソグラフィによって開口を有するマスク・パターンを付けるステップであって、前記開口が前記長いスペーサ軸と交差する長軸を有する、ステップと、
前記マスク・パターンまたは前記スペーサのパターンのどちらによってもマスクされていない下にある層の一部分をエッチング除去して、前記下にある層内に溝を生成するステップと、
前記溝を導電材料で充填して前記導電フィーチャを生成するステップと、
前記マスキング材料およびスペーサ材料を選択的に除去するステップと、
1つの次元で縮小ピッチを有すると共に、前記非ピッチ縮小フォトリソグラフィによって画定可能な別の次元を有する前記電気コンタクトとしての前記導電フィーチャを形成し、前記電気コンタクトの前記縮小ピッチが前記トランジスタおよびディジット線のピッチ幅に近いピッチ幅を有するステップと、
を含む、方法。 - 前記電気コンタクトが、ピッチ縮小された1つの次元と、ピッチ縮小されていない1つの次元とを有する、請求項26に記載の方法。
- 前記電気コンタクトが多数の列として配置される、請求項26に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/215,982 US7829262B2 (en) | 2005-08-31 | 2005-08-31 | Method of forming pitch multipled contacts |
US11/215,982 | 2005-08-31 | ||
PCT/US2006/033421 WO2007027558A2 (en) | 2005-08-31 | 2006-08-28 | Method of forming pitch multipled contacts |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009506576A JP2009506576A (ja) | 2009-02-12 |
JP5299678B2 true JP5299678B2 (ja) | 2013-09-25 |
Family
ID=37628492
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008529144A Active JP5299678B2 (ja) | 2005-08-31 | 2006-08-28 | ピッチ増倍コンタクトを形成する方法 |
Country Status (7)
Country | Link |
---|---|
US (3) | US7829262B2 (ja) |
EP (1) | EP1929508A2 (ja) |
JP (1) | JP5299678B2 (ja) |
KR (2) | KR20100109985A (ja) |
CN (1) | CN101292327B (ja) |
TW (1) | TWI327746B (ja) |
WO (1) | WO2007027558A2 (ja) |
Families Citing this family (117)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8486287B2 (en) * | 2004-03-19 | 2013-07-16 | The Regents Of The University Of California | Methods for fabrication of positional and compositionally controlled nanostructures on substrate |
US7151040B2 (en) * | 2004-08-31 | 2006-12-19 | Micron Technology, Inc. | Methods for increasing photo alignment margins |
US7910288B2 (en) | 2004-09-01 | 2011-03-22 | Micron Technology, Inc. | Mask material conversion |
US7115525B2 (en) * | 2004-09-02 | 2006-10-03 | Micron Technology, Inc. | Method for integrated circuit fabrication using pitch multiplication |
US7655387B2 (en) * | 2004-09-02 | 2010-02-02 | Micron Technology, Inc. | Method to align mask patterns |
US7390746B2 (en) * | 2005-03-15 | 2008-06-24 | Micron Technology, Inc. | Multiple deposition for integration of spacers in pitch multiplication process |
US7253118B2 (en) * | 2005-03-15 | 2007-08-07 | Micron Technology, Inc. | Pitch reduced patterns relative to photolithography features |
US7611944B2 (en) | 2005-03-28 | 2009-11-03 | Micron Technology, Inc. | Integrated circuit fabrication |
KR100833201B1 (ko) * | 2007-06-15 | 2008-05-28 | 삼성전자주식회사 | 콘택 플러그 및 배선 라인 일체형 구조의 미세 패턴을가지는 반도체 소자 및 그 제조 방법 |
US7429536B2 (en) | 2005-05-23 | 2008-09-30 | Micron Technology, Inc. | Methods for forming arrays of small, closely spaced features |
US7560390B2 (en) * | 2005-06-02 | 2009-07-14 | Micron Technology, Inc. | Multiple spacer steps for pitch multiplication |
US7396781B2 (en) * | 2005-06-09 | 2008-07-08 | Micron Technology, Inc. | Method and apparatus for adjusting feature size and position |
US7888721B2 (en) | 2005-07-06 | 2011-02-15 | Micron Technology, Inc. | Surround gate access transistors with grown ultra-thin bodies |
US7768051B2 (en) | 2005-07-25 | 2010-08-03 | Micron Technology, Inc. | DRAM including a vertical surround gate transistor |
US7413981B2 (en) | 2005-07-29 | 2008-08-19 | Micron Technology, Inc. | Pitch doubled circuit layout |
US8123968B2 (en) * | 2005-08-25 | 2012-02-28 | Round Rock Research, Llc | Multiple deposition for integration of spacers in pitch multiplication process |
US7816262B2 (en) * | 2005-08-30 | 2010-10-19 | Micron Technology, Inc. | Method and algorithm for random half pitched interconnect layout with constant spacing |
US7696567B2 (en) * | 2005-08-31 | 2010-04-13 | Micron Technology, Inc | Semiconductor memory device |
US7829262B2 (en) * | 2005-08-31 | 2010-11-09 | Micron Technology, Inc. | Method of forming pitch multipled contacts |
US7687342B2 (en) * | 2005-09-01 | 2010-03-30 | Micron Technology, Inc. | Method of manufacturing a memory device |
US7557032B2 (en) * | 2005-09-01 | 2009-07-07 | Micron Technology, Inc. | Silicided recessed silicon |
US7416943B2 (en) * | 2005-09-01 | 2008-08-26 | Micron Technology, Inc. | Peripheral gate stacks and recessed array gates |
US7393789B2 (en) | 2005-09-01 | 2008-07-01 | Micron Technology, Inc. | Protective coating for planarization |
US7759197B2 (en) * | 2005-09-01 | 2010-07-20 | Micron Technology, Inc. | Method of forming isolated features using pitch multiplication |
US7776744B2 (en) * | 2005-09-01 | 2010-08-17 | Micron Technology, Inc. | Pitch multiplication spacers and methods of forming the same |
US7572572B2 (en) * | 2005-09-01 | 2009-08-11 | Micron Technology, Inc. | Methods for forming arrays of small, closely spaced features |
US7476933B2 (en) | 2006-03-02 | 2009-01-13 | Micron Technology, Inc. | Vertical gated access transistor |
US7842558B2 (en) * | 2006-03-02 | 2010-11-30 | Micron Technology, Inc. | Masking process for simultaneously patterning separate regions |
JP2007266491A (ja) * | 2006-03-29 | 2007-10-11 | Fujitsu Ltd | 半導体装置の製造方法及び半導体装置 |
US7902074B2 (en) | 2006-04-07 | 2011-03-08 | Micron Technology, Inc. | Simplified pitch doubling process flow |
US8003310B2 (en) * | 2006-04-24 | 2011-08-23 | Micron Technology, Inc. | Masking techniques and templates for dense semiconductor fabrication |
US7488685B2 (en) * | 2006-04-25 | 2009-02-10 | Micron Technology, Inc. | Process for improving critical dimension uniformity of integrated circuit arrays |
US7795149B2 (en) | 2006-06-01 | 2010-09-14 | Micron Technology, Inc. | Masking techniques and contact imprint reticles for dense semiconductor fabrication |
US7723009B2 (en) | 2006-06-02 | 2010-05-25 | Micron Technology, Inc. | Topography based patterning |
US8852851B2 (en) | 2006-07-10 | 2014-10-07 | Micron Technology, Inc. | Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same |
US7960797B2 (en) * | 2006-08-29 | 2011-06-14 | Micron Technology, Inc. | Semiconductor devices including fine pitch arrays with staggered contacts |
US7611980B2 (en) * | 2006-08-30 | 2009-11-03 | Micron Technology, Inc. | Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures |
US7666578B2 (en) | 2006-09-14 | 2010-02-23 | Micron Technology, Inc. | Efficient pitch multiplication process |
US8129289B2 (en) | 2006-10-05 | 2012-03-06 | Micron Technology, Inc. | Method to deposit conformal low temperature SiO2 |
US7923373B2 (en) * | 2007-06-04 | 2011-04-12 | Micron Technology, Inc. | Pitch multiplication using self-assembling materials |
US8980756B2 (en) * | 2007-07-30 | 2015-03-17 | Micron Technology, Inc. | Methods for device fabrication using pitch reduction |
US8563229B2 (en) * | 2007-07-31 | 2013-10-22 | Micron Technology, Inc. | Process of semiconductor fabrication with mask overlay on pitch multiplied features and associated structures |
US8481417B2 (en) | 2007-08-03 | 2013-07-09 | Micron Technology, Inc. | Semiconductor structures including tight pitch contacts and methods to form same |
JP2009054956A (ja) * | 2007-08-29 | 2009-03-12 | Toshiba Corp | 半導体メモリ |
US7737039B2 (en) | 2007-11-01 | 2010-06-15 | Micron Technology, Inc. | Spacer process for on pitch contacts and related structures |
US7659208B2 (en) | 2007-12-06 | 2010-02-09 | Micron Technology, Inc | Method for forming high density patterns |
US7759201B2 (en) * | 2007-12-17 | 2010-07-20 | Sandisk 3D Llc | Method for fabricating pitch-doubling pillar structures |
US7790531B2 (en) | 2007-12-18 | 2010-09-07 | Micron Technology, Inc. | Methods for isolating portions of a loop of pitch-multiplied material and related structures |
KR100919349B1 (ko) * | 2007-12-27 | 2009-09-25 | 주식회사 하이닉스반도체 | 반도체 소자의 금속 배선 형성 방법 |
CN101960565B (zh) * | 2008-02-28 | 2012-09-05 | 惠普开发有限公司 | 半导体基板接触通孔 |
US8030218B2 (en) | 2008-03-21 | 2011-10-04 | Micron Technology, Inc. | Method for selectively modifying spacing between pitch multiplied structures |
US7713818B2 (en) | 2008-04-11 | 2010-05-11 | Sandisk 3D, Llc | Double patterning method |
US7981592B2 (en) * | 2008-04-11 | 2011-07-19 | Sandisk 3D Llc | Double patterning method |
US7786015B2 (en) * | 2008-04-28 | 2010-08-31 | Sandisk 3D Llc | Method for fabricating self-aligned complementary pillar structures and wiring |
US7989307B2 (en) | 2008-05-05 | 2011-08-02 | Micron Technology, Inc. | Methods of forming isolated active areas, trenches, and conductive lines in semiconductor structures and semiconductor structures including the same |
US10151981B2 (en) | 2008-05-22 | 2018-12-11 | Micron Technology, Inc. | Methods of forming structures supported by semiconductor substrates |
US20090302472A1 (en) * | 2008-06-05 | 2009-12-10 | Samsung Electronics Co., Ltd. | Non-volatile memory devices including shared bit lines and methods of fabricating the same |
KR101215173B1 (ko) * | 2008-06-09 | 2012-12-24 | 에스케이하이닉스 주식회사 | 반도체 소자의 형성 방법 |
US7732235B2 (en) | 2008-06-30 | 2010-06-08 | Sandisk 3D Llc | Method for fabricating high density pillar structures by double patterning using positive photoresist |
US7781269B2 (en) * | 2008-06-30 | 2010-08-24 | Sandisk 3D Llc | Triangle two dimensional complementary patterning of pillars |
US8076208B2 (en) | 2008-07-03 | 2011-12-13 | Micron Technology, Inc. | Method for forming transistor with high breakdown voltage using pitch multiplication technique |
US8101497B2 (en) | 2008-09-11 | 2012-01-24 | Micron Technology, Inc. | Self-aligned trench formation |
US8076056B2 (en) * | 2008-10-06 | 2011-12-13 | Sandisk 3D Llc | Method of making sub-resolution pillar structures using undercutting technique |
US8080443B2 (en) | 2008-10-27 | 2011-12-20 | Sandisk 3D Llc | Method of making pillars using photoresist spacer mask |
US8492282B2 (en) | 2008-11-24 | 2013-07-23 | Micron Technology, Inc. | Methods of forming a masking pattern for integrated circuits |
US8247302B2 (en) | 2008-12-04 | 2012-08-21 | Micron Technology, Inc. | Methods of fabricating substrates |
US8273634B2 (en) | 2008-12-04 | 2012-09-25 | Micron Technology, Inc. | Methods of fabricating substrates |
US8796155B2 (en) | 2008-12-04 | 2014-08-05 | Micron Technology, Inc. | Methods of fabricating substrates |
US8114765B2 (en) | 2008-12-31 | 2012-02-14 | Sandisk 3D Llc | Methods for increased array feature density |
US8084347B2 (en) * | 2008-12-31 | 2011-12-27 | Sandisk 3D Llc | Resist feature and removable spacer pitch doubling patterning method for pillar structures |
US8268543B2 (en) * | 2009-03-23 | 2012-09-18 | Micron Technology, Inc. | Methods of forming patterns on substrates |
US9330934B2 (en) * | 2009-05-18 | 2016-05-03 | Micron Technology, Inc. | Methods of forming patterns on substrates |
DE102009023251B4 (de) * | 2009-05-29 | 2011-02-24 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | Verfahren zur Herstellung eines Kontaktelements mit großem Aspektverhältnis und mit einer günstigeren Form in einem Halbleiterbauelement zur Verbesserung der Abscheidung einer Beschichtung |
US8026172B2 (en) * | 2009-06-29 | 2011-09-27 | Sandisk 3D Llc | Method of forming contact hole arrays using a hybrid spacer technique |
US20110129991A1 (en) * | 2009-12-02 | 2011-06-02 | Kyle Armstrong | Methods Of Patterning Materials, And Methods Of Forming Memory Cells |
US7923305B1 (en) | 2010-01-12 | 2011-04-12 | Sandisk 3D Llc | Patterning method for high density pillar structures |
US8026178B2 (en) * | 2010-01-12 | 2011-09-27 | Sandisk 3D Llc | Patterning method for high density pillar structures |
FR2960700B1 (fr) | 2010-06-01 | 2012-05-18 | Commissariat Energie Atomique | Procede de lithographie pour la realisation de reseaux de conducteurs relies par des vias |
DE102010035602A1 (de) * | 2010-06-10 | 2011-12-15 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Verfahren zur Strukturierung einer Schicht unter Einsatz einer Hartmaske |
US8518788B2 (en) | 2010-08-11 | 2013-08-27 | Micron Technology, Inc. | Methods of forming a plurality of capacitors |
US8216939B2 (en) | 2010-08-20 | 2012-07-10 | Micron Technology, Inc. | Methods of forming openings |
US8455341B2 (en) | 2010-09-02 | 2013-06-04 | Micron Technology, Inc. | Methods of forming features of integrated circuitry |
US8461053B2 (en) * | 2010-12-17 | 2013-06-11 | Spansion Llc | Self-aligned NAND flash select-gate wordlines for spacer double patterning |
US8586478B2 (en) * | 2011-03-28 | 2013-11-19 | Renesas Electronics Corporation | Method of making a semiconductor device |
US8575032B2 (en) | 2011-05-05 | 2013-11-05 | Micron Technology, Inc. | Methods of forming a pattern on a substrate |
US9076680B2 (en) | 2011-10-18 | 2015-07-07 | Micron Technology, Inc. | Integrated circuitry, methods of forming capacitors, and methods of forming integrated circuitry comprising an array of capacitors and circuitry peripheral to the array |
US9177794B2 (en) | 2012-01-13 | 2015-11-03 | Micron Technology, Inc. | Methods of patterning substrates |
US8664077B2 (en) * | 2012-02-14 | 2014-03-04 | Nanya Technology Corp. | Method for forming self-aligned overlay mark |
US9276001B2 (en) * | 2012-05-23 | 2016-03-01 | Nanya Technology Corporation | Semiconductor device and method for manufacturing the same |
US8629048B1 (en) | 2012-07-06 | 2014-01-14 | Micron Technology, Inc. | Methods of forming a pattern on a substrate |
US9269747B2 (en) | 2012-08-23 | 2016-02-23 | Micron Technology, Inc. | Self-aligned interconnection for integrated circuits |
US9034197B2 (en) * | 2012-09-13 | 2015-05-19 | HGST Netherlands B.V. | Method for separately processing regions on a patterned medium |
US9111857B2 (en) | 2012-09-21 | 2015-08-18 | Micron Technology, Inc. | Method, system and device for recessed contact in memory array |
US20140134844A1 (en) * | 2012-11-12 | 2014-05-15 | Infineon Technologies Dresden Gmbh | Method for processing a die |
US20150118832A1 (en) * | 2013-10-24 | 2015-04-30 | Applied Materials, Inc. | Methods for patterning a hardmask layer for an ion implantation process |
US9159579B2 (en) * | 2013-10-25 | 2015-10-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lithography using multilayer spacer for reduced spacer footing |
US9437479B2 (en) * | 2013-11-19 | 2016-09-06 | Applied Materials, Inc. | Methods for forming an interconnect pattern on a substrate |
US9177797B2 (en) * | 2013-12-04 | 2015-11-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lithography using high selectivity spacers for pitch reduction |
US9679946B2 (en) * | 2014-08-25 | 2017-06-13 | HGST, Inc. | 3-D planes memory device |
US9324619B2 (en) * | 2014-08-25 | 2016-04-26 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
KR102265271B1 (ko) | 2015-01-14 | 2021-06-17 | 삼성전자주식회사 | 반도체 소자 및 그 제조방법 |
KR102323251B1 (ko) | 2015-01-21 | 2021-11-09 | 삼성전자주식회사 | 반도체 소자 및 반도체 소자의 제조방법 |
KR102337410B1 (ko) | 2015-04-06 | 2021-12-10 | 삼성전자주식회사 | 반도체 소자의 미세 패턴 형성 방법 |
CN108369899B (zh) * | 2015-11-20 | 2023-11-17 | 东京毅力科创株式会社 | 形成用于亚分辨率基板图案化的蚀刻掩模的方法 |
CN108475640B (zh) | 2016-01-20 | 2023-06-06 | 应用材料公司 | 用于侧向硬模凹槽减小的混合碳硬模 |
US9837314B2 (en) * | 2016-02-02 | 2017-12-05 | Tokyo Electron Limited | Self-alignment of metal and via using selective deposition |
TWI661466B (zh) * | 2016-04-14 | 2019-06-01 | 日商東京威力科創股份有限公司 | 使用具有多種材料之一層的基板圖案化方法 |
US10163690B2 (en) * | 2016-11-30 | 2018-12-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | 2-D interconnections for integrated circuits |
CN108735711B (zh) * | 2017-04-13 | 2021-04-23 | 中芯国际集成电路制造(北京)有限公司 | 一种半导体器件及其制备方法、电子装置 |
CN109309091A (zh) * | 2017-07-28 | 2019-02-05 | 联华电子股份有限公司 | 图案化方法 |
TWI658763B (zh) * | 2017-10-11 | 2019-05-01 | 欣興電子股份有限公司 | 製造導線之方法 |
US10347487B2 (en) * | 2017-11-14 | 2019-07-09 | Micron Technology, Inc. | Cell contact |
US10790155B2 (en) * | 2018-06-27 | 2020-09-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of manufacturing semiconductor devices |
CN112928057B (zh) * | 2019-12-05 | 2023-05-19 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
US11502041B2 (en) | 2020-04-22 | 2022-11-15 | Nanya Technology Corporation | Method of forming a pattern |
CN112018127A (zh) * | 2020-07-21 | 2020-12-01 | 长江存储科技有限责任公司 | 金属层的形成方法、3d存储器件及其制造方法 |
US11257766B1 (en) | 2020-08-21 | 2022-02-22 | Micron Technology, Inc. | Methods of forming microelectronic devices, and related microelectronic devices, memory devices, and electronic systems |
Family Cites Families (195)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US292991A (en) * | 1884-02-05 | Machine for cutting heads of boxes | ||
US77524A (en) * | 1868-05-05 | Improvement in harvesters | ||
US4234362A (en) * | 1978-11-03 | 1980-11-18 | International Business Machines Corporation | Method for forming an insulator between layers of conductive material |
US4508579A (en) | 1981-03-30 | 1985-04-02 | International Business Machines Corporation | Lateral device structures using self-aligned fabrication techniques |
US4432132A (en) * | 1981-12-07 | 1984-02-21 | Bell Telephone Laboratories, Incorporated | Formation of sidewall oxide layers by reactive oxygen ion etching to define submicron features |
US4419809A (en) | 1981-12-30 | 1983-12-13 | International Business Machines Corporation | Fabrication process of sub-micrometer channel length MOSFETs |
DE3242113A1 (de) * | 1982-11-13 | 1984-05-24 | Ibm Deutschland Gmbh, 7000 Stuttgart | Verfahren zur herstellung einer duennen dielektrischen isolation in einem siliciumhalbleiterkoerper |
US4716131A (en) | 1983-11-28 | 1987-12-29 | Nec Corporation | Method of manufacturing semiconductor device having polycrystalline silicon layer with metal silicide film |
US4648937A (en) * | 1985-10-30 | 1987-03-10 | International Business Machines Corporation | Method of preventing asymmetric etching of lines in sub-micrometer range sidewall images transfer |
GB8528967D0 (en) | 1985-11-25 | 1986-01-02 | Plessey Co Plc | Semiconductor device manufacture |
EP0238690B1 (en) * | 1986-03-27 | 1991-11-06 | International Business Machines Corporation | Process for forming sidewalls |
US5514885A (en) * | 1986-10-09 | 1996-05-07 | Myrick; James J. | SOI methods and apparatus |
US4838991A (en) * | 1987-10-30 | 1989-06-13 | International Business Machines Corporation | Process for defining organic sidewall structures |
US4776922A (en) * | 1987-10-30 | 1988-10-11 | International Business Machines Corporation | Formation of variable-width sidewall structures |
US5328810A (en) * | 1990-05-07 | 1994-07-12 | Micron Technology, Inc. | Method for reducing, by a factor or 2-N, the minimum masking pitch of a photolithographic process |
US5013680A (en) * | 1990-07-18 | 1991-05-07 | Micron Technology, Inc. | Process for fabricating a DRAM array having feature widths that transcend the resolution limit of available photolithography |
US5053105A (en) * | 1990-07-19 | 1991-10-01 | Micron Technology, Inc. | Process for creating an etch mask suitable for deep plasma etches employing self-aligned silicidation of a metal layer masked with a silicon dioxide template |
US5047117A (en) * | 1990-09-26 | 1991-09-10 | Micron Technology, Inc. | Method of forming a narrow self-aligned, annular opening in a masking layer |
DE4034612A1 (de) * | 1990-10-31 | 1992-05-07 | Huels Chemische Werke Ag | Verfahren zur herstellung von methacryloxy- oder acryloxygruppen enthaltenden organosilanen |
IT1243919B (it) | 1990-11-20 | 1994-06-28 | Cons Ric Microelettronica | Procedimento per l'ottenimento di solchi submicrometrici planarizzati in circuiti integrati realizzati con tecnologia ulsi |
US5330879A (en) | 1992-07-16 | 1994-07-19 | Micron Technology, Inc. | Method for fabrication of close-tolerance lines and sharp emission tips on a semiconductor wafer |
DE4236609A1 (de) | 1992-10-29 | 1994-05-05 | Siemens Ag | Verfahren zur Erzeugung einer Struktur in der Oberfläche eines Substrats |
US5470661A (en) * | 1993-01-07 | 1995-11-28 | International Business Machines Corporation | Diamond-like carbon films from a hydrocarbon helium plasma |
US5532741A (en) * | 1993-05-19 | 1996-07-02 | Rohm Co., Ltd. | Video image display and video camera for producing a mirror image |
US6042998A (en) | 1993-09-30 | 2000-03-28 | The University Of New Mexico | Method and apparatus for extending spatial frequencies in photolithography images |
KR970007173B1 (ko) * | 1994-07-14 | 1997-05-03 | 현대전자산업 주식회사 | 미세패턴 형성방법 |
JPH0855920A (ja) | 1994-08-15 | 1996-02-27 | Toshiba Corp | 半導体装置の製造方法 |
JPH0855908A (ja) | 1994-08-17 | 1996-02-27 | Toshiba Corp | 半導体装置 |
US5600153A (en) * | 1994-10-07 | 1997-02-04 | Micron Technology, Inc. | Conductive polysilicon lines and thin film transistors |
TW366367B (en) | 1995-01-26 | 1999-08-11 | Ibm | Sputter deposition of hydrogenated amorphous carbon film |
US5795830A (en) * | 1995-06-06 | 1998-08-18 | International Business Machines Corporation | Reducing pitch with continuously adjustable line and space dimensions |
KR100190757B1 (ko) * | 1995-06-30 | 1999-06-01 | 김영환 | 모스 전계 효과 트랜지스터 형성방법 |
JP3393286B2 (ja) * | 1995-09-08 | 2003-04-07 | ソニー株式会社 | パターンの形成方法 |
US5789320A (en) | 1996-04-23 | 1998-08-04 | International Business Machines Corporation | Plating of noble metal electrodes for DRAM and FRAM |
TW329539B (en) * | 1996-07-05 | 1998-04-11 | Mitsubishi Electric Corp | The semiconductor device and its manufacturing method |
JP3164026B2 (ja) | 1996-08-21 | 2001-05-08 | 日本電気株式会社 | 半導体装置及びその製造方法 |
US5880018A (en) * | 1996-10-07 | 1999-03-09 | Motorola Inc. | Method for manufacturing a low dielectric constant inter-level integrated circuit structure |
US5998256A (en) | 1996-11-01 | 1999-12-07 | Micron Technology, Inc. | Semiconductor processing methods of forming devices on a substrate, forming device arrays on a substrate, forming conductive lines on a substrate, and forming capacitor arrays on a substrate, and integrated circuitry |
US6395613B1 (en) * | 2000-08-30 | 2002-05-28 | Micron Technology, Inc. | Semiconductor processing methods of forming a plurality of capacitors on a substrate, bit line contacts and method of forming bit line contacts |
US5895740A (en) | 1996-11-13 | 1999-04-20 | Vanguard International Semiconductor Corp. | Method of forming contact holes of reduced dimensions by using in-situ formed polymeric sidewall spacers |
KR100231134B1 (ko) | 1997-06-14 | 1999-11-15 | 문정환 | 반도체장치의 배선 형성 방법 |
US6063688A (en) | 1997-09-29 | 2000-05-16 | Intel Corporation | Fabrication of deep submicron structures and quantum wire transistors using hard-mask transistor width definition |
KR100247862B1 (ko) * | 1997-12-11 | 2000-03-15 | 윤종용 | 반도체 장치 및 그 제조방법 |
US6143476A (en) | 1997-12-12 | 2000-11-07 | Applied Materials Inc | Method for high temperature etching of patterned layers using an organic mask stack |
US6291334B1 (en) * | 1997-12-19 | 2001-09-18 | Applied Materials, Inc. | Etch stop layer for dual damascene process |
US6004862A (en) | 1998-01-20 | 1999-12-21 | Advanced Micro Devices, Inc. | Core array and periphery isolation technique |
JP2975917B2 (ja) | 1998-02-06 | 1999-11-10 | 株式会社半導体プロセス研究所 | 半導体装置の製造方法及び半導体装置の製造装置 |
KR100301038B1 (ko) * | 1998-03-02 | 2001-09-06 | 윤종용 | 씨오비(cob)를구비한반도체메모리장치및그제조방법 |
US5933725A (en) * | 1998-05-27 | 1999-08-03 | Vanguard International Semiconductor Corporation | Word line resistance reduction method and design for high density memory with relaxed metal pitch |
TW376582B (en) | 1998-06-26 | 1999-12-11 | Vanguard Int Semiconduct Corp | Method of forming COB DRAM with self-aligned pole and bitline contact plug |
US6020255A (en) * | 1998-07-13 | 2000-02-01 | Taiwan Semiconductor Manufacturing Company | Dual damascene interconnect process with borderless contact |
US6245662B1 (en) * | 1998-07-23 | 2001-06-12 | Applied Materials, Inc. | Method of producing an interconnect structure for an integrated circuit |
US6060383A (en) * | 1998-08-10 | 2000-05-09 | Nogami; Takeshi | Method for making multilayered coaxial interconnect structure |
US6071789A (en) * | 1998-11-10 | 2000-06-06 | Vanguard International Semiconductor Corporation | Method for simultaneously fabricating a DRAM capacitor and metal interconnections |
WO2000034497A2 (en) * | 1998-12-09 | 2000-06-15 | The General Hospital Corporation | Enhanced packaging of herpes virus amplicons and generation of recombinant virus vectors |
US6531067B1 (en) * | 1998-12-28 | 2003-03-11 | Asahi Kasei Microsystems Co., Ltd. | Method for forming contact hole |
US6204187B1 (en) | 1999-01-06 | 2001-03-20 | Infineon Technologies North America, Corp. | Contact and deep trench patterning |
US6211044B1 (en) | 1999-04-12 | 2001-04-03 | Advanced Micro Devices | Process for fabricating a semiconductor device component using a selective silicidation reaction |
JP2000307084A (ja) | 1999-04-23 | 2000-11-02 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
US6110837A (en) * | 1999-04-28 | 2000-08-29 | Worldwide Semiconductor Manufacturing Corp. | Method for forming a hard mask of half critical dimension |
US6136662A (en) * | 1999-05-13 | 2000-10-24 | Lsi Logic Corporation | Semiconductor wafer having a layer-to-layer alignment mark and method for fabricating the same |
JP2000357736A (ja) | 1999-06-15 | 2000-12-26 | Toshiba Corp | 半導体装置及びその製造方法 |
KR100333382B1 (ko) * | 1999-06-24 | 2002-04-18 | 박종섭 | 반도체 장치의 다층금속배선 형성방법 |
JP2001077196A (ja) * | 1999-09-08 | 2001-03-23 | Sony Corp | 半導体装置の製造方法 |
US6730571B1 (en) * | 1999-10-14 | 2004-05-04 | Chartered Semiconductor Manufacturing Ltd. | Method to form a cross network of air gaps within IMD layer |
US6362057B1 (en) | 1999-10-26 | 2002-03-26 | Motorola, Inc. | Method for forming a semiconductor device |
US6582891B1 (en) * | 1999-12-02 | 2003-06-24 | Axcelis Technologies, Inc. | Process for reducing edge roughness in patterned photoresist |
US6573030B1 (en) * | 2000-02-17 | 2003-06-03 | Applied Materials, Inc. | Method for depositing an amorphous carbon layer |
US6967140B2 (en) * | 2000-03-01 | 2005-11-22 | Intel Corporation | Quantum wire gate device and method of making same |
US6297554B1 (en) * | 2000-03-10 | 2001-10-02 | United Microelectronics Corp. | Dual damascene interconnect structure with reduced parasitic capacitance |
US6423474B1 (en) | 2000-03-21 | 2002-07-23 | Micron Technology, Inc. | Use of DARC and BARC in flash memory processing |
JP3805603B2 (ja) * | 2000-05-29 | 2006-08-02 | 富士通株式会社 | 半導体装置及びその製造方法 |
US6632741B1 (en) | 2000-07-19 | 2003-10-14 | International Business Machines Corporation | Self-trimming method on looped patterns |
US6455372B1 (en) | 2000-08-14 | 2002-09-24 | Micron Technology, Inc. | Nucleation for improved flash erase characteristics |
US6348380B1 (en) | 2000-08-25 | 2002-02-19 | Micron Technology, Inc. | Use of dilute steam ambient for improvement of flash devices |
SE517275C2 (sv) * | 2000-09-20 | 2002-05-21 | Obducat Ab | Sätt vid våtetsning av ett substrat |
US6335257B1 (en) * | 2000-09-29 | 2002-01-01 | Vanguard International Semiconductor Corporation | Method of making pillar-type structure on semiconductor substrate |
US6667237B1 (en) | 2000-10-12 | 2003-12-23 | Vram Technologies, Llc | Method and apparatus for patterning fine dimensions |
US6534243B1 (en) * | 2000-10-23 | 2003-03-18 | Advanced Micro Devices, Inc. | Chemical feature doubling process |
US6926843B2 (en) | 2000-11-30 | 2005-08-09 | International Business Machines Corporation | Etching of hard masks |
US6664028B2 (en) | 2000-12-04 | 2003-12-16 | United Microelectronics Corp. | Method of forming opening in wafer layer |
JP3406302B2 (ja) | 2001-01-16 | 2003-05-12 | 株式会社半導体先端テクノロジーズ | 微細パターンの形成方法、半導体装置の製造方法および半導体装置 |
US6740594B2 (en) | 2001-05-31 | 2004-05-25 | Infineon Technologies Ag | Method for removing carbon-containing polysilane from a semiconductor without stripping |
US6960806B2 (en) * | 2001-06-21 | 2005-11-01 | International Business Machines Corporation | Double gated vertical transistor with different first and second gate materials |
US6522584B1 (en) | 2001-08-02 | 2003-02-18 | Micron Technology, Inc. | Programming methods for multi-level flash EEPROMs |
US6744094B2 (en) | 2001-08-24 | 2004-06-01 | Micron Technology Inc. | Floating gate transistor with horizontal gate layers stacked next to vertical body |
TW497138B (en) * | 2001-08-28 | 2002-08-01 | Winbond Electronics Corp | Method for improving consistency of critical dimension |
DE10142590A1 (de) | 2001-08-31 | 2003-04-03 | Infineon Technologies Ag | Verfahren zur Seitenwandverstärkung von Resiststrukturen und zur Herstellung von Strukturen mit reduzierter Strukturgröße |
US7045383B2 (en) * | 2001-09-19 | 2006-05-16 | BAE Systems Information and Ovonyx, Inc | Method for making tapered opening for programmable resistance memory element |
JP4969001B2 (ja) * | 2001-09-20 | 2012-07-04 | 株式会社半導体エネルギー研究所 | 半導体装置及びその作製方法 |
JP2003133437A (ja) * | 2001-10-24 | 2003-05-09 | Hitachi Ltd | 半導体装置の製造方法および半導体装置 |
US7226853B2 (en) | 2001-12-26 | 2007-06-05 | Applied Materials, Inc. | Method of forming a dual damascene structure utilizing a three layer hard mask structure |
TW576864B (en) * | 2001-12-28 | 2004-02-21 | Toshiba Corp | Method for manufacturing a light-emitting device |
US6638441B2 (en) * | 2002-01-07 | 2003-10-28 | Macronix International Co., Ltd. | Method for pitch reduction |
DE10207131B4 (de) | 2002-02-20 | 2007-12-20 | Infineon Technologies Ag | Verfahren zur Bildung einer Hartmaske in einer Schicht auf einer flachen Scheibe |
US6620715B1 (en) | 2002-03-29 | 2003-09-16 | Cypress Semiconductor Corp. | Method for forming sub-critical dimension structures in an integrated circuit |
KR100428791B1 (ko) * | 2002-04-17 | 2004-04-28 | 삼성전자주식회사 | 저유전율 절연막을 이용한 듀얼 다마신 배선 형성방법 |
US6759180B2 (en) | 2002-04-23 | 2004-07-06 | Hewlett-Packard Development Company, L.P. | Method of fabricating sub-lithographic sized line and space patterns for nano-imprinting lithography |
US20030207584A1 (en) * | 2002-05-01 | 2003-11-06 | Swaminathan Sivakumar | Patterning tighter and looser pitch geometries |
US6951709B2 (en) * | 2002-05-03 | 2005-10-04 | Micron Technology, Inc. | Method of fabricating a semiconductor multilevel interconnect structure |
US6602779B1 (en) | 2002-05-13 | 2003-08-05 | Taiwan Semiconductor Manufacturing Co., Ltd | Method for forming low dielectric constant damascene structure while employing carbon doped silicon oxide planarizing stop layer |
US6703312B2 (en) | 2002-05-17 | 2004-03-09 | International Business Machines Corporation | Method of forming active devices of different gatelengths using lithographic printed gate images of same length |
JP4102112B2 (ja) * | 2002-06-06 | 2008-06-18 | 株式会社東芝 | 半導体装置及びその製造方法 |
US6818141B1 (en) | 2002-06-10 | 2004-11-16 | Advanced Micro Devices, Inc. | Application of the CVD bilayer ARC as a hard mask for definition of the subresolution trench features between polysilicon wordlines |
US6734107B2 (en) * | 2002-06-12 | 2004-05-11 | Macronix International Co., Ltd. | Pitch reduction in semiconductor fabrication |
US6559017B1 (en) | 2002-06-13 | 2003-05-06 | Advanced Micro Devices, Inc. | Method of using amorphous carbon as spacer material in a disposable spacer process |
KR100476924B1 (ko) | 2002-06-14 | 2005-03-17 | 삼성전자주식회사 | 반도체 장치의 미세 패턴 형성 방법 |
US6924191B2 (en) | 2002-06-20 | 2005-08-02 | Applied Materials, Inc. | Method for fabricating a gate structure of a field effect transistor |
WO2004003977A2 (en) * | 2002-06-27 | 2004-01-08 | Advanced Micro Devices, Inc. | Method of defining the dimensions of circuit elements by using spacer deposition techniques |
US6689695B1 (en) | 2002-06-28 | 2004-02-10 | Taiwan Semiconductor Manufacturing Company | Multi-purpose composite mask for dual damascene patterning |
US6500756B1 (en) | 2002-06-28 | 2002-12-31 | Advanced Micro Devices, Inc. | Method of forming sub-lithographic spaces between polysilicon lines |
US6664154B1 (en) * | 2002-06-28 | 2003-12-16 | Advanced Micro Devices, Inc. | Method of using amorphous carbon film as a sacrificial layer in replacement gate integration processes |
US6835663B2 (en) * | 2002-06-28 | 2004-12-28 | Infineon Technologies Ag | Hardmask of amorphous carbon-hydrogen (a-C:H) layers with tunable etch resistivity |
US20040018738A1 (en) * | 2002-07-22 | 2004-01-29 | Wei Liu | Method for fabricating a notch gate structure of a field effect transistor |
US6913871B2 (en) | 2002-07-23 | 2005-07-05 | Intel Corporation | Fabricating sub-resolution structures in planar lightwave devices |
US6800930B2 (en) * | 2002-07-31 | 2004-10-05 | Micron Technology, Inc. | Semiconductor dice having back side redistribution layer accessed using through-silicon vias, and assemblies |
US6673684B1 (en) * | 2002-07-31 | 2004-01-06 | Advanced Micro Devices, Inc. | Use of diamond as a hard mask material |
US6764949B2 (en) * | 2002-07-31 | 2004-07-20 | Advanced Micro Devices, Inc. | Method for reducing pattern deformation and photoresist poisoning in semiconductor device fabrication |
US6939808B2 (en) | 2002-08-02 | 2005-09-06 | Applied Materials, Inc. | Undoped and fluorinated amorphous carbon film as pattern mask for metal etch |
KR100480610B1 (ko) | 2002-08-09 | 2005-03-31 | 삼성전자주식회사 | 실리콘 산화막을 이용한 미세 패턴 형성방법 |
US6566280B1 (en) * | 2002-08-26 | 2003-05-20 | Intel Corporation | Forming polymer features on a substrate |
US7205598B2 (en) * | 2002-08-29 | 2007-04-17 | Micron Technology, Inc. | Random access memory device utilizing a vertically oriented select transistor |
US6794699B2 (en) * | 2002-08-29 | 2004-09-21 | Micron Technology Inc | Annular gate and technique for fabricating an annular gate |
US6756284B2 (en) | 2002-09-18 | 2004-06-29 | Silicon Storage Technology, Inc. | Method for forming a sublithographic opening in a semiconductor process |
JP4058327B2 (ja) * | 2002-10-18 | 2008-03-05 | 富士通株式会社 | 半導体装置の製造方法 |
US6706571B1 (en) | 2002-10-22 | 2004-03-16 | Advanced Micro Devices, Inc. | Method for forming multiple structures in a semiconductor device |
US6888755B2 (en) * | 2002-10-28 | 2005-05-03 | Sandisk Corporation | Flash memory cell arrays having dual control gates per memory cell charge storage element |
JP4034164B2 (ja) | 2002-10-28 | 2008-01-16 | 富士通株式会社 | 微細パターンの作製方法及び半導体装置の製造方法 |
US7119020B2 (en) | 2002-12-04 | 2006-10-10 | Matsushita Electric Industrial Co., Ltd. | Method for fabricating semiconductor device |
US6686245B1 (en) * | 2002-12-20 | 2004-02-03 | Motorola, Inc. | Vertical MOSFET with asymmetric gate structure |
US6916594B2 (en) | 2002-12-30 | 2005-07-12 | Hynix Semiconductor Inc. | Overcoating composition for photoresist and method for forming photoresist pattern using the same |
US7015124B1 (en) | 2003-04-28 | 2006-03-21 | Advanced Micro Devices, Inc. | Use of amorphous carbon for gate patterning |
US6773998B1 (en) * | 2003-05-20 | 2004-08-10 | Advanced Micro Devices, Inc. | Modified film stack and patterning strategy for stress compensation and prevention of pattern distortion in amorphous carbon gate patterning |
JP4578785B2 (ja) * | 2003-05-21 | 2010-11-10 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US7291878B2 (en) * | 2003-06-03 | 2007-11-06 | Hitachi Global Storage Technologies Netherlands B.V. | Ultra low-cost solid-state memory |
US6835662B1 (en) | 2003-07-14 | 2004-12-28 | Advanced Micro Devices, Inc. | Partially de-coupled core and periphery gate module process |
DE10345455A1 (de) | 2003-09-30 | 2005-05-04 | Infineon Technologies Ag | Verfahren zum Erzeugen einer Hartmaske und Hartmasken-Anordnung |
KR100536801B1 (ko) * | 2003-10-01 | 2005-12-14 | 동부아남반도체 주식회사 | 반도체 소자 및 그 제조 방법 |
TWI220560B (en) * | 2003-10-27 | 2004-08-21 | Powerchip Semiconductor Corp | NAND flash memory cell architecture, NAND flash memory cell array, manufacturing method and operating method of the same |
US6867116B1 (en) * | 2003-11-10 | 2005-03-15 | Macronix International Co., Ltd. | Fabrication method of sub-resolution pitch for integrated circuits |
JP2005150333A (ja) * | 2003-11-14 | 2005-06-09 | Sony Corp | 半導体装置の製造方法 |
KR100554514B1 (ko) | 2003-12-26 | 2006-03-03 | 삼성전자주식회사 | 반도체 장치에서 패턴 형성 방법 및 이를 이용한 게이트형성방법. |
US6998332B2 (en) * | 2004-01-08 | 2006-02-14 | International Business Machines Corporation | Method of independent P and N gate length control of FET device made by sidewall image transfer technique |
US6875703B1 (en) * | 2004-01-20 | 2005-04-05 | International Business Machines Corporation | Method for forming quadruple density sidewall image transfer (SIT) structures |
US7372091B2 (en) * | 2004-01-27 | 2008-05-13 | Micron Technology, Inc. | Selective epitaxy vertical integrated circuit components |
US7064078B2 (en) * | 2004-01-30 | 2006-06-20 | Applied Materials | Techniques for the use of amorphous carbon (APF) for various etch and litho integration scheme |
US8486287B2 (en) | 2004-03-19 | 2013-07-16 | The Regents Of The University Of California | Methods for fabrication of positional and compositionally controlled nanostructures on substrate |
US7153780B2 (en) * | 2004-03-24 | 2006-12-26 | Intel Corporation | Method and apparatus for self-aligned MOS patterning |
US7098105B2 (en) | 2004-05-26 | 2006-08-29 | Micron Technology, Inc. | Methods for forming semiconductor structures |
US6955961B1 (en) * | 2004-05-27 | 2005-10-18 | Macronix International Co., Ltd. | Method for defining a minimum pitch in an integrated circuit beyond photolithographic resolution |
US7183205B2 (en) * | 2004-06-08 | 2007-02-27 | Macronix International Co., Ltd. | Method of pitch dimension shrinkage |
JP4543767B2 (ja) * | 2004-06-10 | 2010-09-15 | 株式会社ニコン | 露光装置及びデバイス製造方法 |
US7473644B2 (en) * | 2004-07-01 | 2009-01-06 | Micron Technology, Inc. | Method for forming controlled geometry hardmasks including subresolution elements |
US7074666B2 (en) * | 2004-07-28 | 2006-07-11 | International Business Machines Corporation | Borderless contact structures |
KR100704470B1 (ko) * | 2004-07-29 | 2007-04-10 | 주식회사 하이닉스반도체 | 비결정성 탄소막을 희생 하드마스크로 이용하는반도체소자 제조 방법 |
US7175944B2 (en) | 2004-08-31 | 2007-02-13 | Micron Technology, Inc. | Prevention of photoresist scumming |
US7151040B2 (en) | 2004-08-31 | 2006-12-19 | Micron Technology, Inc. | Methods for increasing photo alignment margins |
US7910288B2 (en) | 2004-09-01 | 2011-03-22 | Micron Technology, Inc. | Mask material conversion |
US7442976B2 (en) | 2004-09-01 | 2008-10-28 | Micron Technology, Inc. | DRAM cells with vertical transistors |
US7115525B2 (en) | 2004-09-02 | 2006-10-03 | Micron Technology, Inc. | Method for integrated circuit fabrication using pitch multiplication |
US7655387B2 (en) | 2004-09-02 | 2010-02-02 | Micron Technology, Inc. | Method to align mask patterns |
KR100614651B1 (ko) * | 2004-10-11 | 2006-08-22 | 삼성전자주식회사 | 회로 패턴의 노광을 위한 장치 및 방법, 사용되는포토마스크 및 그 설계 방법, 그리고 조명계 및 그 구현방법 |
US7176130B2 (en) * | 2004-11-12 | 2007-02-13 | Freescale Semiconductor, Inc. | Plasma treatment for surface of semiconductor device |
US7208379B2 (en) | 2004-11-29 | 2007-04-24 | Texas Instruments Incorporated | Pitch multiplication process |
US7298004B2 (en) * | 2004-11-30 | 2007-11-20 | Infineon Technologies Ag | Charge-trapping memory cell and method for production |
KR100596795B1 (ko) * | 2004-12-16 | 2006-07-05 | 주식회사 하이닉스반도체 | 반도체 소자의 캐패시터 및 그 형성방법 |
US7271107B2 (en) * | 2005-02-03 | 2007-09-18 | Lam Research Corporation | Reduction of feature critical dimensions using multiple masks |
KR100787352B1 (ko) | 2005-02-23 | 2007-12-18 | 주식회사 하이닉스반도체 | 하드마스크용 조성물 및 이를 이용한 반도체 소자의 패턴형성 방법 |
US7253118B2 (en) * | 2005-03-15 | 2007-08-07 | Micron Technology, Inc. | Pitch reduced patterns relative to photolithography features |
US7390746B2 (en) * | 2005-03-15 | 2008-06-24 | Micron Technology, Inc. | Multiple deposition for integration of spacers in pitch multiplication process |
US7611944B2 (en) * | 2005-03-28 | 2009-11-03 | Micron Technology, Inc. | Integrated circuit fabrication |
KR100640639B1 (ko) * | 2005-04-19 | 2006-10-31 | 삼성전자주식회사 | 미세콘택을 포함하는 반도체소자 및 그 제조방법 |
US7429536B2 (en) * | 2005-05-23 | 2008-09-30 | Micron Technology, Inc. | Methods for forming arrays of small, closely spaced features |
US7547599B2 (en) | 2005-05-26 | 2009-06-16 | Micron Technology, Inc. | Multi-state memory cell |
US7560390B2 (en) | 2005-06-02 | 2009-07-14 | Micron Technology, Inc. | Multiple spacer steps for pitch multiplication |
US7396781B2 (en) | 2005-06-09 | 2008-07-08 | Micron Technology, Inc. | Method and apparatus for adjusting feature size and position |
JP2006351861A (ja) * | 2005-06-16 | 2006-12-28 | Toshiba Corp | 半導体装置の製造方法 |
US7413981B2 (en) * | 2005-07-29 | 2008-08-19 | Micron Technology, Inc. | Pitch doubled circuit layout |
US7291560B2 (en) | 2005-08-01 | 2007-11-06 | Infineon Technologies Ag | Method of production pitch fractionizations in semiconductor technology |
US7816262B2 (en) * | 2005-08-30 | 2010-10-19 | Micron Technology, Inc. | Method and algorithm for random half pitched interconnect layout with constant spacing |
US7829262B2 (en) | 2005-08-31 | 2010-11-09 | Micron Technology, Inc. | Method of forming pitch multipled contacts |
US7572572B2 (en) * | 2005-09-01 | 2009-08-11 | Micron Technology, Inc. | Methods for forming arrays of small, closely spaced features |
US7393789B2 (en) * | 2005-09-01 | 2008-07-01 | Micron Technology, Inc. | Protective coating for planarization |
US7759197B2 (en) * | 2005-09-01 | 2010-07-20 | Micron Technology, Inc. | Method of forming isolated features using pitch multiplication |
US7776744B2 (en) * | 2005-09-01 | 2010-08-17 | Micron Technology, Inc. | Pitch multiplication spacers and methods of forming the same |
US7687342B2 (en) * | 2005-09-01 | 2010-03-30 | Micron Technology, Inc. | Method of manufacturing a memory device |
US7244638B2 (en) * | 2005-09-30 | 2007-07-17 | Infineon Technologies Ag | Semiconductor memory device and method of production |
KR101200938B1 (ko) | 2005-09-30 | 2012-11-13 | 삼성전자주식회사 | 반도체 장치의 패턴 형성 방법 |
KR100672123B1 (ko) * | 2006-02-02 | 2007-01-19 | 주식회사 하이닉스반도체 | 반도체 소자의 미세 패턴 형성방법 |
US20070210449A1 (en) * | 2006-03-07 | 2007-09-13 | Dirk Caspary | Memory device and an array of conductive lines and methods of making the same |
US7351666B2 (en) * | 2006-03-17 | 2008-04-01 | International Business Machines Corporation | Layout and process to contact sub-lithographic structures |
US7537866B2 (en) | 2006-05-24 | 2009-05-26 | Synopsys, Inc. | Patterning a single integrated circuit layer using multiple masks and multiple masking layers |
US7825460B2 (en) * | 2006-09-06 | 2010-11-02 | International Business Machines Corporation | Vertical field effect transistor arrays and methods for fabrication thereof |
US20080292991A1 (en) | 2007-05-24 | 2008-11-27 | Advanced Micro Devices, Inc. | High fidelity multiple resist patterning |
US7851135B2 (en) | 2007-11-30 | 2010-12-14 | Hynix Semiconductor Inc. | Method of forming an etching mask pattern from developed negative and positive photoresist layers |
-
2005
- 2005-08-31 US US11/215,982 patent/US7829262B2/en active Active
-
2006
- 2006-08-21 EP EP06790026A patent/EP1929508A2/en not_active Withdrawn
- 2006-08-28 WO PCT/US2006/033421 patent/WO2007027558A2/en active Application Filing
- 2006-08-28 KR KR1020107021228A patent/KR20100109985A/ko not_active Application Discontinuation
- 2006-08-28 KR KR1020087007708A patent/KR101003897B1/ko active IP Right Grant
- 2006-08-28 CN CN2006800394191A patent/CN101292327B/zh active Active
- 2006-08-28 JP JP2008529144A patent/JP5299678B2/ja active Active
- 2006-08-30 TW TW095132042A patent/TWI327746B/zh active
-
2010
- 2010-09-30 US US12/894,633 patent/US8426118B2/en active Active
-
2013
- 2013-03-28 US US13/852,275 patent/US8609324B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
EP1929508A2 (en) | 2008-06-11 |
TWI327746B (en) | 2010-07-21 |
WO2007027558A3 (en) | 2007-05-18 |
KR20080043861A (ko) | 2008-05-19 |
US20130210228A1 (en) | 2013-08-15 |
TW200721253A (en) | 2007-06-01 |
KR20100109985A (ko) | 2010-10-11 |
JP2009506576A (ja) | 2009-02-12 |
US8426118B2 (en) | 2013-04-23 |
US7829262B2 (en) | 2010-11-09 |
US20110014574A1 (en) | 2011-01-20 |
WO2007027558A2 (en) | 2007-03-08 |
CN101292327A (zh) | 2008-10-22 |
US20070049035A1 (en) | 2007-03-01 |
KR101003897B1 (ko) | 2010-12-30 |
CN101292327B (zh) | 2010-04-14 |
US8609324B2 (en) | 2013-12-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5299678B2 (ja) | ピッチ増倍コンタクトを形成する方法 | |
US20220262626A1 (en) | Methods of forming electronic devices using pitch reduction | |
US9099402B2 (en) | Integrated circuit structure having arrays of small, closely spaced features | |
US9412591B2 (en) | Process of semiconductor fabrication with mask overlay on pitch multiplied features and associated structures | |
KR101449772B1 (ko) | 효율적인 피치 멀티플리케이션 프로세스 | |
US8895232B2 (en) | Mask material conversion | |
US7455956B2 (en) | Method to align mask patterns | |
JP4945802B2 (ja) | ピッチ増倍を使用して製造された集積回路、及びその製造方法 | |
TWI503863B (zh) | 包含緊密間距接點的半導體結構及其形成方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20110907 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110913 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20111212 Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20111212 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120124 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20120423 Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120423 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20121204 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20130301 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20130301 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20130313 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130322 Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20130322 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20130514 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20130605 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5299678 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |