TW376582B - Method of forming COB DRAM with self-aligned pole and bitline contact plug - Google Patents
Method of forming COB DRAM with self-aligned pole and bitline contact plugInfo
- Publication number
- TW376582B TW376582B TW087110315A TW87110315A TW376582B TW 376582 B TW376582 B TW 376582B TW 087110315 A TW087110315 A TW 087110315A TW 87110315 A TW87110315 A TW 87110315A TW 376582 B TW376582 B TW 376582B
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- oxide
- silicon nitride
- bpsg
- self
- Prior art date
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
In a BPSG layer where a plug is formed between a gate structure and a word line, a poly layer, a tungsten silicide layer and a silicon oxide layer are sequentially formed on the BPSG layer. Next, a multi-layer structure is etched to the surface of the BPSG layer. The BPSG layer is slightly etched to expose a poly plug. An oxide spacer is formed on the sidewall of a film layer. A silicon nitride layer is formed on the bit line, the oxide spacer and the poly plug. An oxide layer is formed on the silicon nitride layer. The oxide layer is etched to form an electrode contact hole. A first conductive layer is formed along the surface of the oxide layer by etching the silicon nitride layer. A portion of the top end of the first conductive layer is removed. The oxide layer is removed to expose the silicon nitride layer. A dielectric film is deposited along the surface of the first conductive layer. Finally, a second conductive layer is formed on the dielectric film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW087110315A TW376582B (en) | 1998-06-26 | 1998-06-26 | Method of forming COB DRAM with self-aligned pole and bitline contact plug |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW087110315A TW376582B (en) | 1998-06-26 | 1998-06-26 | Method of forming COB DRAM with self-aligned pole and bitline contact plug |
Publications (1)
Publication Number | Publication Date |
---|---|
TW376582B true TW376582B (en) | 1999-12-11 |
Family
ID=57942018
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW087110315A TW376582B (en) | 1998-06-26 | 1998-06-26 | Method of forming COB DRAM with self-aligned pole and bitline contact plug |
Country Status (1)
Country | Link |
---|---|
TW (1) | TW376582B (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7795149B2 (en) | 2006-06-01 | 2010-09-14 | Micron Technology, Inc. | Masking techniques and contact imprint reticles for dense semiconductor fabrication |
US8003310B2 (en) | 2006-04-24 | 2011-08-23 | Micron Technology, Inc. | Masking techniques and templates for dense semiconductor fabrication |
US8043915B2 (en) | 2005-09-01 | 2011-10-25 | Micron Technology, Inc. | Pitch multiplied mask patterns for isolated features |
US8207614B2 (en) | 2005-05-23 | 2012-06-26 | Micron Technology, Inc. | Methods for forming arrays of small, closely spaced features |
US8211803B2 (en) | 2007-11-01 | 2012-07-03 | Micron Technology, Inc. | Spacer process for on pitch contacts and related structures |
US8266558B2 (en) | 2005-09-01 | 2012-09-11 | Micron Technology, Inc. | Methods for forming arrays of small, closely spaced features |
US8426118B2 (en) | 2005-08-31 | 2013-04-23 | Micron Technology, Inc. | Method of forming pitch multiplied contacts |
US10515801B2 (en) | 2007-06-04 | 2019-12-24 | Micron Technology, Inc. | Pitch multiplication using self-assembling materials |
-
1998
- 1998-06-26 TW TW087110315A patent/TW376582B/en not_active IP Right Cessation
Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8207614B2 (en) | 2005-05-23 | 2012-06-26 | Micron Technology, Inc. | Methods for forming arrays of small, closely spaced features |
US8426118B2 (en) | 2005-08-31 | 2013-04-23 | Micron Technology, Inc. | Method of forming pitch multiplied contacts |
US8609324B2 (en) | 2005-08-31 | 2013-12-17 | Micron Technology, Inc. | Method of forming pitch multiplied contacts |
US8043915B2 (en) | 2005-09-01 | 2011-10-25 | Micron Technology, Inc. | Pitch multiplied mask patterns for isolated features |
US8266558B2 (en) | 2005-09-01 | 2012-09-11 | Micron Technology, Inc. | Methods for forming arrays of small, closely spaced features |
US8601410B2 (en) | 2005-09-01 | 2013-12-03 | Micron Technology, Inc. | Methods for forming arrays of small, closely spaced features |
US10396281B2 (en) | 2005-09-01 | 2019-08-27 | Micron Technology, Inc. | Methods for forming arrays of small, closely spaced features |
US8003310B2 (en) | 2006-04-24 | 2011-08-23 | Micron Technology, Inc. | Masking techniques and templates for dense semiconductor fabrication |
US7795149B2 (en) | 2006-06-01 | 2010-09-14 | Micron Technology, Inc. | Masking techniques and contact imprint reticles for dense semiconductor fabrication |
US8449805B2 (en) | 2006-06-01 | 2013-05-28 | Micron Technology, Inc. | Masking techniques and contact imprint reticles for dense semiconductor fabrication |
US8663532B2 (en) | 2006-06-01 | 2014-03-04 | Micron Technology, Inc. | Masking techniques and contact imprint reticles for dense semiconductor fabrication |
US10515801B2 (en) | 2007-06-04 | 2019-12-24 | Micron Technology, Inc. | Pitch multiplication using self-assembling materials |
US8211803B2 (en) | 2007-11-01 | 2012-07-03 | Micron Technology, Inc. | Spacer process for on pitch contacts and related structures |
US8772166B2 (en) | 2007-11-01 | 2014-07-08 | Micron Technology, Inc. | Spacer process for on pitch contacts and related structures |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |