TW376582B - Method of forming COB DRAM with self-aligned pole and bitline contact plug - Google Patents

Method of forming COB DRAM with self-aligned pole and bitline contact plug

Info

Publication number
TW376582B
TW376582B TW087110315A TW87110315A TW376582B TW 376582 B TW376582 B TW 376582B TW 087110315 A TW087110315 A TW 087110315A TW 87110315 A TW87110315 A TW 87110315A TW 376582 B TW376582 B TW 376582B
Authority
TW
Taiwan
Prior art keywords
layer
oxide
silicon nitride
bpsg
self
Prior art date
Application number
TW087110315A
Other languages
Chinese (zh)
Inventor
Hong-Yi Luo
xiang-yuan Zheng
Yue-Feng Chen
Original Assignee
Vanguard Int Semiconduct Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Vanguard Int Semiconduct Corp filed Critical Vanguard Int Semiconduct Corp
Priority to TW087110315A priority Critical patent/TW376582B/en
Application granted granted Critical
Publication of TW376582B publication Critical patent/TW376582B/en

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

In a BPSG layer where a plug is formed between a gate structure and a word line, a poly layer, a tungsten silicide layer and a silicon oxide layer are sequentially formed on the BPSG layer. Next, a multi-layer structure is etched to the surface of the BPSG layer. The BPSG layer is slightly etched to expose a poly plug. An oxide spacer is formed on the sidewall of a film layer. A silicon nitride layer is formed on the bit line, the oxide spacer and the poly plug. An oxide layer is formed on the silicon nitride layer. The oxide layer is etched to form an electrode contact hole. A first conductive layer is formed along the surface of the oxide layer by etching the silicon nitride layer. A portion of the top end of the first conductive layer is removed. The oxide layer is removed to expose the silicon nitride layer. A dielectric film is deposited along the surface of the first conductive layer. Finally, a second conductive layer is formed on the dielectric film.
TW087110315A 1998-06-26 1998-06-26 Method of forming COB DRAM with self-aligned pole and bitline contact plug TW376582B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW087110315A TW376582B (en) 1998-06-26 1998-06-26 Method of forming COB DRAM with self-aligned pole and bitline contact plug

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW087110315A TW376582B (en) 1998-06-26 1998-06-26 Method of forming COB DRAM with self-aligned pole and bitline contact plug

Publications (1)

Publication Number Publication Date
TW376582B true TW376582B (en) 1999-12-11

Family

ID=57942018

Family Applications (1)

Application Number Title Priority Date Filing Date
TW087110315A TW376582B (en) 1998-06-26 1998-06-26 Method of forming COB DRAM with self-aligned pole and bitline contact plug

Country Status (1)

Country Link
TW (1) TW376582B (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7795149B2 (en) 2006-06-01 2010-09-14 Micron Technology, Inc. Masking techniques and contact imprint reticles for dense semiconductor fabrication
US8003310B2 (en) 2006-04-24 2011-08-23 Micron Technology, Inc. Masking techniques and templates for dense semiconductor fabrication
US8043915B2 (en) 2005-09-01 2011-10-25 Micron Technology, Inc. Pitch multiplied mask patterns for isolated features
US8207614B2 (en) 2005-05-23 2012-06-26 Micron Technology, Inc. Methods for forming arrays of small, closely spaced features
US8211803B2 (en) 2007-11-01 2012-07-03 Micron Technology, Inc. Spacer process for on pitch contacts and related structures
US8266558B2 (en) 2005-09-01 2012-09-11 Micron Technology, Inc. Methods for forming arrays of small, closely spaced features
US8426118B2 (en) 2005-08-31 2013-04-23 Micron Technology, Inc. Method of forming pitch multiplied contacts
US10515801B2 (en) 2007-06-04 2019-12-24 Micron Technology, Inc. Pitch multiplication using self-assembling materials

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8207614B2 (en) 2005-05-23 2012-06-26 Micron Technology, Inc. Methods for forming arrays of small, closely spaced features
US8426118B2 (en) 2005-08-31 2013-04-23 Micron Technology, Inc. Method of forming pitch multiplied contacts
US8609324B2 (en) 2005-08-31 2013-12-17 Micron Technology, Inc. Method of forming pitch multiplied contacts
US8043915B2 (en) 2005-09-01 2011-10-25 Micron Technology, Inc. Pitch multiplied mask patterns for isolated features
US8266558B2 (en) 2005-09-01 2012-09-11 Micron Technology, Inc. Methods for forming arrays of small, closely spaced features
US8601410B2 (en) 2005-09-01 2013-12-03 Micron Technology, Inc. Methods for forming arrays of small, closely spaced features
US10396281B2 (en) 2005-09-01 2019-08-27 Micron Technology, Inc. Methods for forming arrays of small, closely spaced features
US8003310B2 (en) 2006-04-24 2011-08-23 Micron Technology, Inc. Masking techniques and templates for dense semiconductor fabrication
US7795149B2 (en) 2006-06-01 2010-09-14 Micron Technology, Inc. Masking techniques and contact imprint reticles for dense semiconductor fabrication
US8449805B2 (en) 2006-06-01 2013-05-28 Micron Technology, Inc. Masking techniques and contact imprint reticles for dense semiconductor fabrication
US8663532B2 (en) 2006-06-01 2014-03-04 Micron Technology, Inc. Masking techniques and contact imprint reticles for dense semiconductor fabrication
US10515801B2 (en) 2007-06-04 2019-12-24 Micron Technology, Inc. Pitch multiplication using self-assembling materials
US8211803B2 (en) 2007-11-01 2012-07-03 Micron Technology, Inc. Spacer process for on pitch contacts and related structures
US8772166B2 (en) 2007-11-01 2014-07-08 Micron Technology, Inc. Spacer process for on pitch contacts and related structures

Similar Documents

Publication Publication Date Title
JP4585309B2 (en) Semiconductor processing method for forming a contact pedestal for a storage node of an integrated circuit capacitor
US7101783B2 (en) Method for forming bit-line of semiconductor device
US6010941A (en) Method of forming a capacitor
US7008843B2 (en) Methods of forming memory circuitry
KR100363710B1 (en) Semiconductor device with self-aligned contact structure and method of manufacturing the same
KR970003953A (en) Highly Integrated DRAM Cells and Manufacturing Method Thereof
TW373324B (en) A method of fabricating DRAM cell capacitor
US6242301B1 (en) Capacitor and conductive line constructions and semiconductor processing methods of forming capacitors and conductive lines
KR20040060402A (en) A method for forming a contact of a semiconductor device
TW376582B (en) Method of forming COB DRAM with self-aligned pole and bitline contact plug
KR20040035213A (en) Semiconductor device and method for fabricating the same using damascene process
US5491104A (en) Method for fabricating DRAM cells having fin-type stacked storage capacitors
KR20020066586A (en) Method for forming the bit line in semiconductor device
US6271099B1 (en) Method for forming a capacitor of a DRAM cell
US20040016957A1 (en) Scalable stack-type dram memory structure and its manufacturing methods
EP1137063A2 (en) Gate electrode for DRAM transistor
US5204281A (en) Method of making dynamic random access memory cell having a trench capacitor
US20010044192A1 (en) Method for manufacturing stacked capacitor with stable capacitor lower electrode
TW346672B (en) Method for fabricating a semiconductor memory cell in a DRAM
KR100325288B1 (en) Capacitor and method for manufacturing the same
KR100518232B1 (en) Method for producting semiconductor device
KR20040079171A (en) Method for manufacturing semiconductor device
KR20020002745A (en) Method for forming a bit line of a semiconductor device
TW416126B (en) Manufacturing method for integrating metal silicide and self-aligned contact
KR20010003287A (en) A method of fabricating semiconductor device

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees