TW416126B - Manufacturing method for integrating metal silicide and self-aligned contact - Google Patents

Abstract

There is disclosed a manufacturing method for integrating metal silicide and self-aligned contact, used in embedded dynamic random access memory. The method first forms a first gate whose top layer has a hard mask layer and whose two sides has a first insulating space layer, and a first source/drain region. Then, there is formed a first covering layer whose material is different from that of the first insulating space layer, so as to cover the memory cell region. Next, there are defined a second gate whose two sides have a second insulating space layer in the logic circuit region, and a second source/drain region. Then, there is formed a metal silicide layer on the surface of the second gate and the second source/drain region. Subsequently, a second covering layer is formed to cover the logic circuit region. Then, the first insulating space layer of the first gate and the mask layer are used as a mask to define a first covering layer, thereby forming a self-aligned contact exposing the first source/drain region. Accordingly, it is able to form the gate and source/drain of metal silicide in the logic circuit region, and also form the self-aligned contact in the memory cell region.

Description

416126 V. Description of the invention (1) The present invention relates to a method for manufacturing a semi-conductor memory device, and more particularly to a method for embedded dynamic random access memory. DRAM) integrated metal silicide and self-aligned contact window manufacturing method. The conventional logic device and the memory device are respectively formed on different chips and then set on a circuit board. Due to the structure of the memory device and logic device formed on different chips, the high-speed performance cannot be ensured. Therefore, a device that mixes I ”and logic devices on the same chip has been proposed. Such a device is called a AND A Λ-type JL memory device, such as an eRAM (embedded random access memory) device. Generally speaking, logic circuits require high execution speed, and memory devices require high density. However, as the size of semiconductor devices continues to shrink, logic circuits with high execution speed and high-density memory are required in embedded semiconductor memory devices. Obviously, installation is becoming increasingly difficult. In view of this, the present invention provides a method for manufacturing a semiconductor memory device, which will consist of integrating metal ... and a self-aligned contact window V-form: which forms a metal silicide gate in a road area. Poles and source / drain electrodes to improve execution speed. At the same time, there is no area in the memory-mepan exhibition, self-aligning the contact window to reduce the memory. The invention provides an integrated metal silicide and self-aligned contact window for embedded mobile and random access memory. __ 5. Description of the invention (2) Manufacturing method, which is firstly in the memory cell area A first gate having a hard mask layer on the top layer and a first insulating spacer layer on both sides is formed, and a first-first source / drain region. A first cover layer of a different material from the first insulating spacer layer is then formed to cover the memory cell area. Second, a second gate having a second insulating spacer layer on both sides and a second source / drain region are defined in the logic circuit region. Then, a metal silicide layer is formed on the surface of the second gate and the second source / drain region, and then a second cover layer is formed to cover the logic circuit area. Then, the first insulating spacer layer and the hard The mask layer is a mask and defines a first cover layer to form a self-aligned contact window exposing the first source / drain region. This not only forms metal silicide gates and source / drain electrodes in the logic circuit area, but also forms self-aligned contact windows in the memory cell area. The invention is described below with reference to the drawings and preferred embodiments. Brief Description of the Drawings Figs. 1 to 11 are cross-sectional views of a manufacturing process of an embedded dynamic random access memory according to a preferred embodiment of the present invention. [Explanation of symbols] 100 ~ semiconductor substrate; 150, 152, 154 ~ source / drain; G1-G5-gate; 160a, 160b ~ nitride spacer layer; 139 ~ nitride liner layer; 170 ~ oxide Cover layer; 180, 180, 184, 186 ~ source / drain; G7 ~ gate; 188a, 188b ~ oxide spacer; 120 ~ metal silicide; 210 ~ nitrogen oxide liner; 220 ~ oxide 230, 232 ~ contact holes; 240, 242 ~ conductive material pads; 254 ~ polycrystalline silicon plugs; 2 70'275 ~ metal plugs; 0 capacitors; 280 ~ metal interconnects. Ι · Π · Γ Page 6άΑ31Zβ -----: V. Description of the Invention (3) Example The following uses the manufacturing flow sectional view of the embedded dynamic random access memory of FIGS. 1 to 11 to explain the present invention. Of an embodiment. First, as shown in FIG. 1, a substrate having a memory cell region such as a dynamic random access memory (⑽am) region and a logic circuit region is defined. Among them, FIG. 1 shows that a semiconductor substrate such as a silicon substrate is formed with a plurality of substrates. Shallow trench isolation (STI) is used to isolate the active area. Then, taking an n-type semiconductor stone substrate as an example, P-type ions, such as butterfly ions, are implanted into the active region in the broken substrate 100 by ion implantation to form a p-well region. Secondly, the semiconductor process is performed according to the steps of FIGS. 1 to 5 to form a free electrode G1-G5 with a hard mask layer 138 in the memory cell region of FIG. 5 and insulating spacers 160b and Source / drain regions 150, 152, 154. Then, a cover layer 170 of a different material from the insulating spacer layer 160b is formed to cover the memory cell area, as described below. First, please refer to the surface shown in FIG. 1, which first uses a dry or wet thermal oxidation method on An oxide layer 110 is grown on the surface of the silicon substrate 100, and then a chemical vapor deposition (CVD) method is used to comprehensively deposit a polycrystalline silicon layer 112 and an oxide layer 11 4 ′. The oxide layer 114 is an optional step. Then, a lithographic process is used to define a patterned photoresist 120. If a photoresist is coated first, a patterned photoresist 120 is formed on the surface of the logic circuit area after exposure and development. Then, according to Fig. 2 ', the insulating layer 11 0 and the conductive layer 112 in the logic circuit area are defined. For example, using a patterned photoresist 1 20 as a mask, use the remaining step ’such as an anisotropic dry etching process to remove oxygen located on the surface of the DRAM area.

Five butterflies-η chemical slaughter 110, polycrystalline fragment II, and oxide layer 114. Accordingly, the patterned photoresist 120 is removed. Next, according to FIG. 3, an insulating layer 130, a conductive layer 132/134, a buffer layer 136, and a hard cover curtain layer 138 are comprehensively formed. For example, a dry or wet thermal oxidation method is used to grow an oxide layer 130 on the surface of the silicon substrate 100, and then a chemical vapor deposition (CVD) method is used to comprehensively deposit a polycrystalline silicon layer 1 3 2 and tungsten silicide. The layers 134 ', the oxide layer 136, and the silicon nitride layer 138, wherein the tungsten silicide layer 134 and the oxide layer 114 are selective steps. Then according to Fig. 4, the insulating layer 130, the conductive layer 132/134, the buffer layer 136, and the hard mask layer 138 are defined in the memory cell area to form the gate electrodes G1, G2, G3, G4, and G5. For example, a patterned photoresist 140 is first defined by a lithography process. For example, a layer of photoresist is coated, and a patterned photoresist 140 is formed on the surface of the DR AM region after exposure and development. Then, the patterned photoresist 140 is used as a mask to “remove the step” such as an anisotropic dry etching process to remove the exposed oxide layer 130, the polycrystalline silicon layer 132, the tungsten silicide layer 134, and the oxide layer located on the surface of a part of the DRAM area. The layers 136 and the silicon nitride layer 138 form gates G1, G2, G3, G4, and G5. Accordingly, the patterned photoresist 14 is removed. Successively, according to Fig. 5 ', an insulating spacer 160b and source / drain regions 150, 152, 154 are formed on both sides of the gates g1 to G5. Then, a cover layer 70 of a different material from the insulating spacer layer 160b is formed to cover the DRAM area. For example, 'a silicon nitride layer is conformally deposited using a chemical vapor deposition process, and a silicon nitride spacer layer 160b is formed on both sides of the gate electrodes G1 to G5 through a back-etching step, and another side wall of the logic circuit region is formed. The silicon nitride spacer layer 16a, wherein a source /

Page 8 V. Description of the invention (5) Drain regions 150, 152, 154, or a source with lightly doped regions can be formed through two ion implantation steps and selection of silicon nitride spacer layer 160b as a mask / Drain. Then, a pad layer 139 is formed in an all-round manner. For example, in a chemical vapor deposition process, a silicon nitride pad layer 139 is compliantly deposited on the surfaces of the foregoing layers. The silicon nitride pad layer 139 is an optional step. Then, a capping layer 1 70 'of a different material from the insulating spacers 16Oa, 1 60b is formed to cover the DRAM area. For example, an oxide layer is deposited using a chemical vapor deposition process to cover the logic circuit area and the DRAM area, and then the oxide layer 170 is planarized by a planarization step such as a chemical mechanical polishing process or an etch-back step. Secondly, please refer to FIG. 6, a gate G 7 is defined in a logic circuit area, and insulating spacer layers 1 8 8 a and source / drain regions 1 8 0, 1 8 2, 184, 186 are defined on both sides. For example, the lithography process and the money engraving step are used to sequentially remove the conductive layers 132/134, the buffer layer 136, and the hard mask layer 138 located in the logic circuit area, and then define the insulating layer 110 and the conductive layer 112 to form the gate G7. Then, an insulating spacer layer 188a and source / inverted regions 1 0 0, 1 8 2, 1 8 4, and 18 6 are formed on both sides of the gate G7. For example, firstly, an oxide layer is compliantly deposited using a chemical vapor deposition process, and an oxide spacer layer 18 8 a is formed on both sides of the gate G7 through the step of engraving, and another oxide spacer is formed on the sidewall of the memory cell region. Layer 1 88b 'wherein, source / inverted regions 180, 182, 184, 186 can be formed on both sides of the gate G7 through an ion implantation step, or through two ion implantation steps' and an oxide spacer layer is selected 188a is a mask, forming a source / drain region with a lightly doped region.

4 ^ 6126 5. Description of the invention (6) Next, referring to FIG. 7, a metal silicide layer 2 0 0 is formed on the surface of the gate 188a and the source / drain regions ι80, 182, 184, and ι86 using a metal silicide process. For example, 'a metal layer is formed comprehensively to cover the surface of the cover layer 170 of the memory cell region-domain and the gate 188 & of the logic circuit region, the source / drain regions 180, 182, 184, 186, and shallow trench isolation. Area (STI) surface, for example, a direct current (DC) magnetron sputtering process is used to fully deposit a metal layer with good oxygen absorption capacity, such as a metal titanium, cobalt or platinum layer. Here, a titanium metal layer is used as an example. In order to be able to react with silicon to form titanium silicide at an appropriate temperature, and to form a low-resistance compound by cross-diffusion, a good ohmic contact can be formed between the silicon and titanium interfaces. Therefore, after the metal layer is deposited, a first thermal process such as a rapid thermal annealing process (RTP) is first performed. The temperature is about 600 ° C to 650 ° C. After this thermal annealing step, the titanium silicide compound 200 is formed on the surfaces of the titanium, the polycrystalline silicon gate G7, and the source / drain electrodes 180, 182, 184, and 186. Then, a selective etching process, such as a wet etching process, is used to remove the remaining titanium metal layer that has not reacted with silicon. Second, a second thermal process, such as a rapid thermal annealing process (RTP), is performed, and the temperature is about goot to 900. Between ^ Through this thermal annealing step, the resistance of the dream titanium compound 200 on the surface of the polycrystalline silicon gate G7 and the source / drain regions 180, 182, 184, and 186 can be reduced. Then, please refer to the semiconductor process steps in FIGS. 8 to 10, in the “circle” to comprehensively form the pad insulation layer 21 and the cover layer 220 of a different material to cover the memory cell area and the logic circuit area. After planarization, a through-layer is formed in the memory cell area and the source /

Page 10 61P.fi_ V. Description of the invention (7) ^ The pad regions 152, 154 are electrically connected to the conductive material pads 24, 242, such as doped dopedite material, as described below. First, according to the cross-section of FIG. 8, a silicon nitride oxide layer 210 and a cover layer 220 are comprehensively formed to cover the ram area and the logic circuit area. For example, in a chemical vapor deposition process, a silicon oxynitride liner layer 2 i 0 is first conformally deposited on the surfaces of the foregoing layers, and the 'silicon oxynitride liner layer 21o is a selective step. Then, a high density plasma deposition process (HDp) is used to deposit an oxide layer 220 to cover the logic circuit area * DRAM area. _ Next, please refer to FIG. 9 'for planarizing the silicon oxynitride layer 210 and the cover layer 220, such as a chemical mechanical polishing process or an etch-back step, to planarize the cover layer 220 and the cover layer 17 of the memory cell region. Secondly, in the DRAM region ', a lithography process and an etching step are used, and an insulating spacer layer 160b and a hard mask layer 138 are used as a mask, and a silicon nitride liner layer is used. Etch end point detection is performed, and a cover layer is defined to form self-aligned contact windows 230, 232 exposing the source / drain regions 152, 154. Next, please refer to FIG. 10 'form a conductive material pad 240, 242, such as a doped polycrystalline silicon material pad', which is filled with self-aligned contact windows 23 and 232, and is connected to the source and terminal regions 1 5 2, 1 5 4 Electrical connection. Then refer to Figure 11 to complete the subsequent process of embedded dynamic random access memory. For example, a conductive layer 252 electrically connected to the conductive material pad 240 is used as the bit line BL. For example, an insulating layer 250 can be formed comprehensively, such as an oxide layer formed by a low-pressure chemical vapor deposition method. . Then, the insulating layer 250 is selectively etched to form a bit line contact hole exposing the conductive material pad 240b. Next, in the above-mentioned contact hole formation example

Μ ΨΛ «Λ 1 τη \ < Λ I is a conductive layer 2 52 composed of polycrystalline silicon / tungsten silicide to be used as a bit line BL. Then, the insulating layer 256 is formed comprehensively to cover the insulating layer 25 and the conductive layer 252 as the bit line BL. A capacitor C is then formed in the memory cell area through the insulating layers 256, 250 and electrically connected to the conductive material pad 242. The capacitor C generally includes a plug 254 composed of polycrystalline stone and a lower electrode 266 '. A dielectric layer 264 composed of a silicon layer / a silicon nitride layer / a silicon dioxide layer (ON); and an upper electrode 262 composed of a polycrystalline silicon layer. Next, after the capacitor C is completed, a thick insulating layer 26 is formed comprehensively. For example, a chemical vapor deposition process may be used to deposit an oxide layer 26 and then planarize it. Then, the silicon nitride oxide liner layer 2 is used for end-of-etch detection. The above-mentioned insulating layers 26 (), '256, 250, 220, and 170 are defined by a lithography process and a dry etching step to form an exposed source / drain. The contact hole on the surface of the metal dream layer of the electrode 186 and the contact hole on the surface of the tungsten silicide layer exposed from the gate. Next, a contact plug 27 () electrically connected to one of the source / drain electrodes 186 and a contact plug 275 electrically connected to the surface of the tungsten silicide layer 134 of the gate G1 are formed in the logic circuit area, respectively. For example, contact plugs made of metal tungsten. Next, a metal interconnect 280 'is defined on the surface of the insulating layer 26, and is electrically connected to the tungsten plugs 270 and 275. The effects improved by the present invention include the following. (1) Metal silicides in the logic circuit area and memory

Page 12 The self-alignment of the contact area of the body cell area can make the logic circuit have a higher execution-speed at the same time .... (1) It is necessary to form closed polar nitrogen at different thicknesses in the logic drop. Floor. The description of the fifth invention (9) (3) It is necessary to form gate spacers of different widths at the time of delay. (4) In the logic circuit region and the memory cell region, different lightly doped regions may be formed respectively as required. (5) In the area of the logical mine road and the area of the chair, the lining layer Γ of material and thickness can be separately formed as the etch stop layer that defines the gold over-contact, hole, and self-aligned contact hole. To prevent the phenomenon of overetching. Π — 较佳 Ϊ The present invention has been disclosed in the preferred embodiment as above. Without the i A limiter of the present invention, anyone who is familiar with this technology ... is not intended to be used as a patent application attached to the attached = Protection of the invention "

Claims (1)

6. Scope of Patent Application 1. An integrated metal fragmentation and self-discipline method, which includes the following steps: 1. Manufacturing of the quasi-contact window a) Define a base with a memory cell area and a logic circuit area (b) in the memory Body unit region formation-ts & β β # & war gate top layer with hard cover and first insulation spacer on both sides, and a first source / drain region, (c) forming a A first covering layer of a different material from the first insulating spacer layer to cover the memory cell region; (d) forming a second gate electrode having a second insulating spacer layer on both sides of the logic circuit region; and A second source / dead region; (e) forming a metal debris layer on the surface of the first and second source / dead regions; (f) forming a second cover layer to cover the logic circuit region And (g) using the first insulating spacer layer of the first gate electrode and the hard mask layer as a mask to define the first cover layer to form a self-aligned contact window exposing the first source / drain region. 2. The manufacturing method according to item 1 of the scope of patent application, wherein in step (b), the first gate top layer of the memory cell region includes a silicon nitride hard mask curtain layer. 3_ The manufacturing method as described in item 2 of the patent application scope, wherein in step (b), both sides of the third gate of the memory cell region include a silicon nitride spacer layer. 4. The manufacturing method described in item 3 of the scope of patent application, which is executed in step 6126. Step (c), the first covering layer is an oxide layer. 5. The manufacturing method as described in item 1 of the scope of patent application, wherein step (b) 'further includes a step of forming a lining according to compliance. * 6. The manufacturing method as described in item 5 of the scope of patent application, wherein in step (b), the pad layer is a siliconized silicon layer. 7. The manufacturing method according to item 1 of the scope of patent application, wherein in step (d), both sides of the second gate electrode of the logic circuit region include an oxide & barrier layer. 8. The manufacturing method as described in item 7 of the scope of patent application, wherein in step (e) ′, the metal oxide layer is; b. 9. The manufacturing method according to item 8 of the scope of patent application, wherein step (e) 'further includes a step of forming a lining layer conformably. 10. The manufacturing method according to item 9 of the patent application park, wherein in step (e) ′, the liner layer is an oxynitride layer. 11. The manufacturing method according to item 10 of the scope of patent application, wherein in step (f), the second covering layer is a high-density plasma oxide layer. 12. —A method for manufacturing a metal silicide and a self-aligned contact window 'is applicable to a substrate having a memory cell region and a logic circuit region, and includes the following steps: Ca) forming a first insulation in the logic circuit region Layer and a first conductive layer; (b) comprehensively forming a second insulating layer, a second conductive layer, and a hard mask layer; (0) defining the second insulating layer, the second conductive layer, and the hard mask layer layer, 416126 Six 'application for patent scope to form a first gate electrode in the memory cell area; (d) forming a first insulating spacer layer and source / > and pole regions on both sides of the first gate electrode, C e) formation A second insulation layer of a different material from the first insulation spacer layer to cover the memory cell area; the CO removes the second insulation layer, the two conductive layers and the hard cover curtain layer left in the logic circuit area, and Define the first insulating layer and the first to form a second gate; β (g) form a second insulating spacer and a second source on both sides of the second gate / (h) between the second gate and A metal oxide layer is formed on the surface of the second source / drain region; (i) a fourth insulating layer is formed to cover the logic circuit area; and (j) the first insulating spacer layer and the hard mask layer are used as the mask A third insulating layer is defined to form a self-aligned contact window exposing the first source / drain region. 13. The manufacturing method according to item 12 of the scope of patent application, wherein in step (a) 'the first insulating layer is an oxide layer' and the first conductive layer is a polycrystalline silicon layer. 14. The manufacturing method according to item 13 of the scope of patent application, wherein in step (b), 'the second insulating layer is an oxide layer', the second conductive layer is a polycrystalline stone layer, and the hard mask layer is nitrogen. Transformation; 5th floor. 15. The manufacturing method according to item 14 of the scope of the patent application, wherein in step (d), the first insulating spacer layer is a nitride nitride spacer layer. 16. The manufacturing method described in item 15 of the scope of patent application, wherein 416126 VI. Scope of Patent Application Step (d) further includes the step of compliantly depositing a silicon nitride liner layer. 17. The manufacturing method as described in item 16 of the scope of patent application, wherein in step (e), the third insulating layer is an oxide layer. 18. The manufacturing method according to item 17 of the scope of patent application, wherein in step (g), the second insulating spacer layer is a silicon oxide spacer layer. 19. The manufacturing method according to item 18 of the scope of patent application, wherein the step (g) further comprises a step of compliantly depositing a silicon nitride oxide liner layer. 20. The manufacturing method according to item 19 of the scope of patent application, wherein in step (i), the fourth insulating layer is a silicon oxide layer. Page 17