KR100518232B1 - Method for producting semiconductor device - Google Patents
Method for producting semiconductor device Download PDFInfo
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- KR100518232B1 KR100518232B1 KR10-2003-0064362A KR20030064362A KR100518232B1 KR 100518232 B1 KR100518232 B1 KR 100518232B1 KR 20030064362 A KR20030064362 A KR 20030064362A KR 100518232 B1 KR100518232 B1 KR 100518232B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
Abstract
본 발명은 반도체소자의 제조방법을 개시한다. 개시된 본 발명은 소정의 하지층이 형성된 반도체 기판 상에 베리어막, 텅스텐막과 하드 마스크막용 산화막 및 질화막을 차례로 형성하는 단계; 상기 하드마스크용 질화막, 산화막, 텅스텐막 및 베리어막을 패터닝하여 비트라인을 형성하는 단계; 상기 기판 결과물을 산화시켜 상기 텅스텐막 측벽에 산화막을 형성하는 단계; 상기 측벽 산화막을 포함한 비트라인의 양측벽에 제 1질화막 스페이서를 형성하는 단계; 상기 기판 결과물 상에 절연막을 형성하는 단계; 상기 절연막을 식각하여 비트라인 사이 영역을 노출시키는 콘택홀을 형성하는 단계; 상기 콘택 홀의 측벽에 제 2질화막 스페이서를 형성하는 단계; 및 측벽에 제 2산화막 스페이서가 형성된 콘택 홀 내에 도전막을 매립시켜 스토리지 콘택을 형성하는 단계;를 포함한다. 본 발명에 따르면, 소자제조공정을 진행할 때, 비트라인을 구성하는 텅스텐라인 측벽에 산화막을 형성하여 비트라인의 기생 캐패시터를 감소시켜 반도체소자의 동작특성을 향상시킬 수 있다.The present invention discloses a method for manufacturing a semiconductor device. The present invention includes the steps of sequentially forming a barrier film, a tungsten film, an oxide film for a hard mask film, and a nitride film on a semiconductor substrate on which a predetermined base layer is formed; Patterning the hard mask nitride film, oxide film, tungsten film and barrier film to form a bit line; Oxidizing the substrate resultant to form an oxide film on the tungsten film sidewalls; Forming first nitride layer spacers on both sidewalls of the bit line including the sidewall oxide layer; Forming an insulating film on the substrate resultant; Etching the insulating film to form a contact hole exposing a region between bit lines; Forming a second nitride film spacer on sidewalls of the contact hole; And forming a storage contact by filling the conductive layer in a contact hole in which the second oxide spacer is formed on the sidewall. According to the present invention, when the device manufacturing process is performed, an oxide film is formed on the sidewall of the tungsten line constituting the bit line, thereby reducing the parasitic capacitor of the bit line, thereby improving operating characteristics of the semiconductor device.
Description
본 발명은 반도체소자의 제조방법에 관한 것으로서, 보다 상세하게는 반도체 소자제조시에 비트라인을 사용하는 텅스텐라인의 기생 캐패시터 값을 감소시켜서 소자동작특성을 개선하는 반도체소자의 비트라인 형성방법에 관한 것이다 .BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a bit line of a semiconductor device, which improves device operation characteristics by reducing parasitic capacitor values of tungsten lines using bit lines in semiconductor device manufacturing. will be .
일반적으로, 반도체소자의 비트라인은 반도체기판상에 게이트 전극라인주변에 형성되어 상기 게이트전극은 트랜지스터기능을 담당하며 상기 비트라인은 메모리소자에서 데이터가 in/out 되는 동작기능을 담당하게 된다.In general, a bit line of a semiconductor device is formed around a gate electrode line on a semiconductor substrate so that the gate electrode is responsible for a transistor function and the bit line is responsible for an operation function of data in / out from a memory device.
이러한 종래기술에 따른 반도체소자의 제조방법에 대해 도 1을 참조하여 설명하면 다음과 같다.A method of manufacturing a semiconductor device according to the related art will be described with reference to FIG. 1 as follows.
도 1은 종래기술에 따른 반도체소자의 제조방법을 설명하기 위한 공정단면도이다.1 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to the prior art.
도 1에 도시된 바와같이, 반도체 기판(10)상에 STI공정을 진행하여 소자분리막(11)을 형성하고 상기 소자분리막(11)을 포함하는 기판(10)구조 전면 상에 소자분리막과 비트라인을 연결하는 산화막(13)과 LPC(Landing Plug Contact)막(15)을 형성한다.As shown in FIG. 1, an STI process is performed on a semiconductor substrate 10 to form an isolation layer 11, and an isolation layer and a bit line on the entire surface of the substrate 10 structure including the isolation layer 11. An oxide film 13 and an LPC (Landing Plug Contact) film 15 are formed.
그다음, 상기 산화막(13)을 포함하는 기판 상부에 BPSG막(17)을 증착하고 상기 BPSG막(17)내에 금속 베리어막(27)을 형성한 후 상기 금속 베리어막(27) 상부에 텅스텐막(19)과 하드마스크로 질화막(21)을 형성하고 상기 텅스텐막(19)측벽에 스페이서(25)를 형성하여 상기 텅스텐막(19)으로 이루어지는 비트라인을 형성한다.Next, a BPSG film 17 is deposited on the substrate including the oxide film 13, a metal barrier film 27 is formed in the BPSG film 17, and then a tungsten film is formed on the metal barrier film 27. 19 and a hard mask to form a nitride film 21 and a spacer 25 on the side wall of the tungsten film 19 to form a bit line made of the tungsten film 19.
이후에, 상기 비트라인을 포함하는 상부구조를 덮는 매립산화막(23)을 증착하고 후속으로 금속배선라인 형성공정을 진행한다.Subsequently, the buried oxide film 23 covering the upper structure including the bit line is deposited and the metal wiring line forming process is subsequently performed.
그러나, 상기 종래기술에 따른 반도체소자의 제조방법에 의하면, 도 1의 도면부호 "A"에 도시된 바와 같이, 반도체소자가 직접화되는 경향으로 인하여 상기 메모리의 비트라인과 비트라인 또는 비트라인과 비트라인사이의 절연막기능을 하는 SNC(Storage Node Contact) 폴리막 사이의 거리가 가까와지면서 비트라인에서 감지되는 기생 캐패시터의 크기가 점점 증가하는 문제점이 발생하게 된다.However, according to the method of manufacturing a semiconductor device according to the related art, as shown by reference numeral "A" of FIG. 1, the bit line and the bit line or the bit line and As the distance between the storage node contact (SNC) polylayers acting as an insulating layer between the bit lines increases, the size of the parasitic capacitors detected in the bit lines increases.
특히, SAC(Self Aligned Contact)에치공정을 진행할 경우는 유전율이 높은 절연막인 질화물질을 사용하기 때문에 비트라인 캐패시터가 더욱 증가된다.In particular, when the self-aligned contact (SAC) etching process is performed, a bit line capacitor is further increased because a nitride material, which is an insulating film having a high dielectric constant, is used.
이에 본 발명은 상기 종래기술의 제반 문제점을 해결하기 위하여 안출된 것으로서, 비트라인 측벽에 유전율이 낮은 산화막을 형성하여 비트라인 캐패시터 값을 감소시키어 소자동작특성을 개선하는 반도체소자의 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems of the prior art, to provide a method for manufacturing a semiconductor device to improve the device operating characteristics by reducing the bit line capacitor value by forming an oxide film having a low dielectric constant on the sidewall of the bit line The purpose is.
상기 목적을 달성하기 위하여 본 발명에 따른 반도체소자의 비트라인 형성방법은 반도체기판 상에 형성된 랜딩 플러그 폴리막 및 제 1 산화막을 덮는 절연막을 형성하고 패터닝하여 비트라인 콘택트 홀을 형성하는 단계와, 상기 비트라인 콘택트 홀의 내부 표면을 포함하는 상기 절연막 상에 베리어막, 텅스텐막, 제 2 산화막 및 하드 마스크막용 질화막을 차례로 형성하는 단계; 상기 하드마스크용 질화막, 제 2 산화막, 텅스텐막 및 베리어막을 패터닝하여 비트라인을 형성하는 단계; 상기 텅스텐막의 노출된 측면을 산화하여 측벽산화막을 형성하는 단계; 상기 측벽산화막을 포함한 비트라인의 양측면에 제 1질화막 스페이서를 형성하는 단계; 상기 제 1질화막 스페이서 사이의 절연막을 식각하여 상기 랜딩 플러그 폴리막을 노출시키는 스토리지 노드 콘택 홀을 형성하는 단계; 상기 제 1질화막 스페이서의 표면 및 상기 스토리지 노드 콘택 홀의 측벽에 제 2질화막 스페이서를 형성하는 단계; 측벽에 제 2질화막 스페이서가 형성된 상기 스토리지 노드 콘택 홀 내에 도전막을 매립시켜 스토리지 콘택을 형성하는 단계를 포함한다.In order to achieve the above object, a method of forming a bit line of a semiconductor device according to the present invention includes forming and patterning an insulating film covering a landing plug poly film and a first oxide film formed on a semiconductor substrate to form a bit line contact hole; Sequentially forming a barrier film, a tungsten film, a second oxide film, and a nitride film for a hard mask film on the insulating film including the inner surface of the bit line contact hole; Patterning the hard mask nitride film, the second oxide film, the tungsten film, and the barrier film to form a bit line; Oxidizing the exposed side of the tungsten film to form a sidewall oxide film; Forming first nitride layer spacers on both sides of the bit line including the sidewall oxide layer; Etching the insulating film between the first nitride film spacers to form a storage node contact hole exposing the landing plug poly film; Forming a second nitride film spacer on a surface of the first nitride film spacer and a sidewall of the storage node contact hole; And embedding a conductive layer in the storage node contact hole having a second nitride layer spacer formed on a sidewall thereof to form a storage contact.
(실시예)(Example)
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.
도 2a 내지 도 2h는 본 발명에 따른 반도체소자의 제조방법을 설명하기 위한 공정단면도이다.2A through 2H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
도 2a에 도시된 바와 같이, 반도체기판(20) 상에 STI(Shallow Trench Isolation)공정을 진행하여 소자분리막(22)을 형성하고 상기 소자분리막(22)을 포함하는 상기 기판(20) 상에 비트라인과 상기 소자분리막(22)을 연결하는 제 1산화막(24)과 LPP(Landing Plug Poly)(26)막을 형성한다.As shown in FIG. 2A, a shallow trench isolation (STI) process is performed on the semiconductor substrate 20 to form an isolation layer 22, and a bit on the substrate 20 including the isolation layer 22. A first oxide layer 24 and a landing plug poly (LPP) 26 layer connecting the line and the device isolation layer 22 are formed.
이후에, 열공정으로 Dopant를 주입하여 기판 전면을 활성화시킨 후 BPSG막(28)을 1700Å의 두께로 형성한다.Subsequently, the dopant is implanted by a thermal process to activate the entire surface of the substrate, and then the BPSG film 28 is formed to a thickness of 1700 Å.
그 다음, 도 2b에 도시된 바와 같이, 상기 BPSG막(28)상부에 마스크공정과 건식식각공정을 진행하여 비트라인 콘택트 홀(29)을 형성한다.Next, as shown in FIG. 2B, a mask process and a dry etching process are performed on the BPSG film 28 to form a bit line contact hole 29.
이어서, 도 2c에 도시된 바와 같이, Ti/TiN으로 이루어진 베리어막(38)과 텅스텐막(30)을 형성한 후 제 2산화막(40)을 100Å ~ 300Å 두께로 증착하고 하드마스크로 질화막(32)을 순차적으로 형성한다.Subsequently, as shown in FIG. 2C, after forming the barrier film 38 made of Ti / TiN and the tungsten film 30, the second oxide film 40 is deposited to a thickness of 100 μs to 300 μm and the nitride film 32 is formed using a hard mask. ) Are formed sequentially.
그 다음, 도 2d에 도시된 바와 같이, 상기 질화막(32),제 2산화막(40), 텅스텐막(30)과 상기 금속 베리어막(38)을 마스크공정과 건식식각공정을 진행하여 상기 텅스텐막(30)으로 이루어지는 비트라인을 형성한다.Next, as shown in FIG. 2D, the tungsten film is subjected to a mask process and a dry etching process of the nitride film 32, the second oxide film 40, the tungsten film 30, and the metal barrier film 38. A bit line consisting of 30 is formed.
이어서, 도 2e에 도시된 바와 같이, 비트라인을 구성하는 텅스텐막(30)을 산화시키어 상기 텅스텐막(30) 측벽에 약 50Å의 두께로 측벽산화막(42)을 형성한다.Subsequently, as shown in FIG. 2E, the tungsten film 30 constituting the bit line is oxidized to form a sidewall oxide film 42 on the sidewall of the tungsten film 30 to a thickness of about 50 GPa.
이때, 캐패시터 양을 구하는 공식 C = ε* A/D ( ε: 평균유전상수값, A : 전극의 단면적, D : 전극간 거리)에 의하여,상기 비트라인 측벽에 형성된 측벽산화막(42)은 텅스텐막(30)을 산화시키어 형성되기때문에 상기 텅스텐막(30)의 평균 유전상수값 ε을 낮추게 되고, 또한, 상기 형성된 측벽산화막(42)으로 인하여 비트라인과 비트라인사이의 거리를 증가시키기 때문에 전극간 거리 D 가 증가되므로 캐패시터양을 감소시킬 수 있다. At this time, the sidewall oxide film 42 formed on the sidewalls of the bit line is tungsten by the formula C = ε * A / D (ε: average dielectric constant value, A: cross-sectional area of the electrode, D: distance between electrodes) for calculating the amount of capacitor. Since the film 30 is formed by oxidizing, the average dielectric constant value ε of the tungsten film 30 is lowered, and the distance between the bit line and the bit line is increased due to the formed sidewall oxide film 42. Since the distance D is increased, the amount of capacitors can be reduced.
그 다음, 도 2f에 도시된 바와 같이, 기판 상부구조를 매립하는 질화막을 증착시킨 후 건식식각하여 상기 비트라인에 제 1질화막 스페이서(36)를 형성한다.Next, as shown in FIG. 2F, a nitride film filling the substrate upper structure is deposited and then dry etched to form a first nitride film spacer 36 on the bit line.
이어서, 도 2g에 도시된 바와 같이, 상기 제 1질화막 스페이서(36) 하단부에 형성된 BPSG막(28)을 건식식각공정을 진행하여 SNC(Storage Node Contact)홀(35)을 형성한다.Subsequently, as illustrated in FIG. 2G, a dry etching process is performed on the BPSG film 28 formed at the lower end of the first nitride film spacer 36 to form a storage node contact (SNC) hole 35.
그 다음, 도 2h에 도시된 바와 같이, 상기 SNC 홀을 매립하는 질화막을 증착하고 건식식각으로 제 2질화막 스페이서(37)를 형성시킨 후 상기 비트라인을 매립하는 도전막으로 SNC(Storage Node Contact) 폴리막(34)을 형성하여 스토리지 노드 콘택을 형성한다.Next, as shown in FIG. 2H, a nitride film filling the SNC hole is deposited, and a second nitride spacer 37 is formed by dry etching, and then a storage node contact (SNC) is used as a conductive film filling the bit line. The poly film 34 is formed to form a storage node contact.
이와 같은 방법으로, 도 2h의 도면부호 "B"에 도시된 바와 같이, 비트라인을 구성하는 텅스텐막주변에 유전율이 낮은 측벽산화막이 형성되어 비트라인과 SNC Poly막사이의 캐패시터양을 감소시키어 전체 기생 캐패시터를 감소시킬 수 있다.In this manner, as shown by reference numeral “B” of FIG. 2H, a low dielectric constant sidewall oxide film is formed around the tungsten film constituting the bit line, thereby reducing the amount of capacitors between the bit line and the SNC Poly film. Parasitic capacitors can be reduced.
상기에서 설명한 바와같이, 본 발명은 비트라인을 이루는 텅스텐측벽에 산화공정을 진행하여 산화막 스페이서를 형성하므로써 비트라인과 SNC Poly막사이에 발생되는 기생 캐패시터 크기를 감소시키어 반도체 소자동작 특성을 개선할 수 있다.As described above, the present invention can improve the semiconductor device operation characteristics by reducing the size of the parasitic capacitor generated between the bit line and the SNC Poly film by performing an oxidation process on the tungsten side wall forming the bit line. have.
한편, 본 발명은 상술한 특정의 바람직한 실시예에 한정되지 아니하며, 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능할 것이다. On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.
도 1은 종래의 발명에 따른 반도체소자의 제조방법을 설명하기위한 공정단면도.1 is a cross-sectional view for explaining a method of manufacturing a semiconductor device according to the related art.
도 2a 및 도 2h는 본 발명에 따른 반도체소자의 제조방법을 설명하기 위한 공정단면도.2A and 2H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
20 : 기판 22 : 소자분리막20: substrate 22: device isolation film
24 : 제 1산화막 26 : 랜딩플러그폴리막24: first oxide film 26: landing plug poly film
28 : BPSG막 30 : 텅스텐막28: BPSG film 30: tungsten film
32 : 질화막 34 : SNC 폴리막32: nitride film 34: SNC poly film
36 : 제 1질화막 스페이서 38 : 베리어막36 first nitride film spacer 38 barrier film
38 : 제 2질화막 스페이서 40 : 제 2산화막 38 second nitride film spacer 40 second oxide film
42 : 측벽산화막 42: sidewall oxide film
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