TW346672B - Method for fabricating a semiconductor memory cell in a DRAM - Google Patents

Abstract

A method for fabricating a semiconductor memory cell in a DRAM, the method comprising: forming isolation regions on a substrate; forming gate electrodes on the substrate and the isolation regions; forming first spacers on the sidewalls of the gate electrodes; forming source/drain regions in the surface of the substrate; forming a first dielectric layer on the source/drain regions and the gate electrodes; patterning and etching the first dielectric layer to expose a portion of the source/drain regions to form first contact holes; forming a first conductive layer on the first dielectric layer and in the first contact holes; removing the first conductive layer over the first dielectric layer to form inter plugs; forming a second dielectric layer on the first conductive layer and the first dielectric layer; patterning and etching the second dielectric layer until a portion of the first conductive layer is exposed to form second contact holes; forming a second conductive layer on the second dielectric layer and in the second contact holes to form bit lines; forming a third dielectric layer on the second conductive layer; patterning and etching the third dielectric layer, the second conductive layer, and the second dielectric layer until a portion of the first conductive layer is exposed to form a pre-third contact hole; forming second spacers on the sidewalls of the pre-third contact hole to form a third contact hole; forming a third conductive layer on the third dielectric layer and in the third contact hole; patterning and etching the third conductive layer to form a storage node of a capacitor; forming a capacitor insulating film over the storage node; and forming a plate of the capacitor over the capacitor insulting film.