JP5269563B2 - 配線基板とその製造方法 - Google Patents

配線基板とその製造方法 Download PDF

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Publication number
JP5269563B2
JP5269563B2 JP2008305154A JP2008305154A JP5269563B2 JP 5269563 B2 JP5269563 B2 JP 5269563B2 JP 2008305154 A JP2008305154 A JP 2008305154A JP 2008305154 A JP2008305154 A JP 2008305154A JP 5269563 B2 JP5269563 B2 JP 5269563B2
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JP
Japan
Prior art keywords
wiring board
pad
external connection
wiring
plating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2008305154A
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English (en)
Japanese (ja)
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JP2010129899A5 (enExample
JP2010129899A (ja
Inventor
健太郎 金子
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2008305154A priority Critical patent/JP5269563B2/ja
Priority to US12/626,025 priority patent/US8183467B2/en
Publication of JP2010129899A publication Critical patent/JP2010129899A/ja
Publication of JP2010129899A5 publication Critical patent/JP2010129899A5/ja
Priority to US13/427,235 priority patent/US8754336B2/en
Application granted granted Critical
Publication of JP5269563B2 publication Critical patent/JP5269563B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113—Via provided in pad; Pad over filled via
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09845—Stepped hole, via, edge, bump or conductor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0147—Carriers and holders
    • H05K2203/0152—Temporary metallic carrier, e.g. for transferring material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0369—Etching selective parts of a metal substrate through part of its thickness, e.g. using etch resist
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1184—Underetching, e.g. etching of substrate under conductors or etching of conductor under dielectrics; Means for allowing or controlling underetching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7424—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self-supporting substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2008305154A 2008-11-28 2008-11-28 配線基板とその製造方法 Active JP5269563B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2008305154A JP5269563B2 (ja) 2008-11-28 2008-11-28 配線基板とその製造方法
US12/626,025 US8183467B2 (en) 2008-11-28 2009-11-25 Wiring board and method of producing the same
US13/427,235 US8754336B2 (en) 2008-11-28 2012-03-22 Wiring board and method of producing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008305154A JP5269563B2 (ja) 2008-11-28 2008-11-28 配線基板とその製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2013097979A Division JP5701333B2 (ja) 2013-05-07 2013-05-07 配線基板とその製造方法

Publications (3)

Publication Number Publication Date
JP2010129899A JP2010129899A (ja) 2010-06-10
JP2010129899A5 JP2010129899A5 (enExample) 2011-10-27
JP5269563B2 true JP5269563B2 (ja) 2013-08-21

Family

ID=42221771

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008305154A Active JP5269563B2 (ja) 2008-11-28 2008-11-28 配線基板とその製造方法

Country Status (2)

Country Link
US (2) US8183467B2 (enExample)
JP (1) JP5269563B2 (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8461036B2 (en) * 2009-12-22 2013-06-11 Intel Corporation Multiple surface finishes for microelectronic package substrates
US9362236B2 (en) * 2013-03-07 2016-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods for forming the same
KR20160010960A (ko) * 2014-07-21 2016-01-29 삼성전기주식회사 인쇄회로기판 및 그 제조방법
JP6358431B2 (ja) * 2014-08-25 2018-07-18 新光電気工業株式会社 電子部品装置及びその製造方法
KR102340053B1 (ko) * 2015-06-18 2021-12-16 삼성전기주식회사 인쇄회로기판 및 인쇄회로기판의 제조 방법
JP2017050313A (ja) * 2015-08-31 2017-03-09 イビデン株式会社 プリント配線板及びプリント配線板の製造方法
JPWO2020090601A1 (ja) * 2018-10-30 2021-09-24 凸版印刷株式会社 半導体パッケージ用配線基板及び半導体パッケージ用配線基板の製造方法
US11164814B2 (en) * 2019-03-14 2021-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same
JP7266454B2 (ja) * 2019-04-25 2023-04-28 新光電気工業株式会社 配線基板、積層型配線基板、及び配線基板の製造方法
US20220069489A1 (en) * 2020-08-28 2022-03-03 Unimicron Technology Corp. Circuit board structure and manufacturing method thereof
TWI742991B (zh) * 2021-01-20 2021-10-11 啟耀光電股份有限公司 基板結構與電子裝置
JP7216139B2 (ja) * 2021-04-20 2023-01-31 Ｆｉｃｔ株式会社 回路基板の製造方法

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US5329695A (en) * 1992-09-01 1994-07-19 Rogers Corporation Method of manufacturing a multilayer circuit board
JP2550915B2 (ja) * 1994-06-21 1996-11-06 日本電気株式会社 印刷配線板の表面保護剤および表面保護膜の形成方法
SG65717A1 (en) * 1995-06-06 1999-06-22 Ibiden Co Ltd Printed circuit boards
JP3618176B2 (ja) * 1996-06-20 2005-02-09 日本特殊陶業株式会社 配線基板
US6225569B1 (en) * 1996-11-15 2001-05-01 Ngk Spark Plug Co., Ltd. Wiring substrate and method of manufacturing the same
US5900674A (en) * 1996-12-23 1999-05-04 General Electric Company Interface structures for electronic devices
US6043990A (en) * 1997-06-09 2000-03-28 Prototype Solutions Corporation Multiple board package employing solder balis and fabrication method and apparatus
JP3976954B2 (ja) 1999-08-27 2007-09-19 新光電気工業株式会社 多層配線基板の製造方法及び半導体装置
US6306751B1 (en) * 1999-09-27 2001-10-23 Lsi Logic Corporation Apparatus and method for improving ball joints in semiconductor packages
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KR100396787B1 (ko) * 2001-11-13 2003-09-02 엘지전자 주식회사 반도체 패키지용 인쇄회로기판의 와이어 본딩패드 형성방법
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Also Published As

Publication number Publication date
US8183467B2 (en) 2012-05-22
US20120175157A1 (en) 2012-07-12
US8754336B2 (en) 2014-06-17
US20100132995A1 (en) 2010-06-03
JP2010129899A (ja) 2010-06-10

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