JP5269563B2 - 配線基板とその製造方法 - Google Patents

配線基板とその製造方法 Download PDF

Info

Publication number
JP5269563B2
JP5269563B2 JP2008305154A JP2008305154A JP5269563B2 JP 5269563 B2 JP5269563 B2 JP 5269563B2 JP 2008305154 A JP2008305154 A JP 2008305154A JP 2008305154 A JP2008305154 A JP 2008305154A JP 5269563 B2 JP5269563 B2 JP 5269563B2
Authority
JP
Japan
Prior art keywords
wiring board
pad
external connection
wiring
plating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2008305154A
Other languages
English (en)
Japanese (ja)
Other versions
JP2010129899A (ja
JP2010129899A5 (enExample
Inventor
健太郎 金子
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2008305154A priority Critical patent/JP5269563B2/ja
Priority to US12/626,025 priority patent/US8183467B2/en
Publication of JP2010129899A publication Critical patent/JP2010129899A/ja
Publication of JP2010129899A5 publication Critical patent/JP2010129899A5/ja
Priority to US13/427,235 priority patent/US8754336B2/en
Application granted granted Critical
Publication of JP5269563B2 publication Critical patent/JP5269563B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113—Via provided in pad; Pad over filled via
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09845—Stepped hole, via, edge, bump or conductor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0147—Carriers and holders
    • H05K2203/0152—Temporary metallic carrier, e.g. for transferring material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0369—Etching selective parts of a metal substrate through part of its thickness, e.g. using etch resist
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1184—Underetching, e.g. etching of substrate under conductors or etching of conductor under dielectrics; Means for allowing or controlling underetching

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2008305154A 2008-11-28 2008-11-28 配線基板とその製造方法 Active JP5269563B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2008305154A JP5269563B2 (ja) 2008-11-28 2008-11-28 配線基板とその製造方法
US12/626,025 US8183467B2 (en) 2008-11-28 2009-11-25 Wiring board and method of producing the same
US13/427,235 US8754336B2 (en) 2008-11-28 2012-03-22 Wiring board and method of producing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008305154A JP5269563B2 (ja) 2008-11-28 2008-11-28 配線基板とその製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2013097979A Division JP5701333B2 (ja) 2013-05-07 2013-05-07 配線基板とその製造方法

Publications (3)

Publication Number Publication Date
JP2010129899A JP2010129899A (ja) 2010-06-10
JP2010129899A5 JP2010129899A5 (enExample) 2011-10-27
JP5269563B2 true JP5269563B2 (ja) 2013-08-21

Family

ID=42221771

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008305154A Active JP5269563B2 (ja) 2008-11-28 2008-11-28 配線基板とその製造方法

Country Status (2)

Country Link
US (2) US8183467B2 (enExample)
JP (1) JP5269563B2 (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8461036B2 (en) * 2009-12-22 2013-06-11 Intel Corporation Multiple surface finishes for microelectronic package substrates
US9362236B2 (en) * 2013-03-07 2016-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods for forming the same
KR20160010960A (ko) * 2014-07-21 2016-01-29 삼성전기주식회사 인쇄회로기판 및 그 제조방법
JP6358431B2 (ja) * 2014-08-25 2018-07-18 新光電気工業株式会社 電子部品装置及びその製造方法
KR102340053B1 (ko) * 2015-06-18 2021-12-16 삼성전기주식회사 인쇄회로기판 및 인쇄회로기판의 제조 방법
JP2017050313A (ja) * 2015-08-31 2017-03-09 イビデン株式会社 プリント配線板及びプリント配線板の製造方法
WO2020090601A1 (ja) * 2018-10-30 2020-05-07 凸版印刷株式会社 半導体パッケージ用配線基板及び半導体パッケージ用配線基板の製造方法
US11164814B2 (en) * 2019-03-14 2021-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same
JP7266454B2 (ja) * 2019-04-25 2023-04-28 新光電気工業株式会社 配線基板、積層型配線基板、及び配線基板の製造方法
US20220069489A1 (en) * 2020-08-28 2022-03-03 Unimicron Technology Corp. Circuit board structure and manufacturing method thereof
TWI742991B (zh) * 2021-01-20 2021-10-11 啟耀光電股份有限公司 基板結構與電子裝置
JP7216139B2 (ja) * 2021-04-20 2023-01-31 Ｆｉｃｔ株式会社 回路基板の製造方法

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5329695A (en) * 1992-09-01 1994-07-19 Rogers Corporation Method of manufacturing a multilayer circuit board
JP2550915B2 (ja) * 1994-06-21 1996-11-06 日本電気株式会社 印刷配線板の表面保護剤および表面保護膜の形成方法
CN1080981C (zh) * 1995-06-06 2002-03-13 揖斐电株式会社 印刷电路板
JP3618176B2 (ja) * 1996-06-20 2005-02-09 日本特殊陶業株式会社 配線基板
US6225569B1 (en) * 1996-11-15 2001-05-01 Ngk Spark Plug Co., Ltd. Wiring substrate and method of manufacturing the same
US5900674A (en) * 1996-12-23 1999-05-04 General Electric Company Interface structures for electronic devices
US6043990A (en) * 1997-06-09 2000-03-28 Prototype Solutions Corporation Multiple board package employing solder balis and fabrication method and apparatus
JP3976954B2 (ja) 1999-08-27 2007-09-19 新光電気工業株式会社 多層配線基板の製造方法及び半導体装置
US6306751B1 (en) * 1999-09-27 2001-10-23 Lsi Logic Corporation Apparatus and method for improving ball joints in semiconductor packages
US6485843B1 (en) * 2000-09-29 2002-11-26 Altera Corporation Apparatus and method for mounting BGA devices
JP2003039219A (ja) 2001-07-30 2003-02-12 Tohoku Sogo Kenkyusha:Kk ドリル
US6988312B2 (en) * 2001-10-31 2006-01-24 Shinko Electric Industries Co., Ltd. Method for producing multilayer circuit board for semiconductor device
KR100396787B1 (ko) * 2001-11-13 2003-09-02 엘지전자 주식회사 반도체 패키지용 인쇄회로기판의 와이어 본딩패드 형성방법
KR100439407B1 (ko) * 2002-04-11 2004-07-09 삼성전기주식회사 반도체소자 패키지 제조방법
US6762503B2 (en) * 2002-08-29 2004-07-13 Micron Technology, Inc. Innovative solder ball pad structure to ease design rule, methods of fabricating same and substrates, electronic device assemblies and systems employing same
TWI229436B (en) * 2003-07-10 2005-03-11 Advanced Semiconductor Eng Wafer structure and bumping process
US20050208749A1 (en) * 2004-03-17 2005-09-22 Beckman Michael W Methods for forming electrical connections and resulting devices
JP2005276892A (ja) * 2004-03-23 2005-10-06 Kyocera Corp 配線基板
US7626829B2 (en) * 2004-10-27 2009-12-01 Ibiden Co., Ltd. Multilayer printed wiring board and manufacturing method of the multilayer printed wiring board
JP2006186321A (ja) * 2004-12-01 2006-07-13 Shinko Electric Ind Co Ltd 回路基板の製造方法及び電子部品実装構造体の製造方法
JPWO2006064863A1 (ja) * 2004-12-17 2008-06-12 イビデン株式会社 プリント配線板
US7041591B1 (en) * 2004-12-30 2006-05-09 Phoenix Precision Technology Corporation Method for fabricating semiconductor package substrate with plated metal layer over conductive pad
TWI288447B (en) * 2005-04-12 2007-10-11 Siliconware Precision Industries Co Ltd Conductive bump structure for semiconductor device and fabrication method thereof
JP2005229138A (ja) * 2005-05-11 2005-08-25 Kyocera Corp 配線基板
JP2007067147A (ja) * 2005-08-31 2007-03-15 Shinko Electric Ind Co Ltd プリント配線基板およびその製造方法
TWI295550B (en) * 2005-12-20 2008-04-01 Phoenix Prec Technology Corp Structure of circuit board and method for fabricating the same
TWI278263B (en) * 2006-02-15 2007-04-01 Phoenix Prec Technology Corp Circuit board structure and method for fabricating the same
US7911038B2 (en) 2006-06-30 2011-03-22 Renesas Electronics Corporation Wiring board, semiconductor device using wiring board and their manufacturing methods
JP4354469B2 (ja) * 2006-08-11 2009-10-28 シャープ株式会社 半導体装置および半導体装置の製造方法
JP4800253B2 (ja) * 2007-04-04 2011-10-26 新光電気工業株式会社 配線基板の製造方法
US8314474B2 (en) * 2008-07-25 2012-11-20 Ati Technologies Ulc Under bump metallization for on-die capacitor

Also Published As

Publication number Publication date
JP2010129899A (ja) 2010-06-10
US8754336B2 (en) 2014-06-17
US8183467B2 (en) 2012-05-22
US20120175157A1 (en) 2012-07-12
US20100132995A1 (en) 2010-06-03

Similar Documents

Publication Publication Date Title
JP5269563B2 (ja) 配線基板とその製造方法
JP5101169B2 (ja) 配線基板とその製造方法
JP4271590B2 (ja) 半導体装置及びその製造方法
JP5421254B2 (ja) ピン・インタフェースを有する多層配線エレメント
US7185429B2 (en) Manufacture method of a flexible multilayer wiring board
JP5886617B2 (ja) 配線基板及びその製造方法、半導体パッケージ
JP6247032B2 (ja) 配線基板、半導体装置及び配線基板の製造方法
JP4619223B2 (ja) 半導体パッケージ及びその製造方法
JP4489821B2 (ja) 半導体装置及びその製造方法
JP2012146793A (ja) 配線基板及びその製造方法
JP2002050871A (ja) ビルドアップ回路基板およびその製造方法
JP2014072372A (ja) プリント配線板の製造方法及びプリント配線板
KR101011339B1 (ko) 배선기판 제조방법
JP4769056B2 (ja) 配線基板及びその製法方法
JP2012248891A (ja) 配線基板及びその製造方法
JP5701333B2 (ja) 配線基板とその製造方法
JP3874669B2 (ja) 配線基板の製造方法
JP2010067888A (ja) 配線基板及びその製造方法
JP5511922B2 (ja) 配線基板とその製造方法
CN102931165A (zh) 封装基板及其制造方法
TWI498068B (zh) A surface mounting method for an electronic component, and a printed circuit board produced by the method
JP4591098B2 (ja) 半導体素子搭載用基板の製造方法
JP2010103290A (ja) 半導体装置の製造方法
JP2005093930A (ja) 多層基板とその製造方法
JP2000208917A (ja) 回路基板の製造方法および基板材料

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110908

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20110908

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20120524

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120612

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120809

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20121030

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20121221

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20130409

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20130508

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

Ref document number: 5269563

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150