JP5208765B2 - Mosfetゲート電極のランディング・パッドのための構造および方法 - Google Patents
Mosfetゲート電極のランディング・パッドのための構造および方法 Download PDFInfo
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Description
をさらに含んでもよく、第1のゲート電極は、SOI層上にあり、第2のゲート電極は、STI領域上にある。他の実施の形態において、本方法は、ランディング・パッドの幅を第2のゲート電極の幅よりも大きく構成するステップをさらに含んでもよい。
をさらに含んでもよい。
Claims (13)
- 基板と、
前記基板上の埋め込み酸化物(buried oxide:BOX)層と、
前記BOX層上の絶縁体上シリコン(silicon on insulator:SOI)層上に形成された第1のゲート電極と、
前記第1のゲート電極に接続するように前記BOX層上のシャロー・トレンチ・アイソレーション(shallow trench isolation:STI)上に形成された第2のゲート電極と、
前記第2のゲート電極上のみに選択的に接して重なり合うフランジ付き端部の対を備えるランディング・パッドとを備え、
前記第1のゲート電極および前記ランディング・パッドの上にサリサイド領域が形成された、
集積回路。 - 前記ランディング・パッドの幅は、前記第2のゲート電極の幅よりも大きい、請求項1に記載の集積回路。
- 前記第1のゲート電極の両側にあるエピタキシャル成長領域と、
前記第1のゲート電極に隣接しかつその両側にある側壁スペーサと、
前記SOI層と前記第1のゲート電極との間にあるゲート誘電体層と、
前記エピタキシャル成長領域上にあるサリサイド領域と、
前記エピタキシャル成長領域上にある前記サリサイド領域に接続された相互接続端子と、
前記第1のゲート電極、前記側壁スペーサ、前記エピタキシャル成長領域上にある前記サリサイド領域、および前記STI領域上にある誘電体ライナーと、
前記誘電体ライナー上にあるレベル間誘電体層と
をさらに備える、請求項1に記載の集積回路。 - 前記第1のゲート電極の両側にある隆起ソースおよびドレイン領域と、
前記第1のゲート電極に隣接しかつその両側にある側壁スペーサと、
前記SOI層と前記第1のゲート電極との間にあるゲート誘電体層と、
前記第1のゲート電極ならびに前記隆起ソースおよびドレイン領域上にあるサリサイド領域と、
前記隆起ソースおよびドレイン領域上にある前記サリサイド領域に接続された相互接続端子と、
前記第1のゲート電極、前記側壁スペーサ、前記隆起ソースおよびドレイン領域上にある前記サリサイド領域、および前記STI領域上にある誘電体ライナーと、
前記誘電体ライナー上にあるレベル間誘電体層と
をさらに備える、請求項1に記載の集積回路。 - 前記STI領域と前記第2のゲート電極との間にあるゲート誘電体層と、
前記ランディング・パッドと接触する、前記第2のゲート電極に隣接しかつその両側にある側壁スペーサと、
前記ランディング・パッド上にある前記サリサイド領域に接続された接続間端子と、
前記側壁スペーサ、前記ランディング・パッド上にある前記サリサイド領域、および前記STI領域上にある誘電体ライナーと、
前記誘電体ライナー上にあるレベル間誘電体層と
をさらに備える、請求項1に記載の集積回路。 - 前記ランディング・パッドの上部表面は、前記第1のゲート電極の上部表面より高い、
請求項1に記載の集積回路。 - 集積回路を形成する方法であって、
基板を準備するステップと、
前記基板上に埋め込み酸化物(buried oxide:BOX)層を位置付けるステップと、
前記BOX層上に絶縁体上シリコン(silicon on insulator:SOI)層を配置するステップと、
前記BOX層上にシャロー・トレンチ・アイソレーション(shallow trench isolation:STI)領域を形成するステップと、
前記SOI層上に第1のゲート電極をパターニングし、該第1のゲート電極に接続した第2のゲート電極を前記STI領域上にパターニングするステップと、
フランジ付き端部の対を備え、前記第2のゲート電極上のみに選択的に接して重なり合うランディング・パッドを形成するステップと、
前記第1のゲート電極および前記ランディング・パッド上にサリサイド領域を形成するステップと
を含む、
方法。 - 前記ランディング・パッドの幅を前記第2のゲート電極の幅よりも大きく構成するステップをさらに含む、請求項7に記載の方法。
- 前記第1のゲート電極の両側にエピタキシャル領域を選択的に成長させるステップと、
前記第1のゲート電極に隣接しかつその両側に側壁スペーサを形成するステップと、
前記第1のゲート電極の両側に選択的に成長させたエピタキシャル成長領域上にサリサイド領域を形成するステップと、
相互接続端子を前記第1のゲート電極の両側に選択的に成長させた前記サリサイド領域に接続するステップと、
前記第1のゲート電極、前記側壁スペーサ、前記第1のゲート電極の両側に選択的に成長させた前記サリサイド領域、および前記STI領域上に誘電体ライナーを敷設するステップと、
前記誘電体ライナー上にレベル間誘電体層を配置するステップと
をさらに含む、請求項7に記載の方法。 - 前記第1のゲート電極の両側に隆起ソースおよびドレイン領域を形成するステップと、
前記第1のゲート電極に隣接しかつその両側に側壁スペーサを位置付けるステップと、
前記SOI層と前記第1のゲート電極との間にゲート誘電体層を構成するステップと、
前記隆起ソースおよびドレイン領域上にサリサイド領域を形成するステップと、
相互接続端子を前記隆起ソースおよびドレイン領域上に形成した前記サリサイド領域に接続するステップと、
前記第1のゲート電極、前記側壁スペーサ、前記隆起ソースおよびドレイン領域上に形成した前記サリサイド領域、および前記STI領域上に誘電体ライナーを敷設するステップと、
前記誘電体ライナー上にレベル間誘電体層を配置するステップと
をさらに含む、請求項7に記載の方法。 - 前記第2のゲート電極に隣接しかつその両側に側壁スペーサを位置付けるステップと、
前記側壁スペーサの上部をエッチングして前記第2のゲート電極の両側を露出させるステップと、
前記第2のゲート電極上に前記ランディング・パッドを形成した後に、前記第2のゲート電極に隣接しかつその両側に、前記ランディング・パッドと接触する2次側壁スペーサを前記側壁スペーサに一体化して形成するステップと、
接続間端子を前記ランディング・パッド上にある前記サリサイド領域に接続するステップと、
前記側壁スペーサ、前記ランディング・パッド上にある前記サリサイド領域、および前記STI領域上に誘電体ライナーを敷設するステップと、
前記誘電体ライナー上にレベル間誘電体層を形成するステップと
をさらに含む、請求項7に記載の方法。 - 前記ランディング・パッドの上部表面を前記第1のゲート電極の上部表面より高く構成するステップをさらに含む、請求項7に記載の方法。
- 前記第2のゲート電極をパターニングするステップとは別個の処理ステップにおいて前記ランディング・パッドを形成するステップをさらに含む、請求項7に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/333,068 US7528065B2 (en) | 2006-01-17 | 2006-01-17 | Structure and method for MOSFET gate electrode landing pad |
US11/333,068 | 2006-01-17 | ||
PCT/US2007/060564 WO2007127503A2 (en) | 2006-01-17 | 2007-01-16 | Structure and method for mosfet gate electrode landing pad |
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CN102110717B (zh) * | 2011-01-26 | 2013-01-02 | 成都瑞芯电子有限公司 | 沟槽式金属氧化物半导体场效应晶体管及其制造方法 |
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US20070164357A1 (en) | 2007-07-19 |
WO2007127503A2 (en) | 2007-11-08 |
KR101020015B1 (ko) | 2011-03-09 |
JP2009524221A (ja) | 2009-06-25 |
KR20080085192A (ko) | 2008-09-23 |
US8304912B2 (en) | 2012-11-06 |
CN101490842A (zh) | 2009-07-22 |
TW200742086A (en) | 2007-11-01 |
EP1994563A4 (en) | 2011-06-22 |
US7528065B2 (en) | 2009-05-05 |
WO2007127503A8 (en) | 2008-09-04 |
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EP1994563A2 (en) | 2008-11-26 |
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