TWI672767B - 被動裝置結構及其製造方法 - Google Patents

被動裝置結構及其製造方法 Download PDF

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TWI672767B
TWI672767B TW107113831A TW107113831A TWI672767B TW I672767 B TWI672767 B TW I672767B TW 107113831 A TW107113831 A TW 107113831A TW 107113831 A TW107113831 A TW 107113831A TW I672767 B TWI672767 B TW I672767B
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fins
layer
dielectric layer
passive device
conformal dielectric
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TW201906074A (zh
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劉兵武
輝 臧
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美商格芯（美國）集成電路科技有限公司
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Abstract

本發明揭露用於積體電路的被動裝置的結構以及相關製造方法。形成具有凸起鰭片以及位於該鰭片之間的介電隔離層的半導體基板。在被動裝置的鰭片之間的該介電隔離層上方形成蝕刻停止層。在該鰭片及蝕刻停止層上方形成層間介電層。選擇性蝕刻該層間介電層，以形成用於至該鰭片的導電接觸的開口，其中，該蝕刻停止層防止蝕刻該介電隔離層。形成導電接觸以接觸該多個鰭片，該導電接觸終止於該蝕刻停止層。

Description

被動裝置結構及其製造方法
本發明關於半導體裝置製造及積體電路，尤其關於包括被動裝置結構的結構以及製造被動裝置的方法。
二極體、電容器及電阻器是積體電路中的被動裝置，它們不能夠開關電流。例如，二極體可包括位於半導體晶圓中的兩個相鄰摻雜區，其中，該兩個摻雜區具有相反的導電類型，以定義p-n接面(junction)。
在包括鰭式場效電晶體(fin-type field-effect transistor；FinFET)裝置的積體電路結構中，被動裝置例如二極體也可包括接觸導電接觸的多個鰭片。鰭片可通過隔離介電材料電性隔離，但在製造期間，該隔離材料的某部分可能被蝕刻，且如果該蝕刻製程沒有被很好地控制，則該隔離材料的某些部分可能被蝕刻太深。當形成該導電接觸時，它可深入至該隔離材料的這些深蝕刻區域中，從而劣化電性隔離並在該裝置中引起電流洩漏。隨著積體電路裝置持續縮小，確保防止電流洩漏及電性短 路已成為製程中越來越重要的考慮因素。
在本發明的一個實施例中，一種結構具有介電隔離層以及設於該介電隔離層上的共形介電層。該結構包括被動裝置，該被動裝置具有半導體本體以及自該半導體本體延伸穿過該介電隔離層並穿過該共形介電層的多個鰭片。導電接觸設於該多個鰭片及該共形介電層上，該導電接觸與該多個鰭片連接並終止於該多個鰭片之間的該共形介電層。
在本發明的一個實施例中，一種方法包括在位於被動裝置的多個鰭片之間的介電隔離層上形成蝕刻停止層。在該多個鰭片及該蝕刻停止層上沉積層間介電層，以及蝕刻該層間介電層以形成暴露該多個鰭片並終止於該蝕刻停止層上的開口。在該開口中形成導電接觸，該導電接觸與該多個鰭片連接。
10‧‧‧結構
12‧‧‧半導體基板或基板
15‧‧‧阱
16‧‧‧摻雜區
17‧‧‧p-n接面
20‧‧‧鰭片
20a‧‧‧側壁
22‧‧‧鰭片
23‧‧‧凸起鰭片結構
30‧‧‧介電隔離層
40‧‧‧共形介電層
41‧‧‧蝕刻停止層
41a、41b‧‧‧厚度
45‧‧‧犧牲層
47‧‧‧遮罩層
60‧‧‧層間介電層
70、75‧‧‧導電接觸
100‧‧‧被動裝置
105‧‧‧主動裝置或鰭式場效電晶體(FinFET)裝置
包含於並構成本說明書的一部分的附圖說明本發明的各種實施例，並與上面所作的有關本發明的概括說明以及下面所作的有關實施例的詳細說明一起用以解釋本發明的實施例。
第1圖至第7A圖顯示依據本發明的實施例處於製程方法的連續製造階段的結構的剖視圖。
第7B圖及第7C圖顯示處於第7A圖之後的連續製造階段的結構的頂視圖。
第8A圖至第8B圖分別顯示處於第7C圖之後的製造階段的結構的剖視圖及頂視圖。
第1圖至第8B圖顯示一種用於製造包括被動裝置100的結構10的方法的實施例。在第1圖至第8B圖中，將結構10顯示為包括形成於結構10的另一部分上的主動裝置105，例如FinFET裝置。常常建立用於製造積體電路裝置及結構的製程以在相同製造步驟中同時製造積體電路中的不同裝置的部分，例如以保護一個裝置(或多個類似裝置)免受執行於同一結構的另一個裝置上的製程影響。本文中所述並在第1圖至第8B圖中顯示的製程可在考慮或不考慮結構10的其它元件例如裝置105的情況下執行，以形成被動裝置，例如所示被動裝置100的實施例。
請參照第1圖並依據本發明的實施例，結構10具有位於半導體基板12上方的被動裝置100及鰭式場效電晶體裝置105(也被稱為FinFET裝置105)。被動裝置100具有延伸於半導體基板12上方的多個鰭片20，且FinFET裝置105也具有自半導體基板12突出的多個鰭片22。鰭片20、22可通過例如光刻及蝕刻製程例如側壁圖像轉移(sidewall imaging transfer；SIT)製程由半導體基板12的材料形成。在鰭片20、22之間設置介電隔離層30，以使鰭片20、22自基板12延伸穿過介電隔離層30。介電隔離層30可為通過例如化學氣相沉積(chemical vapor deposition；CVD)沉積的介電材料例如矽的氧化物(例如， 二氧化矽(SiO2))。被動裝置100進一步包括具有導電類型如n型的阱(well)15。若用n型摻雜物(例如磷)摻雜該區域，則阱15可例如為n阱。
第1圖還顯示在鰭片20及介電隔離層30上方沉積共形介電層40之後的被動裝置100，以及在鰭片22上方磊晶生長半導體材料以形成凸起鰭片結構23之後的FinFET裝置105。共形介電層40可為氮化物材料，例如氮化矽，或低k介電材料如矽氧碳氮化物(SiOCN)。低k介電材料通常為具有小於二氧化矽的介電常數的介電常數k的任意介電質。介電隔離層30可具有與共形介電層40不同的蝕刻選擇性，無論共形介電層40是氮化物材料、低k介電材料還是替代介電材料。共形介電層40可通過確保共形介電層40在鰭片20及介電隔離層30上方具有基本均勻的厚度的任意製程沉積，例如通過化學氣相沉積(CVD)或原子層沉積(atomic layer deposition；ALD)沉積。通過在鰭片22上方磊晶生長半導體材料例如矽或矽-鍺(SiGe)來形成凸起鰭片結構23可用以定義FinFET裝置105的源/汲區。在示例實施例中，該磊晶沉積及生長製程可經控制以持續形成凸起鰭片結構23直至凸起鰭片結構23合併在一起，如第1圖中所示。凸起鰭片結構23的合併提供著陸導電接觸的較大表面區域。
在一個實施例中，在FinFET裝置105的鰭片22上方磊晶生長該半導體材料期間，可掩蔽被動裝置100，而在形成凸起鰭片結構23以後，在鰭片20上方沉積 共形介電層40。在一個例子中，可掩蔽凸起鰭片結構23，以防止在凸起鰭片結構23上沉積共形介電層40。在另一個例子中，共形介電層40可沉積於凸起鰭片結構23以及鰭片20上方，並自凸起鰭片結構23被選擇性蝕刻掉。在另一個實施例中，在鰭片22上方磊晶生長半導體材料之前，在鰭片20上方可沉積共形介電層40，從而共形介電層40防止在鰭片20上方磊晶生長該半導體材料，因為半導體材料不會成核於介電材料上方。
請參照第2圖，其中類似的附圖標記表示第2圖中類似的特徵且在下一製造階段，在被動裝置100上以及在FinFET裝置105上沉積犧牲層45。犧牲層45可為例如旋塗硬遮罩如有機平坦化層(organic planarization layer；OPL)，且可通過任意製程例如旋塗製程設置。另外，在覆蓋FinFET裝置105的犧牲層45的部分上沉積遮罩層47。遮罩層47可包括能夠保護犧牲層45免受隨後的蝕刻或凹入製程影響的任意材料，如下面進一步所述，例如具有一個或多個遮罩材料層的光刻堆疊。例如，除其它光刻遮罩層以外，光刻堆疊可包括抗反射塗層以及光阻層。遮罩層47可選擇性設於FinFET裝置105上方的犧牲層45的部分上方。
請參照第3圖，其中類似的附圖標記表示第2圖中類似的特徵且在下一製造階段，顯示在凹入犧牲層45於鰭片20的頂部表面下方之後的結構10。犧牲層45的凹入可通過能夠選擇性移除犧牲層45的任意製程執 行，例如使用反應離子蝕刻(reactive-ion etching；RIE)製程的回蝕刻。該凹入可經控制以終止於犧牲層45已到達預定降低厚度時，且剩餘犧牲層45保留於相鄰對鰭片20之間的共形介電層40的部分上方。在該凹入期間，遮罩層47掩蔽FinFET裝置105上方的犧牲層45。
請參照第4圖，其中類似的附圖標記表示第3圖中類似的特徵且在下一製造階段，自鰭片20的頂部表面及側壁20a移除共形介電層40，以暴露鰭片20的上部。該移除可通過選擇性蝕刻製程執行，該選擇性蝕刻製程選擇性移除共形介電層40的介電材料，而不會蝕刻凹入犧牲層45且不會蝕刻鰭片20的半導體材料。在一個實施例中，該蝕刻製程可為非等向性(anisotropic)乾式蝕刻製程，例如反應離子蝕刻(RIE)製程。該蝕刻製程可經控制以終止於鰭片20的充足部分已通過該蝕刻製程暴露時且在犧牲層45與鰭片20之間的共形介電層40的部分被蝕刻之前。在一個例子中，該蝕刻製程可經控制以終止於共形介電層40的剩餘部分具有基本等於凹入犧牲層45的選定厚度的厚度時。該蝕刻製程可例如通過定時該蝕刻製程以持續預定的持續時間來控制。在該蝕刻期間，遮罩層47掩蔽FinFET裝置105。
請參照第5圖，其中類似的附圖標記表示第4圖中類似的特徵且在下一製造階段，自共形介電層40的剩餘部分上方移除剩餘犧牲層45，以使該共形介電層的剩餘部分形成蝕刻停止層41。如第5圖所示，遮罩層47 繼續保護FinFET裝置105上方的犧牲層45的部分，而自被動裝置100上方移除犧牲層45。在替代實施例中，在後續製造階段中可保留被動裝置100上的剩餘犧牲層45，如下所述，而在單個移除步驟中移除剩餘犧牲層45以及位於FinFET裝置105上方的犧牲層45的部分，如下所述。如第5圖所示，作為本文中所述製程的結果，蝕刻停止層41設於與被動裝置100關聯的鰭片20之間的空隙中，且可在靠近或接觸鰭片20處具有較大的厚度41a並在成對鰭片20之間具有較小的厚度41b。
請參照第6圖，其中類似的附圖標記表示第5圖中類似的特徵且在下一製造階段，將摻雜物的離子注入(通常用附圖標記50表示)被動裝置100，以在阱15內形成摻雜區16。遮罩層47可阻擋該摻雜物的注入，從而該摻雜物不會進入FinFET裝置105的任意部分中，而僅注入被動裝置100的部分中。該摻雜物提供導電類型與半導體材料阱15的導電類型相反的摻雜區16的半導體材料。在一個實施例中，該摻雜物可為p型摻雜物，例如硼。由於摻雜區16與阱15具有相反的導電類型，因此摻雜區16與阱15沿p-n接面17鄰接。在此階段期間也可將該摻雜物注入50至鰭片20，從而鰭片20與摻雜區16共同具有相同的導電類型。
請參照第7A圖及第7B圖，其中類似的附圖標記表示第6圖中類似的特徵且在下一製造階段，自FinFET裝置105上方移除遮罩層47以及犧牲層45的剩餘 部分，且在結構10上方沉積層間介電層60。在示例實施例中，層間介電層60可為氧化物材料，例如二氧化矽，且可為與介電隔離層30相同或類似的材料。
請參照第7C圖，其中類似的附圖標記表示第7A圖及第7B圖中類似的特徵且在下一製造階段，例如通過光刻蝕刻製程可選擇性蝕刻層間介電層60，從而形成開口以暴露被動裝置100並暴露由FinFET裝置105的凸起鰭片結構23所定義的源/汲區，以及允許至該暴露部分的導電接觸，如下所述，同時保留層間介電層60的其它部分完好，以使位於層間介電層60下方的結構10的部分可與導電接觸70保持電性隔離。該蝕刻製程可為選擇性蝕刻層間介電層60的部分而不會蝕刻蝕刻停止層41的材料的任意蝕刻製程，例如相對氧化物材料具有選擇性的蝕刻製程，從而在被動裝置100上方的該開口的蝕刻終止於蝕刻停止層41。因此，可自被動裝置100上方安全移除層間介電層60，而該蝕刻製程不會不合期望地蝕刻介電隔離層30的部分，否則，這可導致相鄰鰭片20之間剩餘的絕緣材料不足以及/或者在導電接觸(例如第8A圖及第8B圖中所示的導電接觸70)與被動裝置100的半導體基板12之間的電性隔離不足。通過該選擇性蝕刻製程所形成的該開口可在同一蝕刻製程內同時形成。
請參照第8A圖及第8B圖，其中類似的附圖標記表示第7A圖至第7C圖中類似的特徵且在下一製造階段，在被動裝置100的多個鰭片20上方設置導電接觸 70，並在構成FinFET裝置105的源/汲區23的凸起鰭片結構23上方設置另一個導電接觸75。在一個實施例中，導電接觸70可直接接觸被動裝置100的鰭片20。類似地，在一個實施例中，另一個導電接觸75可直接接觸FinFET裝置105的凸起鰭片結構23。例如，通過矽化矽化物形成金屬(如鈷或鎳)以及位於多個鰭片20的頂部表面及/或接觸該矽化物形成金屬的凸起鰭片結構23的頂部表面的半導體材料，可部分形成導電接觸70、75。矽化製程可包括一個或多個退火步驟，以通過使該矽化物形成金屬與鰭片20及/或凸起鰭片結構23的半導體材料反應來形成矽化物相，從而形成導電接觸70的金屬矽化物層。在一個實施例中，該導電接觸還可包括沉積於該金屬矽化物層上方的金屬材料，例如鎢。
如上所述的方法用於積體電路晶片的製造中。製造者可以原始晶圓形式(例如作為具有多個未封裝晶片的單個晶圓)、作為裸晶片，或者以封裝形式分配所得的積體電路晶片。在後一種情況中，該晶片設于單晶片封裝件中(例如塑膠承載件，其具有附著至主機板或其它更高層次承載件的引腳)或者多晶片封裝件中(例如陶瓷承載件，其具有單面或雙面互連或嵌埋互連)。在任何情況下，可將該晶片與其它晶片、分立電路元件和/或其它信號處理裝置集成，作為中間產品或最終產品的部分。
本文中引用術語例如“垂直”、“水平”等作為示例來建立參考框架，並非限制。本文中所使用的術語“水 平”被定義為與半導體基板的傳統平面平行的平面，而不論其實際的三維空間取向。術語“垂直”及“正交”是指垂直於如剛剛所定義的水平面的方向。術語“橫向”是指在該水平平面內的方向。術語例如“上方”及“下方”用以表示元件或結構相對彼此的定位，而不是相對標高。
與另一個元件“連接”或“耦接”的特徵可與該另一個元件直接連接或耦接，或者可存在一個或多個中間元件。如果不存在中間元件，則特徵可與另一個元件“直接連接”或“直接耦接”。如存在至少一個中間元件，則特徵可與另一個元件“非直接連接”或“非直接耦接”。
對本發明的各種實施例所作的說明是出於說明目的，而非意圖詳盡無遺或限於所揭露的實施例。許多修改及變更對於本領域的普通技術人員將顯而易見，而不背離所述實施例的範圍及精神。本文中所使用的術語經選擇以最佳解釋實施例的原理、實際應用或在市場已知技術上的技術改進，或者使本領域的普通技術人員能夠理解本文中所揭露的實施例。

Claims (20)

  1. 一種被動裝置結構，包括：介電隔離層；共形介電層，設於該介電隔離層上；被動裝置，包括半導體本體以及自該半導體本體延伸穿過該介電隔離層並穿過該共形介電層的多個鰭片；以及第一導電接觸，設於該多個鰭片及該共形介電層上，該第一導電接觸與該多個鰭片直接接觸並終止於該多個鰭片之間的該共形介電層。
  2. 如申請專利範圍第1項所述的被動裝置結構，其中，該被動裝置包括位於半導體基板上方的半導體本體、形成於該半導體本體中的阱、以及位於該阱內的摻雜區，該阱具有第一導電類型，該摻雜區具有與該第一導電類型相反的第二導電類型，該摻雜區與該阱沿p-n接面鄰接，該摻雜區設於該多個鰭片與該阱之間，且該多個鰭片與該摻雜區連接。
  3. 如申請專利範圍第2項所述的被動裝置結構，其中，該多個鰭片具有該第二導電類型。
  4. 如申請專利範圍第1項所述的被動裝置結構，其中，該共形介電層為氮化物材料，且該介電隔離層為氧化物材料。
  5. 如申請專利範圍第1項所述的被動裝置結構，其中，該共形介電層為低k介電材料，且該介電隔離層為氧 化物材料。
  6. 如申請專利範圍第1項所述的被動裝置結構，其中，該共形介電層在靠近或接觸該多個鰭片處具有第一厚度且在該多個鰭片的相鄰對之間具有第二厚度。
  7. 如申請專利範圍第1項所述的被動裝置結構，進一步包括：鰭式場效電晶體裝置，包括源/汲區；以及第二導電接觸，與該源/汲區連接。
  8. 如申請專利範圍第7項所述的被動裝置結構，其中，該鰭式場效電晶體裝置進一步包括多個鰭片以及形成於該多個鰭片上的多個凸起鰭片結構，該多個凸起鰭片結構定義該源/汲區。
  9. 如申請專利範圍第1項所述的被動裝置結構，進一步包括：層間介電層，位於該共形介電層上，其中，該第一導電接觸及該多個鰭片設置於在該層間介電層中所定義的開口中。
  10. 一種製造被動裝置結構的方法，該方法包括：在位於與被動裝置關聯的多個第一鰭片之間的空隙中的介電隔離層上形成蝕刻停止層；在該多個第一鰭片及該蝕刻停止層上沉積層間介電層；蝕刻該層間介電層以形成第一開口，該第一開口暴露該多個第一鰭片並終止於該多個第一鰭片之間的 該空隙中的該蝕刻停止層上；以及在該第一開口中形成與該多個第一鰭片直接接觸的第一導電接觸。
  11. 如申請專利範圍第10項所述的方法，其中，該多個第一鰭片各者包括一個或多個側壁，且形成該蝕刻停止層包括：在該多個第一鰭片及該介電隔離層上沉積共形介電層；形成掩蔽該多個第一鰭片之間的該空隙中的該共形介電層的部分的犧牲層；以及選擇性蝕刻該共形介電層，以自該多個第一鰭片的該一個或多個側壁移除該共形介電層，其中，該共形介電層的該部分形成該蝕刻停止層。
  12. 如申請專利範圍第11項所述的方法，其中，該共形介電層包括氮化物材料，且該層間介電層是具有與該氮化物材料不同的蝕刻選擇性的氧化物材料。
  13. 如申請專利範圍第11項所述的方法，其中，該共形介電層包括低k介電材料，且該層間介電層是具有與該低k介電材料不同的蝕刻選擇性的氧化物材料。
  14. 如申請專利範圍第11項所述的方法，其中，該第一導電接觸經設置以接觸該多個第一鰭片的該一個或多個側壁。
  15. 如申請專利範圍第11項所述的方法，其中，形成該犧 牲層包括：在該共形介電層及該多個第一鰭片上沉積該犧牲層；以及通過回蝕刻製程凹入該犧牲層於該多個第一鰭片之間的該空隙中。
  16. 如申請專利範圍第11項所述的方法，進一步包括：在鰭式場效電晶體裝置的多個第二鰭片上形成該犧牲層；在選擇性蝕刻該共形介電層之前，在該鰭式場效電晶體裝置上方的該犧牲層上沉積遮罩層，該遮罩層經設置以掩蔽該鰭式場效電晶體裝置免受該共形介電層的該選擇性蝕刻；以及在選擇性蝕刻該共形介電層以後，自該鰭式場效電晶體裝置上方移除該遮罩層及該犧牲層。
  17. 如申請專利範圍第16項所述的方法，進一步包括：在該多個第二鰭片的至少部分上方磊晶生長半導體材料，以形成凸起鰭片結構，其中，該凸起鰭片結構定義該鰭式場效電晶體裝置的源/汲區。
  18. 如申請專利範圍第17項所述的方法，其中，該層間介電層形成於該鰭式場效電晶體裝置上，且進一步包括：在該層間介電層中蝕刻第二開口，該第二開口暴露該源/汲區；以及 在該第二開口中形成與該源/汲區連接的第二導電接觸，其中，同時蝕刻該層間介電層中的該第一開口與該第二開口。
  19. 如申請專利範圍第10項所述的方法，其中，該被動裝置包括位於半導體基板上方的半導體本體以及形成於該半導體本體中的阱，該阱具有第一導電類型，且進一步包括：在形成該蝕刻停止層以後，在該阱上方形成摻雜區，其中，該摻雜區具有與該第一導電類型相反的第二導電類型。
  20. 如申請專利範圍第19項所述的方法，其中，形成該摻雜區包括：向該阱中注入摻雜物。
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