TWI614869B - 互連結構與其製造方法和應用其之半導體元件 - Google Patents

互連結構與其製造方法和應用其之半導體元件 Download PDF

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TWI614869B
TWI614869B TW105120339A TW105120339A TWI614869B TW I614869 B TWI614869 B TW I614869B TW 105120339 A TW105120339 A TW 105120339A TW 105120339 A TW105120339 A TW 105120339A TW I614869 B TWI614869 B TW I614869B
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silicide
layer
barrier layer
semiconductor
silicon
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TW105120339A
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TW201711157A (zh
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林瑀宏
劉繼文
曾鴻輝
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台灣積體電路製造股份有限公司
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Abstract

一種半導體元件包括：包含接觸區域的半導體基板，存在於接觸區域上的矽化物，存在於半導體基板上的介電層，包含開口以曝露接觸區域的部分的介電層，存在於開口中的導體，存在於導體與介電層之間的阻障層，以及存在於阻障層與介電層之間的金屬層，其中此矽化物的矽濃度沿著此矽化物的高度而變化。

Description

互連結構與其製造方法和應用其之半 導體元件
本揭露係關於一種半導體元件之結構與製造方法。
半導體積體電路(integrated circuit；IC)工業已經歷了快速增長。現代積體電路由約數百萬諸如電晶體及電容器之主動元件組成。積體電路材料及設計中的技術進步產生了數代積體電路，其中每一代皆具有比上一代更小且更為複雜的電路。此等元件開始時彼此絕緣，但後來經由多個金屬層互連接在一起以形成功能電路。隨著積體電路變得日益複雜，互連接結構亦變得更加複雜，從而造成金屬層數目增加。
互連結構可包括橫向互連如金屬線(電線)和縱向互連如導電通孔與觸點。然而，複雜的互連限制了現代積體電路的效能和密度。
本揭露之一實施方式提供了一種半導體元件，包含：包含接觸區域的半導體基版、存在於接觸區域上的矽化物、存在於半導體基版上的介電層，其中介電層包含開口以曝露該接觸區域的一部分，存在於開口中的導體、存在於導體和介電層之間的阻障層、存在於阻障層與介電層之間的金屬層，其中矽化物的矽濃度沿著矽化物的高度而變化。
本揭露之另一實施方式提供了一種互連結構，包含矽化物、導體、阻障層，其中阻障層存在於導體的側壁上並且存在於矽化物與導體之間，存在於阻障層側壁處的金屬層，其中矽化物的矽濃度沿著矽化物的高度而減小。
本揭露之又一實施方式提供了一種互連結構的製造方法，包含在在介電層中形成開口以曝露接觸區域的一部分；在開口的側壁上並且在接觸區域上形成金屬層；在金屬層上形成阻障層；並且在阻障層形成於金屬層上之後執行退火製程，以在阻障層與接觸區域之間形成矽化物。
100‧‧‧鰭式場效電晶體元件
110‧‧‧基板
112‧‧‧n阱區域
116‧‧‧p阱區域
122‧‧‧半導體鰭片
122c‧‧‧通道部分
122r‧‧‧溝槽部分
124‧‧‧半導體鰭片
124c‧‧‧通道部分
124r‧‧‧溝槽部分
130‧‧‧隔離結構
140‧‧‧閘極間隔層
142‧‧‧虛設閘極
150‧‧‧磊晶結構
160‧‧‧磊晶結構
170‧‧‧閘極堆疊
210‧‧‧磊晶結構
220‧‧‧介電層
222‧‧‧開口
230‧‧‧金屬層
240‧‧‧阻障層
250‧‧‧矽化物
260‧‧‧導體
300‧‧‧半導體元件
310‧‧‧絕緣體上半導體結構
312‧‧‧半導體基板
314‧‧‧內埋氧化物層
316‧‧‧絕緣體上半導體層
320‧‧‧襯墊
322‧‧‧襯墊
324‧‧‧襯墊
326‧‧‧襯墊
328‧‧‧襯墊
332‧‧‧連接結構
334‧‧‧連接結構
342‧‧‧奈米線
344‧‧‧奈米線
352‧‧‧間隔層
354‧‧‧間隔層
362‧‧‧虛設閘極材料層
364‧‧‧虛設閘極材料層
370‧‧‧層間介電質層
382‧‧‧溝槽
384‧‧‧溝槽
390‧‧‧閘極堆疊
392‧‧‧閘極堆疊
400‧‧‧互連結構
410‧‧‧金屬層
420‧‧‧矽化物
430‧‧‧阻障層
440‧‧‧導體
閱讀以下詳細敘述並搭配對應之圖式，可了解本揭露之多個態樣。應注意，根據業界中的標準做法，多個特徵並非按比例繪製。事實上，多個特徵之尺寸可任意增加或減少以利於討論的清晰性。
第1A圖至第1E圖是根據本揭示案的部分實施例，用於製造鰭式場效電晶體(FinFET)元件的方法在各個階段的示意性斜視圖。
第2A圖至第2G圖是在鰭式場效電晶體元件中製造互連結構的方法的局部橫截面圖。
第3A圖至第3F圖是根據本揭示案的部分實施例，用於製造半導體元件的方法在各個階段的示意性斜視圖。
第4圖是根據本揭示案的部分其它實施例，互連結構的局部橫截面圖。
以下揭露提供眾多不同的實施例或範例，用於實施本案提供的主要內容之不同特徵。下文描述一特定範例之組件及配置以簡化本揭露。當然，此範例僅為示意性，且並不擬定限制。舉例而言，以下描述「第一特徵形成在第二特徵之上方或之上」，於實施例中可包括第一特徵與第二特徵直接接觸，且亦可包括在第一特徵與第二特徵之間形成額外特徵使得第一特徵及第二特徵無直接接觸。此外，本揭露可在各範例中重複使用元件符號及/或字母。此重複之目的在於簡化及釐清，且其自身並不規定所討論的各實施例及/或配置之間的關係。
此外，空間相對術語，諸如「下方(beneath)」、「以下(below)」、「下部(lower)」、「上方(above)」、「上部(upper)」等等在本文中用於簡化描述，以描述如附圖中所圖示的一個元件或特徵結構與另一元件或特徵結構的關係。除了描繪圖示之方位外，空間相對術語也包含元件在使用中或操作下之不同方位。此設備可以其他方式定向(旋轉90度 或處於其他方位上)，而本案中使用之空間相對描述詞可相應地進行解釋。
隨著半導體元件尺寸不斷縮小，滿足複合金屬化製造中的導電性需求及可靠度已變得日益困難。舉例而言，互連接結構(包含將積體電路元件中不同層的金屬線互連接的金屬線及導電通孔)之形成一般需要低電阻，而且需要阻障層，阻障層阻擋導電通孔中的導電金屬擴散到內層介電質(Interlayer Dielectric：ILD)層中。為了降低積體電路元件中的阻容(resistance-capacitor；RC)延遲，阻障層亦有調控互連接之電阻率的功用。本揭露係關於一種降低半導體元件(諸如鰭式場效電晶體元件)中的互連接結構之電阻的方法。
第1A圖至第1E圖是根據本揭示案的部分實施例，用於製造鰭式場效電晶體元件的方法在各個階段的示意性斜視圖。參照第1A圖。提供了基板110。在部分實施例中，基板110可為半導體材料並且可包括已知結構，包括例如漸變層或者埋入式氧化物。在部分實施例中，基板110可包含未摻雜或者有摻雜的(例如，p型、n型，或其組合)塊體矽。可使用適用於半導體元件形成的其它材料，諸如鍺、石英、藍寶石以及玻璃，可替代地用於基板110。或者，矽基板110可為有效的絕緣體上半導體(SOI)基板層，也可為多層結構如形成在塊體矽層上的矽鍺層。
在基板110中形成了複數個p阱區域116與複數個n阱區域112。每個n阱區域112形成在兩個p阱區域116之間。用P型摻雜劑材料如硼離子植入p阱區域116，並且用N型摻雜 劑材料如砷離子植入n阱區域112。在p阱區域116之植入期間，覆蓋遮罩(諸如光阻劑)於n阱區域112上，而在n阱區域112之植入期間，覆蓋遮罩(諸如光阻劑)p阱區域116上。
在基板110上形成複數個半導體鰭片122、124。半導體鰭片124形成在p阱區域116上，並且半導體鰭片122形成在n阱區域112上。在部分實施例中，半導體鰭片122、124包含矽。應注意的是，第1A圖中的半導體鰭片122、124的數目僅用來說明，且不應限制本揭示案所主張的範疇。本領域中之一般技術者可根據實際情況選擇適當數目的半導體鰭片122、124。
半導體鰭片122、124可藉由使用如光微影技術來圖案化並蝕刻基板110而形成。在部分實施例中，在基板110上方沉積光阻材料層(未圖示)。根據所需圖案(在此情形中為半導體鰭片122、124)照射(曝露)光阻材料層並且使光阻材料層顯影以移除一部分光阻材料。剩餘的光阻材料保護下層材料不受後續處理步驟如蝕刻的影響。應當指出的是，在蝕刻製程中亦可使用其它遮罩，諸如氧化物或者氮化矽遮罩。
在基板110上形成複數個隔離結構130。充當半導體鰭片122、124邊緣的淺溝槽隔離(STI)，隔離結構130可使用四乙氧基正矽酸鹽(TEOS)和氧作為前驅物藉由化學氣相沉積(chemical vapor deposition；CVD)來形成。在又部分其他實施例中，隔離結構130是絕緣體上半導體晶圓的絕緣體層。
參照第1B圖。在半導體鰭片122、124的部分上形成至少一個虛設閘極142，並且曝露半導體鰭片122、124的其它部分。虛設閘極142可橫跨多個半導體鰭片122、124。
如第1C圖所示，在基板110上方並且沿著虛設閘極142的側面形成複數個閘極間隔層140。在部分實施例中，閘極間隔層140可包括氧化矽、氮化矽、氧氮化矽，或者其它適合的材料。閘極間隔層140可包括單層或者多層結構。可藉由化學氣相沉積、物理氣相沉積(physical vapor deposition；PVD)、原子層沉積(atomic layer deposition；ALD)或者其它適當的技術來形成閘極間隔層140的毯覆層。隨後，在毯覆層上執行異向性蝕刻以在虛設閘極142的兩側上形成一對閘極間隔層140。在部分實施例中，閘極間隔層140用於偏移隨後形成的摻雜區域，諸如源極/汲極區域。閘極間隔層140可進一步用於設計或者改變源極/汲極區域(接面)之輪廓。
參照第1C圖。部分地移除(或者部分地開槽)半導體鰭片122、124中曝露虛設閘極142與閘極間隔層140外的部分，以在半導體鰭片122、124中形成溝槽R。在部分實施例中，溝槽R具有鰭狀介電側壁結構作為其上部部分。在部分實施例中，溝槽R的側壁實質上彼此垂直平行。在部分其他實施例中，溝槽R為非垂直的平行輪廓。
在第1C圖中，半導體鰭片122包括至少一個溝槽部分122r與至少一個通道部分122c。溝槽R形成在溝槽部分122r上，且虛設閘極142覆蓋通道部分122c。半導體鰭片124 包括至少一個溝槽部分124r與至少一個通道部分124c。溝槽R形成在溝槽部分124r上，且虛設閘極142覆蓋通道部分124c。
開槽製程可包含乾式蝕刻製程、濕式蝕刻製程及/或其組合。開槽製程亦可包括選擇性濕式蝕刻或者選擇性乾式蝕刻。濕式蝕刻溶液包括氫氧化四甲銨(TMAH)、氫氟酸(HF)/硝酸(HNO3)/乙酸(CH3COOH)溶液，或者其它合適的溶液。乾式蝕刻製程與濕式蝕刻製程具有可調控的蝕刻參數，諸如所使用的蝕刻劑、蝕刻溫度、蝕刻溶液濃度、蝕刻壓力、電源功率、射頻(radio frequency；RF)偏壓、射頻偏壓功率、蝕刻劑流動速率以及其它合適的參數。濕式蝕刻溶液可包括氨水(NH4OH)、氫氧化鉀(potassium hydroxide；KOH)、氫氟酸(hydrofluoric acid；HF)、氫氧化四甲銨(TMAH)、其它合適的濕式蝕刻溶液，或其組合。乾式蝕刻製程包括使用氯基的化學物質的偏壓電漿蝕刻製程。其它乾式蝕刻劑氣體包括四氟化碳(CF4)、三氟化氮(NF3)、六氟化硫(SF6)及氦(He)。亦可使用諸如深反應性離子蝕刻(deep reactive-ion etching；DRIE)的機制來異向性地執行乾式蝕刻。
參照第1D圖。在半導體鰭片124的溝槽R中分別形成複數個磊晶結構160，並且在半導體鰭片122的溝槽R中分別形成複數個磊晶結構150。磊晶結構160與相鄰的磊晶結構150分隔。磊晶結構150與160從溝槽R突出。磊晶結構160可為n型磊晶結構，而磊晶結構150可為p型磊晶結構。磊晶結 構150與160可使用一種或多種磊晶(epitaxy/epitaxial,epi)製程形成，使得半導體鰭片122、124上以結晶狀態形成矽(Si)特徵、矽鍺(SiGe)特徵及/或其他適宜特徵。在部分實施例中，磊晶結構150與160的晶格常數與半導體鰭片122、124的晶格常數不同，而使磊晶結構150與160經應變或受應力以賦能靜態隨機存取記憶體(SRAM)元件的載子遷移率並且增強元件效能。磊晶結構150與160可包括半導體材料如鍺(Ge)或者矽(Si)；或者化合物半導體材料，諸如砷化鎵(GaAs)、鋁砷化鎵(AlGaAs)、矽鍺(SiGe)、碳化矽(SiC)，或者磷砷化鎵(GaAsP)。
在部分實施例中，在不同的磊晶製程中形成磊晶結構150與160。磊晶結構160可包括磷化矽(SiP)、碳化矽(SiC)、碳磷化矽(SiPC)、矽(Si)、第III-V族化合物半導體材料或其組合，並且磊晶結構150可包括矽鍺(SiGe)、矽鍺碳(SiGeC)、鍺(Ge)、矽(Si)、第III-V族化合物半導體材料或其組合。在磊晶結構160之形成期間，n型雜質如磷或者砷可隨著磊晶的進行而摻雜。例如，當磊晶結構160包括碳化矽或矽時，摻雜n型雜質。此外，在磊晶結構150之形成期間，可隨著磊晶的進行而摻雜p型雜質，諸如硼或者二氟化硼。磊晶製程包括化學氣相沉積技術(例如：氣相磊晶(vapor-phase epitaxy；VPE)及/或超高真空化學氣相沉積技術(ultra-high vacuum CVD；UHV-CVD))、分子束磊晶及/或其它合適的製程。磊晶製程可使用氣態及/或液態前驅物，前驅物與半導體鰭片122、124的成分(例如，矽)反應。因此，受應變之通 道可以達到：增加載子遷移率及增強元件效能。磊晶結構150與160可為原位摻雜(in-situ doped)的。若磊晶結構150與160不是原位摻雜的，則執行第二植入製程(亦即，接面植入製程)以摻雜磊晶結構150與160。執行一個或多個退火製程來活化磊晶結構150與160。退火製程包括快速熱退火(rapid thermal annealing；RTA)及/或雷射退火製程。
在部分實施例中，磊晶結構150具有頂部部分，以及設置在頂部部分與基板110之間的本體部分。頂部部分的寬度比本體部分的寬度更寬。磊晶結構160具有頂部部分，以及設置在頂部部分與基板110之間的本體部分。頂部部分的寬度比本體部分的寬度更寬。磊晶結構150與160用作鰭式場效電晶體元件100的源極/汲極。
在部分實施例中，磊晶結構150與160具有不同的形狀。磊晶結構160的頂部部分可具有在隔離結構130上方存在的至少一個實質上為上刻面的表面，並且磊晶結構150的頂部部分可具有在隔離結構130上方存在的至少一個非刻面(或者圓形)表面，且所主張的範疇不限於此方面。
參照第1E圖。在形成磊晶結構150與160之後，移除虛設閘極142，由此在閘極間隔層140之間形成溝槽。使隔離結構130以及半導體鰭片122、124的一部分從溝槽中曝露。可以藉由執行一種或多種蝕刻製程來移除虛設閘極142。形成閘極堆疊170並填充溝槽。閘極堆疊170包括閘電極以及設置在閘電極與隔離結構130之間的閘極介電層。可藉由沉積製程(諸如原子層沉積製程、化學氣相沉積製程、物理氣相沉 積製程或濺射沉積製程)分別形成閘極介電質及閘電極。閘極介電層是用介電材料製成的，諸如氮化矽、氧氮化矽、具有高介電常數(high k)的介電質及/或其組合。在部分實施例中，閘電極是金屬電極。在部分實施例中，閘極堆疊170亦包括閘電極上的封端層。
在製造鰭式場效電晶體元件100之後，形成互連接結構以便將鰭式場效電晶體元件之電極互連接至其他元件。製造互連結構的細節在第2A圖至第2G圖中論述，其中第2A圖至第2G圖是在鰭式場效電晶體元件中製造互連結構的方法的局部橫截面圖。
參照第2A圖。在鰭式場效電晶體元件100上形成介電層220。介電層220覆蓋磊晶結構210以及圍繞磊晶結構210的隔離結構。磊晶結構210可為第1D圖中所論述的磊晶結構150與160中的任意一者。介電層220可為層間介電質(interlayer dielectric；ILD)且可含有氧化物材料或者低介電常數(low k)材料。介電層220可藉由例如化學氣相沉積處理步驟、旋塗處理步驟或其組合形成。介電層220用以隔離不同及/或相同層上形成之導電特徵。
參照第2B圖。在介電層220中形成開口222。在部分實施例中，介電層220中存在複數個開口。舉例而言，開口222可為接觸開口、通孔開口、單鑲嵌開口、雙鑲嵌開口，或其組合。開口222可藉由如以下步驟形成：在介電層220上方形成圖案化的光阻層(未圖示)並且藉由使用圖案化的光阻層(未圖示)作為遮罩並使用乾式蝕刻處理步驟來移除介 電層220的部分，以決定開口222之輪廓。可使用各種合適的乾式蝕刻製程。在乾式蝕刻處理步驟之後，藉由例如光微影移除製程來移除圖案化的光阻層(未圖示)。在形成開口222期間亦移除磊晶結構210中的一部分。
使磊晶結構210的一部分從開口222中曝露。選擇性地執行氧化物移除製程以在形成開口222之後移除存在於曝露的磊晶結構210上的氧化物層。
參照第2C圖。金屬層230形成在開口222的側壁與底部以及在介電層220上方。在部分實施例中，金屬層230可為金屬合金層。金屬層230包括用於自對準矽化物(salicide)技術的金屬，諸如鈦(Ti)、鈷(Co)、鎳(Ni)、鉑(Pt)或者鎢(W)。金屬層230是藉由沉積製程形成的，諸如化學氣相沉積製程、物理氣相沉積製程或者濺射沉積製程。
參照第2D圖。在金屬層230上形成阻障層240。阻障層240可作為阻障以防止隨後形成的導體擴散至下方介電層220。在部分實施例中阻障層240包括鉭(Ta)、鈦(Ti)等等。在部分實施例中，阻障層240具有約10埃至約250埃的厚度。在部分實施例中，金屬層230與阻障層240的組合厚度約小於120埃，以防止後續開口填充製程期間的縫隙填充問題。阻障層240是藉由使用物理氣相沉積、化學氣相沉積、電漿輔助化學氣相沉積(Plasma-Enhanced Chemical Vapor Deposition；PECVD)、低壓化學氣相沉積(Low-Pressue Chemical Vapor Deposition；LPCVD)或者其它熟知的沉積技術沉積的。
參照第2E圖。執行退火製程以在磊晶結構210上形成矽化物250。利用退火製程來將非晶矽化物轉化成低電阻多晶相(lower-resistance polycrystalline phase)。矽化物製程有時用於形成至源極與汲極區域的矽化物觸點，從而解決臨界尺寸的容限問題。在部分實施例中，金屬層為鈦層並經退火以變成矽化鈦。執行退火製程以形成富Ti相，並且矽化鈦的厚度在30埃至160埃的範圍中。在部分實施例中，若磊晶結構210為n型磊晶結構，矽化鈦可為二矽化鈦(TiSi2)。在部分實施例中，若磊晶結構210為p型磊晶結構，矽化鈦可為鈦矽鍺(TiSiGe)。
使用n型源極或汲極區域作為實例，當鈦與矽被帶入觸點且在高於500℃的溫度下加熱時，較高電阻率的C49-TiSi2相轉變成較低電阻率的C54-TiSi2相。C49-TiSi2相具有體心正交結構，每單位晶胞具有12個原子並且電阻率為60-90μΩ-cm。C54-TiSi2相具有面心正交結構，具有每單位晶胞24個原子以及比C49-TiSi2相顯著更低的電阻率(12-20μΩ-cm)。
以小於700℃的退火溫度及少於120秒的退火持續時間來執行退火製程。因此，矽濃度(對於n型源極或汲極區域)或者矽與鍺濃度(對於p型源極或汲極區域)隨著矽化物高度的不斷增大而降低，由於只有磊晶結構210的頂部擴散入金屬層230中。亦即，矽化鈦的頂部(例如，距離磊晶結構210較遠處)處的矽濃度或者矽與鍺濃度小於矽化鈦的底部(例如，靠近磊晶結構210)處的矽濃度或者矽與鍺濃度。矽 化物250中在矽化物250與阻障層240之間的介面處的矽濃度或者矽與鍺濃度小於在矽化物250與磊晶結構210之間的介面處的矽濃度或者矽與鍺濃度。
參照第2F圖。在阻障層240上方形成導體260以填充開口222。在部分實施例中，在介電層220中形成導體260以作為互連結構。在部分實施例中，導體260是藉由沉積製程形成的，諸如化學氣相沉積製程、物理氣相沉積製程或者濺射沉積製程。在部分實施例中，導體260包括鎢(W)或者銅(Cu)。
金屬層230的底部與磊晶結構210反應並且變成矽化物250。因此，剩餘的金屬層230存在於阻障層240與開口222的側壁之間且不存在於矽化物250與阻障層240之間。亦即，阻障層240的底部與矽化物250直接接觸，以使得互連結構的接觸電阻降低。
參照第2G圖。移除導體260在介電層220上方的部分。在部分實施例中，移除製程是化學機械研磨製程，經執行以移除導體260的過量部分、阻障層240以及開口222外部的金屬層230，從而曝露介電層220的頂表面並且獲得平坦化的表面。
上述互連結構不限於用於具有磊晶結構的鰭式場效電晶體元件，而是可用於具有矽化物觸點的任何合適的半導體元件。例如，上述互連結構可用於例如奈米線組件，如第3A圖至第3F圖中所論述的。
參照第3A圖至第3F圖。第3A圖至第3F圖是根據本揭示案的部分實施例，用於製造半導體元件的方法在各個階段的示意性斜視圖。參照第3A圖，此方法從絕緣體上半導體結構310開始。絕緣體上半導體結構310包括半導體基板312、內埋氧化物(buried oxide；BOX)層314以及絕緣體上半導體層316。在部分實施例中，絕緣體上半導體層316是由半導體材料如矽形成的。內埋氧化物層314可包括氧化矽、氮化矽或者氧氮化矽。內埋氧化物層314存在於半導體基板312與絕緣體上半導體層316之間。更詳細地，內埋氧化物層314可存在於絕緣體上半導體層316下方及半導體基板312的頂部處，且內埋氧化物層314可藉由將高能摻雜劑植入絕緣體上半導體結構310中並隨後將結構退火以形成埋入式氧化物層。在部分其它實施例中，可在形成絕緣體上半導體層316之前沉積或者生長內埋氧化物層314。在又部分其它實施例中，可使用晶圓鍵合技術來形成絕緣體上半導體結構310，其中鍵合的晶圓對是利用膠合劑、黏性聚合物，或者直接鍵合而形成。
參照第3B圖。絕緣體上半導體層316經圖案化以形成襯墊322、324、326與328，以及連接結構332與334。例如，襯墊322、324、326與328以及連接結構332與334可藉由使用合適的製程如光微影與蝕刻來製造。連接結構332連接襯墊322與324。連接結構334連接襯墊326與328。換言之，連接結構332中的至少一者可具有分離襯墊322與324在其相對側上，並且連接結構334中的至少一者可具有分離襯墊326與328在其相對側上的。
參照第3C圖。部分地移除連接結構332與334以形成第一奈米線342與第二奈米線344。在部分實施例中，藉由等向蝕刻製程移除連接結構332與334的下部部分以及內埋氧化物層314的下伏部分，以使得第一奈米線342懸吊在襯墊322與324之間，並且第二奈米線344懸吊在襯墊326與328之間。等向蝕刻是一種不不具優先方向的蝕刻形式。等向蝕刻的一個實例是濕式蝕刻。等向蝕刻製程形成底切區域，且第一奈米線342與第二奈米線344懸吊在其上方。在部分實施例中，可使用稀氫氟酸(diluted hydrofluoric acid；DHF)來執行等向蝕刻。在等向蝕刻製程之後，可將第一奈米線342與第二奈米線344平滑化以形成橢圓形(並且有時為圓柱形)結構。在部分實施例中，可藉由退火製程來執行平滑化製程。示例性退火溫度可在約600℃至約1000℃的範圍中，而退火製程中的氫氣壓力可在約7托至約600托的範圍中。
參照第3D圖。形成虛設閘極材料層362並橫越第一奈米線342，且形成虛設閘極材料層364並橫越第二奈米線344。間隔層352形成在虛設閘極材料層362的相對側壁上，且間隔層354形成在虛設閘極材料層364的相對側壁上。虛設閘極材料層362與364可為多晶矽。形成間隔層352與354的方法包括：形成介電層，並隨後執行蝕刻製程以移除介電層的一部分。
在形成間隔層352與354之後，可將n型摻雜劑引入與間隔層352相鄰的第一奈米線342的曝露部分，從而形成n型源極/汲極延伸區域。類似地，可將p型摻雜劑引入與間隔 層354相鄰的第二奈米線344的曝露部分中，從而形成p型源極/汲極延伸區域。p型摻雜劑的實例包括硼、鋁、鎵以及銦(但不限定於此些)。n型摻雜劑的實例包括銻、砷以及磷(但不限定於此些)。
在部分實施例中，在第一奈米線342與第二奈米線344中形成源極/汲極延伸區域，此形成應用原位摻雜磊晶生長製程隨後進行退火製程以驅使摻雜劑從原位摻雜磊晶半導體材料進入第一奈米線342及第二奈米線344中，來提供延伸區域。在部分實施例中，使用磊晶成長製程形成原位摻雜的半導體材料。「原位摻雜」意指在沉積原位摻雜的半導體材料中的含半導體材料之磊晶成長製程期間將摻雜劑併入原位摻雜的半導體材料。當控制化學反應物時，沉積原子到達第一奈米線342及受包覆的奈米線344以及襯墊322、324、326與328的表面，此等沉積原子具有足夠能量以在表面上四處移動並且使其自身定位至沉積表面的原子晶體排列。磊晶成長使得襯墊322、324、326與328以及第一奈米線342與第二奈米線344等未被虛設閘極材料層362與364以及間隔層352與354覆蓋的部分變厚。
此後，可對襯墊322、324、326以及328執行離子植入以形成深源極/汲極區域。深源極/汲極區域可使用離子植入來形成。在提供深源極/汲極區域的離子植入期間，元件中不需要植入的部分可用遮罩保護，諸如光阻遮罩。襯墊322與324中的深源極/汲極區域與第一奈米線342中的源極/汲極延伸區域具有相同的導電性摻雜劑，諸如n型摻雜劑，但是襯 墊322與324中的深源極/汲極區域具有比第一奈米線342中的源極/汲極延伸區域更大的摻雜劑濃度。類似地，襯墊326與328中的深源極/汲極區域與第二奈米線344中的源極/汲極延伸區域具有相同的導電性摻雜劑，諸如p型摻雜劑，但是襯墊326與328中的深源極/汲極區域具有比第二奈米線344中的源極/汲極延伸區域更大的摻雜劑濃度。
參照第3E圖。形成層間介電質層370以覆蓋虛設閘極材料層、第一奈米線342以及第二奈米線344。層間介電質層370可包括氧化矽、氮化矽、氧氮化矽、碳化矽、低介電常數介電材料，或其組合。可藉由沉積製程如化學氣相沉積製程來形成層間介電質層370。此後，移除層間介電質層370的部分以曝露虛設閘極材料層的頂表面。移除步驟可包括執行執行化學機械研磨(CMP)製程。藉由使用合適的製程如濕式蝕刻來進一步移除虛設閘極材料層。在移除虛設閘極材料層之後，在間隔層352之間形成了第一溝槽382，並且在間隔層354之間形成了第二溝槽384，且第一溝槽382與第二溝槽384藉由間隔層352、354以及層間介電質層370而彼此在空間上分離。
參照第3F圖。形成閘極堆疊390與392並且填充溝槽382與384。閘極堆疊390與392分別包括包覆奈米線的閘極介電層、包覆閘極介電層的閘電極，以及包覆閘電極的封端層。
在形成半導體元件300之後，在層間介電質層370中形成複數個互連結構以連接至襯墊322、324、326與328。第4圖圖示了互連結構與襯墊的橫截面圖。
如第4圖所示，互連結構400形成於層間介電質層370中並且與襯墊320接觸。襯墊320可為如第3F圖中所圖示的襯墊322、324、326與328中的任意一者。互連結構400包括金屬層410、矽化物420、阻障層430，以及導體440。製造互連結構400的細節與在第2A圖至第2G圖中描述的方法基本上相同。在層間介電質層370的開口中沉積金屬層410，並且金屬層的底部與襯墊320反應並且變成矽化物420。金屬層410存在於阻障層430與層間介電質層370的側壁之間，並且不存在於阻障層430與矽化物420之間。阻障層430與矽化物420直接接觸。形成導體440以填充開口。
在金屬層與阻障層沉積之後執行矽化物的退火製程。在退火製程期間，金屬層的底部接觸並且與源極或汲極區域反應，並且變成金屬矽化物。因此，金屬層存在於阻障層與開口的側壁之間，並且不存在於阻障層與矽化物之間。阻障層與矽化物直接接觸，從而降低了互連結構的接觸電阻。
根據本揭示案的部分實施例，半導體元件包括：包含接觸區域的半導體基板，存在於接觸區域上的矽化物，存在於半導體基板上的介電層，包含開口以曝露接觸區域的部分的介電層，存在於開口中的導體，存在於導體與介電層之間的阻障層，以及存在於阻障層與介電層之間的金屬層，其中矽化物的矽濃度沿著矽化物高度而變化。
根據本揭示案的部分實施例，互連結構包括矽化物，導體，存在於矽化物與導體之間的阻障層，以及存在於阻障層的側壁處之金屬層，其中矽化物的矽濃度沿著矽化物的高度而減小。
根據本揭示案的部分實施例，製造互連結構的方法包括：在介電層中形成開口以曝露接觸區域的部分；在開口的側壁上並且在接觸區域上形成金屬層；在金屬層上形成阻障層；以及在阻障層形成於金屬層上之後執行退火製程以在阻障層與接觸區域之間形成矽化物。
上文概述了若干實施例的特徵，以便本領域熟習此項技藝者可更好地理解本揭示案的態樣。本領域熟習此項技藝者應當瞭解到他們可容易地使用本揭示案作為基礎來設計或者修改其他製程及結構，以實行相同目的及/或實現相同優勢的。本領域熟習此項技藝者亦應當瞭解到，此類等效構造不脫離本揭示案的精神及範疇，以及在不脫離本揭示案的精神及範疇的情況下，其可對本文進行各種改變、取代及變更。
210‧‧‧磊晶結構
220‧‧‧介電層
222‧‧‧開口
230‧‧‧金屬層
240‧‧‧阻障層
250‧‧‧矽化物
260‧‧‧導體

Claims (7)

  1. 一種半導體元件，包含：一半導體基板，包含一接觸區域；一矽化物，存在於該接觸區域上；一介電層，存在於該半導體基板上，該介電層包含一開口以曝露該接觸區域的一部分；一導體，存在於該開口中；一阻障層，存在於該導體與該介電層之間；以及一金屬層，存在於該阻障層與該介電層之間且不存在於該阻障層與該矽化物之間，其中該矽化物的一矽濃度沿著該矽化物的一高度而變化。
  2. 如請求項1所述之半導體元件，其中該矽濃度沿著該矽化物的該高度而減小。
  3. 如請求項1所述之半導體元件，其中在該矽化物與該阻障層之間的一介面處的該矽濃度小於在該矽化物與該接觸區域之間的一介面處的矽濃度。
  4. 如請求項1所述之半導體元件，其中該矽化物的一材料包含鈦矽鍺，且一鍺濃度，如同該矽濃度一樣，沿著該矽化物的該高度而變化。
  5. 一種互連結構，包含： 一矽化物；一導體；一阻障層，存在於該導體的一側壁上且存在於該矽化物與該導體之間；以及一金屬層，存在於該阻障層的側壁處，其中該矽化物的一矽濃度沿著該矽化物的一高度而減小，且該金屬層不存在於該阻障層與該矽化物之間。
  6. 如請求項5所述之互連結構，其中該矽化物的一底部處的該矽濃度小於該矽化物的一頂部處的該矽濃度。
  7. 一種製造一互連結構的方法，該方法包含以下步驟：在一介電層中形成一開口以曝露一接觸區域的一部分；在該開口的一側壁上並且在該接觸區域上形成一金屬層；在該金屬層上形成一阻障層；以及在該阻障層形成於該金屬層上後執行一退火製程以在該阻障層與該接觸區域之間形成一矽化物，其中該矽化物的一矽濃度沿著該矽化物的一高度而減小，且該金屬層在該阻障層與該接觸區域之間的一部分與該接觸區域反應，使得該金屬層不存在於該阻障層與該矽化物之間。
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