CN106531686B - 互连结构和其制造方法及半导体器件 - Google Patents

互连结构和其制造方法及半导体器件 Download PDF

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CN106531686B
CN106531686B CN201610677823.7A CN201610677823A CN106531686B CN 106531686 B CN106531686 B CN 106531686B CN 201610677823 A CN201610677823 A CN 201610677823A CN 106531686 B CN106531686 B CN 106531686B
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silicide
layer
barrier layer
contact region
present
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CN106531686A (zh
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林瑀宏
刘继文
曾鸿辉
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种半导体器件包括：包括接触区域的半导体衬底；在接触区域上存在的硅化物；在半导体衬底上存在的介电层，介电层包括暴露出接触区域的部分的开口；在开口中存在的导体；在导体和介电层之间存在的阻挡层；以及在阻挡层和介电层之间存在的金属层，其中，硅化物的Si浓度沿着硅化物的高度而变化。本发明的实施例还提供了互连结构和其制造方法。

Description

互连结构和其制造方法及半导体器件
技术领域
本发明涉及互连结构和其制造方法以及半导体器件。
背景技术
半导体集成电路(IC)产业经历了快速增长。确实地，现代集成电路由诸如晶体管和电容器的上百万有源器件组成。IC材料和设计的技术进步产生了多代IC，其中，每代都具有比上一代更小且更复杂的电路。初始地，这些器件彼此隔离，但是稍后通过多个金属层互连在一起以形成功能电路。由于IC变得越来越复杂，互连结构也变得越来越复杂，导致金属层的数量增加。
互连结构可以包括诸如金属线(引线)的横向互连和诸如导电通孔和接触件的竖直互连。然而，复杂互连件限制现代集成电路的性能和密度。
发明内容
本发明的实施例提供了一种半导体器件，包括：半导体衬底，包括接触区域；硅化物，存在于所述接触区域上；介电层，存在于所述半导体衬底上，所述介电层包括暴露出所述接触区域的部分的开口；导体，存在于所述开口中；阻挡层，存在于所述导体和所述介电层之间；以及金属层，存在于所述阻挡层和所述介电层之间，其中，所述硅化物的Si浓度沿着所述硅化物的高度而变化。
本发明的另一实施例提供了一种互连结构，包括：硅化物；导体；阻挡层，存在于所述导体的侧壁上和存在于所述硅化物和所述导体之间；以及金属层，存在于所述阻挡层的侧壁处，其中，所述硅化物的Si浓度沿着所述硅化物的高度而减小。
本发明的又一实施例提供了一种制造互连结构的方法，所述方法包括：在介电层中形成开口以暴露出接触区域的部分；在所述开口的侧壁上和所述接触区域上形成金属层；在所述金属层上形成阻挡层；以及在所述金属层上形成所述阻挡层之后，实施退火工艺以在所述阻挡层和所述接触区域之间形成硅化物。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明的实施例。应该强调的是，根据工业中的标准实践，对各种部件没有按比例绘制并且仅仅用于说明的目的。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增大或缩小。
图1A至图1E是根据本发明的一些实施例的用于在各个阶段中制造FinFET器件的方法的示意性斜视图。
图2A至图2G是制造FinFET器件中的互连结构的方法的局部截面图。
图3A至图3F是根据本发明的一些实施例的用于在各个阶段中制造半导体器件的方法的示意性斜视图。
图4是根据本发明的一些其它实施例的互连结构的局部截面图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件形成为直接接触的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字母。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等的空间相对术语，以便于描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而在此使用的空间相对描述符可以同样地作相应的解释。
随着半导体器件尺寸持续缩小，满足导电性需求和多个金属制造中的可靠性已经变得越来越难。例如，包括金属线和将来自集成电路(IC)器件的不同层的金属线互连的导电通孔的互连结构的形成一般需要低电阻而且需要阻挡层以阻止导电通孔中的导电金属扩散至ILD层内。为了降低IC器件中的RC延迟，阻挡层还起到控制互连件的电阻率的作用。本发明涉及一种减小诸如FinFET器件的半导体器件中的互连结构的电阻的方法。
图1A至图1E是根据本发明的一些实施例的用于在各个阶段中制造FinFET器件的方法的示意性斜视图。参考图1A。提供衬底110。例如，在一些实施例中，衬底110可以是半导体材料并且可以包括已知的结构，包括梯度层或掩埋氧化物。在一些实施例中，衬底110包括可以是未掺杂或掺杂(如，p型、n型或它们的组合)的块状硅。可以使用适合于半导体器件形成的其他的材料。诸如锗、石英、蓝宝石和玻璃的其他的材料可以可选地用于衬底110。可选地，硅衬底110可以是绝缘体上半导体(SOI)衬底的有源层或诸如形成在块状硅层上的硅锗层的多层结构。
多个p阱区域116和多个n阱区域112形成在衬底110中。一个n阱区域112形成在两个p阱区域116之间。p阱区域116注入有P掺杂剂材料，诸如硼离子，并且n阱区域112注入有N掺杂剂材料，诸如砷离子。在p阱区域116的注入期间，n阱区域112覆盖有掩模(诸如光刻胶)，并且在n阱区域112的注入期间，p阱区域116覆盖有掩模(诸如光刻胶)。
多个半导体鳍122、124形成在衬底110上。半导体鳍124形成在p阱区域116上，并且半导体鳍122形成在n阱区域112上。在一些实施例中，半导体鳍122、124包括硅。应该注意的是图1A中的半导体鳍122、124的数量是说明性的，并不应当限制本发明的保护范围。本领域的技术人员可以根据实际情况选择合适的半导体鳍122、124的数量。
例如，可以通过使用光刻技术图案化和蚀刻衬底110来形成半导体鳍122、124。在一些实施例中，在衬底110上方沉积光刻胶材料层(未示出)。根据所需图案(这里为半导体鳍122、124)辐照(曝光)并显影光刻胶材料层，从而去除光刻胶材料的一部分。剩余的光刻胶材料保护下面的材料免受随后的工艺步骤(诸如蚀刻)的影响。应该注意，也可以在蚀刻工艺中使用诸如氧化物或氮化硅掩模的其他的掩模。
多个隔离结构130形成在衬底110上。作为围绕半导体鳍122、124的浅沟槽隔离(STI)的隔离结构130可以通过采用正硅酸乙酯(TEOS)和氧气为前体的化学气相沉积(CVD)技术来形成。在又一些其他的实施例中，隔离结构130是SOI晶圆的绝缘层。
参考图1B。至少一个伪栅极142形成在半导体鳍122、124的部分上，并暴露半导体鳍122、124的另外部分。伪栅极142可以形成为横越多个半导体鳍122、124。
如图1C所示，多个栅极间隔件140形成在衬底110上方并且沿着伪栅极142的侧部。在一些实施例中，栅极间隔件140可以包括氧化硅、氮化硅、氮氧化硅或其他合适的材料。栅极间隔件140可以包括单层或多层结构。栅极间隔件140的毯式层可以通过CVD、PVD、ALD或其他合适的技术来形成。然后，对毯式层执行各向异性蚀刻以在伪栅极142的两侧上形成一对栅极间隔件140。在一些实施例中，栅极间隔件140用于偏移随后形成的掺杂区域，诸如源极/漏极区域。栅极间隔件140还可以用于设计或改变源极/漏极区域(结)轮廓。
参考图1C。部分地去除(或部分地开沟)半导体鳍122、124的由伪栅极142和栅极间隔件142暴露的部分以在半导体鳍122、124中形成沟槽R。在一些实施例中，沟槽R形成有作为其上部的介电鳍侧壁结构125。在一些实施例中，沟槽R的侧壁基本相互平行并且相互垂直平行。在一些其它的实施例中，沟槽R形成有非垂直平行的轮廓。
在图1C中，半导体鳍122包括至少一个沟槽部分122r和至少一个沟道部分122c。沟槽R形成在沟槽部分122r上，并且伪栅极142覆盖沟道部分122c。半导体鳍124包括至少一个沟槽部分124r和至少一个沟道部分124c。沟槽R形成在沟槽部分124r上，并且伪栅极142覆盖沟道部分124c。
开沟工艺可以包括干蚀刻工艺、湿蚀刻工艺和/或它们的组合。开沟工艺还可以包括选择性湿蚀刻或选择性干蚀刻。湿蚀刻溶液包括四甲基氢氧化铵(TMAH)、HF/HNO3/CH3COOH溶液、或其他合适溶液。干蚀刻和湿蚀刻工艺具有可以调整的蚀刻参数，诸如所使用的蚀刻剂、蚀刻温度、蚀刻溶液浓度、蚀刻压力、源功率、RF偏置电压、RF偏置功率、蚀刻剂流量和其他合适的参数。例如，湿蚀刻液可以包括NH4OH、KOH(氢氧化钾)、HF(氢氟酸)、TMAH(四甲基氢氧化铵)、其他合适的湿蚀刻溶液或它们的组合。干蚀刻工艺包括使用氯基化学物质的偏置的等离子体蚀刻工艺。其他干蚀刻剂气体包括CF4、NF3、SF6、和He。也可以使用诸如DRIE(深反应离子蚀刻)的机制各向异性地实施干蚀刻。
参考图1D。多个外延结构160分别形成在半导体鳍124的沟槽R中，并且多个外延结构150分别形成在半导体鳍122的沟槽R中。外延结构160与邻近的外延结构150分离。外延结构150和160从沟槽R突出。外延结构160可以是n型外延结构，且外延结构150可以是p型外延结构。可以使用一个或多个外延或外延的(epi)工艺来形成外延结构150和160，从而使得可以在半导体鳍122、124上以晶体状态形成Si部件、SiGe部件和/或其他合适的部件。在一些实施例中，外延结构150和160的晶格常数不同于半导体鳍122、124的晶格常数，并且外延结构150和160被应变或受到应力以使SRAM器件实现载流子迁移以及提高器件的性能。外延结构150和160可以包括：诸如锗(Ge)或硅(Si)的半导体材料；诸如砷化镓(GaAs)、砷化铝镓(AlGaAs)、硅锗(SiGe)、碳化硅(SiC)、磷砷化镓(GaAsP)的化合物半导体材料。
在一些实施例中，在不同的外延工艺中形成外延结构150和160。外延结构160可以包括SiP、SiC、SiPC、Si、III-V族化合物半导体材料或它们的组合，并且外延结构150可以包括SiGe、SiGeC、Ge、Si、III-V族化合物半导体材料或它们的组合。在外延结构160的形成期间，可以随着外延的进行来掺杂诸如磷或砷的n型杂质。例如，当外延结构160包括SiC或Si时，掺杂n型杂质。此外，在外延结构150的形成期间，可以随着外延的进行来掺杂诸如硼或BF2的p型杂质。例如，当外延结构150包括SiGe时，掺杂p型杂质。外延工艺包括CVD沉积技术(例如，气相外延(VPE)和/或超高真空CVD(UHV-CVD))、分子束外延，和/或其他合适的工艺。外延工艺可以使用气体和/或液体前体，它们与半导体鳍122、124的组分(如，硅)相互作用。因此，可获得应变的沟道以提高载流子迁移率和加强器件性能。外延结构150和160可以是原位掺杂的。如果外延结构150和160不是原位掺杂的，那么将执行第二注入工艺(即，结注入工艺)以掺杂该外延结构150和160。可以执行一个或多个退火工艺以激活外延结构150和160。退火工艺包括快速热退火(RTA)和/或激光退火工艺。
在一些实施例中，外延结构150具有顶部和设置在顶部与衬底110之间的主体部分。顶部的宽度比主体部分的宽度宽。外延结构160具有顶部和设置在顶部与衬底110之间的主体部分。顶部的宽度比主体部分的宽度宽。外延结构150和160用作FinFET器件100的源极/漏极电极。
在一些实施例中，外延结构150和160具有不同的形状。外延结构160的顶部可以具有存在于隔离结构130之上的至少一个基本上刻面表面，并且外延结构150的顶部可以具有存在于隔离结构130之上的至少一个非刻面(或圆形)表面，并且不在这方面对所要求的范围进行限制。
参考图1E。在形成外延结构150和160之后，去除伪栅极142，从而在栅极间隔件140之间形成沟槽。隔离结构130和半导体鳍122、124的一部分从沟槽暴露。可以通过执行一个或多个蚀刻工艺来去除伪栅极142。形成栅极堆叠件170并且填充沟槽。栅极堆叠件170包括栅电极和在栅电极和隔离结构130之间设置的栅极电介质。可以通过诸如ALD工艺、CVD工艺、PVD工艺或溅射沉积工艺的沉积工艺分别地形成栅极电介质和栅电极。栅极电介质是由诸如氮化硅、氮氧化硅的介电材料、具有高介电常数(高k)的电介质和/或它们的组合制成的。在一些实施例中，栅电极是金属电极。在一些实施例中，栅极堆叠件170还包括位于栅电极上的覆盖层。
在制造FinFET器件100之后，形成互连结构以用于将FinFET器件的电极互连至其它器件。制造互连结构的细节在图2A至图2G中讨论，其中，图2A至图2G是制造FinFET器件中的互连结构的方法的局部截面图。
参考图2A。在FinFET器件100上形成介电层220。介电层220覆盖外延结构210和围绕外延结构210的隔离结构。外延结构210可以是如图1D所讨论的外延结构150和160的任意一个。介电层220可以是层间电介质(ILD)和可以包含氧化物材料或低k材料。介电层220可以通过例如化学汽相沉积(CVD)处理步骤、旋涂处理步骤或它们的组合形成。提供介电层220以隔离在不同和/或相同的层上形成的导电部件。
参考图2B。在介电层220中形成开口222。在一些实施例中，在介电层220中形成有多个开口。例如，开口222可以是接触开口、通孔开口、单镶嵌开口、双镶嵌开口、或它们的组合。例如，可以通过在介电层220上方形成图案化的光刻胶层(未示出)且使用干蚀刻处理步骤以去除介电层220的部分以通过使用图案化的光刻胶层(未示出)作为掩模限定开口222来形成开口222。可以使用各种合适的干蚀刻工艺。在干蚀刻处理步骤之后，通过例如光刻去除工艺去除图案化的光刻胶层(未示出)。在形成开口222期间还去除了外延结构210的一些。
该外延结构210的一部分从开口222暴露。在形成开口222之后，选择性地实施氧化物去除工艺以去除在暴露的外延结构210上存在的氧化物层。
参考图2C。形成金属层230以内衬开口222的侧壁和底部且位于介电层220上方。在一些实施例中，金属层230可为金属合金层。金属层230包括在自对准硅化物(自对准多晶硅化物)技术中使用的金属，诸如钛(Ti)、钴(Co)、镍(Ni)、铂(Pt)、或钨(W)。通过诸如CVD工艺、PVD工艺或溅射沉积工艺的沉积工艺形成金属层230。
参考图2D。在金属层230上形成阻挡层240。阻挡层240可以用作防止随后形成的导体扩散至下面的介电层220内的阻挡件。在一些实施例中，阻挡层240包括钽(Ta)、钛(Ti)等。在一些实施例中，阻挡层240具有约10埃至约250埃的厚度。在一些实施例中，金属层230和阻挡层240的组合厚度小于约120埃以防止在随后的开口填充工艺期间的间隙填充问题。通过使用PVD、CVD、PECVD、LPCVD、或其它众所周知的沉积技术沉积阻挡层240。
参考图2E。实施退火工艺以在外延结构210上形成硅化物250。利用退火工艺以将非晶硅化物转化至低电阻多晶相。有时使用自对准多晶硅化物工艺以形成至源极和漏极区域的硅化物接触件以解决临界尺寸容差的问题。在一些实施例中，金属层是钛层且被退火以变成硅化钛250。实施退火工艺以形成富Ti相，且硅化钛的厚度在从30埃至160埃的范围内。在一些实施例中，由于外延结构210是n型外延结构，硅化钛250可以是TiSi2。在一些实施例中，由于外延结构210是p型外延结构，硅化钛250可以是TiSiGe。
使用n型源极和漏极区域作为实例，当钛和硅接触且在500℃以上的温度下加热，更高的电阻率C49-TiSi2相转移至较低的电阻率C54-TiSi2相。C49-TiSi2相具有每个晶胞带有12个原子的正交底心结构和60-90μΩ-cm的电阻率。C54-TiSi2相具有每个晶胞带有24个原子的正交面心结构和比C49-TiSi2相显著较低的电阻率(12-20μΩ-cm)。
在小于700℃的退火温度下和小于120秒的退火持续时间内实施退火工艺。结果，由于仅有外延结构210的顶部扩撒至金属层230内，Si浓度(用于n型源极或漏极区域)或Si和Ge浓度(用于p型源极或漏极区域)随着硅化物高度的增大而减小。换言之，在硅化钛250的顶部处(例如，远离外延结构210)的Si浓度或Si和Ge浓度小于在硅化钛250的底部处(例如，接近外延结构210)的Si浓度或Si和Ge浓度。在硅化钛250和阻挡层240之间的界面处的硅化钛250的Si浓度或Si和Ge浓度小于在硅化钛250和外延结构210之间的界面处的Si浓度或Si和Ge浓度。
参考图2F。在阻挡层240上方形成导体260以填充开口222。在一些实施例中，导体260形成为介电层220中的互连结构。在一些实施例中，通过诸如CVD工艺、PVD工艺或溅射沉积工艺的沉积工艺形成导体260。在一些实施例中，导体260包括钨(W)或铜(Cu)。
金属层230的底部与外延结构210反应且变为硅化钛250。因此，剩余的金属层230存在于阻挡层240和开口222的侧壁之间且不存在于硅化钛250和阻挡层240之间。也就是，阻挡层240的底部与硅化钛250直接接触，从而减小了互连结构的接触电阻。
参考图2G。去除导体260的位于介电层220上方的部分。在一些实施例中，去除工艺是实施的化学机械抛光(CMP)工艺以去除导体260、阻挡层240和金属层230的位于开口222外部的多余部分，从而暴露出介电层220的顶面和实现平坦化的表面。
前述互连结构不限制于用于具有外延结构的FinFET器件，还可以用于具有硅化物接触件的任何合适的半导体器件。例如，前述互连结构可以用于例如纳米线组件，如图3A至图3F论述的。
参考图3A至图3F。图3A至图3F是根据本发明的一些实施例的用于在各个阶段中制造半导体器件的方法的示意性斜视图。参考图3A，该方法开始于绝缘体上半导体(SOI)结构310。SOI结构310包括半导体衬底312、埋氧层(BOX)314和SOI层316。在一些实施例中，SOI层316由诸如硅的半导体材料形成。BOX层314可以包括氧化硅、氮化硅或氮氧化硅。BOX层314存在于半导体衬底312和SOI层316之间。更详细地，BOX层314可以存在于SOI层316下面和处在半导体衬底312的顶部处，以及可以通过注入高能掺杂剂至SOI结构310且然后退火结构以形成埋氧层来形成BOX层314。在一些其它实施例中，在SOI层316的形成之前，可以沉积或生长BOX层314。在又一些其它实施例中，可以使用晶圆接合技术形成SOI结构310，其中利用胶、粘合聚合物、或直接接合形成接合的晶圆对。
参考图3B。图案化SOI层316以形成焊盘322、324、326和328以及连接结构332和334。例如，可以通过使用诸如光刻和蚀刻的合适的工艺制造焊盘322、324、326和328以及连接结构332和334。连接结构332连接焊盘322和324。连接结构334连接焊盘326和328。换言之，连接结构332的至少一个可以具有位于其相对侧上的分离的焊盘322和324，以及连接结构334的至少一个可以具有位于其相对侧上的分离的焊盘326和328。
参考图3C。部分地去除连接结构332和334以形成第一纳米线342和第二纳米线344。在一些实施例中，通过各向同性蚀刻工艺去除连接结构332和334的下部以及下面的BOX层314的部分，从而第一纳米线342形成为在焊盘322和324之间悬置，且第二纳米线344形成为在焊盘326和328之间悬置。各向同性蚀刻是一种不包括优选方向的蚀刻的形式。各项同性蚀刻的一个实例是湿蚀刻。各项同性蚀刻工艺形成第一纳米线342和第二纳米线344悬置在其上方的底切区域。在一些实施例中，可以使用稀释的氢氟酸(DHF)实施各项同性蚀刻。在各项同性蚀刻工艺之后，可以使第一纳米线342和第二纳米线344平滑以形成椭圆形(且在一些例子中，圆柱形)结构。在一些实施例中，可以通过退火工艺实施平滑工艺。例如，退火温度的范围可以从约600℃至约1000℃，且退火工艺中的氢气压力的范围可以从约7torr至约600torr。
参考图3D。横越第一纳米线342形成伪栅极材料层362，且横越第二纳米线344形成伪栅极材料层364。在伪栅极材料层362的相对侧壁上形成间隔件352，并且在伪栅极材料层364的相对侧壁上形成间隔件354。伪栅极材料层362和364可以是多晶硅。形成间隔件352和354的方法包括：形成介电层且然后实施蚀刻工艺以去除介电层的部分。
在间隔件352和354的形成之后，n型掺杂剂可以引入至第一纳米线342的邻近间隔件352的暴露部分从而形成n型源极/漏极延伸区域。相似地，p型掺杂剂可以引入至第二纳米线344的邻近间隔件354的暴露部分从而形成p型源极/漏极延伸区域。p型掺杂剂的实例包括但不限制于硼、铝、镓和铟。n型掺杂剂的实例包括但不限制于锑、砷和磷。
在一些实施例中，使用原位掺杂外延生长工艺和接下来的退火工艺在第一纳米线342和第二纳米线344中形成源极/漏极延伸区域以将来自原位掺杂的外延半导体材料的掺杂剂驱动至第一纳米线342和第二纳米线344内以提供延伸区域。在一些实施例中，使用外延生长工艺形成原位掺杂的半导体材料。“原位掺杂”意味着在沉积原位掺杂半导体材料的含半导体材料的外延生长工艺期间，将掺杂剂结合至原位掺杂半导体材料中。当控制化学反应物时，沉积原子到达第一纳米线342和第二纳米线344以及焊盘322、324、326和328的表面处以足够的能量在表面上四处运动且使它们自己向着沉积表面的原子的晶体布置定向。外延生长加厚焊盘322、324、326和328以及第一纳米线342和第二纳米线344的未被伪栅极材料层362和364以及间隔件352和354覆盖的部分。
之后，可以对焊盘322、324、326和328实施离子注入以形成深源极/漏极区域。可以使用离子注入形成深源极/漏极区域。在提供深源极/漏极区域的离子注入期间，其中注入是不期望的器件的部分可以由诸如光刻胶掩模的掩模保护。焊盘322和324的深源极/漏极区域具有与第一纳米线342中的源极/漏极延伸区域相同的导电性掺杂剂，诸如n型掺杂剂，但是焊盘322和324中的深源极/漏极区域具有与第一纳米线342中的源极/漏极延伸区域相比更大的掺杂剂浓度。相似地，焊盘326和328的深源极/漏极区域具有与第二纳米线344中的源极/漏极延伸区域相同的导电性掺杂剂，诸如p型掺杂剂，但是焊盘326和328中的深源极/漏极区域具有与第二纳米线344中的源极/漏极延伸区域相比更大的掺杂剂浓度。
参考图3E。形成层间介电(ILD)层370以覆盖伪栅极材料层、第一纳米线342和第二纳米线344。ILD层370可以包括氧化硅、氮化硅、氮氧化硅、碳化硅、低介电常数介电材料或它们的组合。ILD层370可以通过诸如CVD工艺的沉积工艺形成。之后，去除ILD层370的部分以暴露处伪栅极材料层的顶面。去除步骤可以包括实施化学机械抛光(CMP)工艺。通过使用诸如湿蚀刻的合适的工艺进一步去除伪栅极材料层。在伪栅极材料层的去除之后，在间隔件352之间形成第一沟槽382，且在间隔件354之间形成第二沟槽384，并且第一沟槽382和第二沟槽384通过间隔件352、354和ILD层370彼此空间地隔离。
参考图3F。栅极堆叠件390和392形成且填充沟槽382和384。栅极堆叠件390和392分别地包括包裹纳米线的栅极电介质、包裹栅极电介质的栅电极、以及包裹栅电极的覆盖层。
在形成半导体器件300之后，在ILD层370中形成多个互连结构以连接至焊盘322、324、326和328。在图4中示出互连结构和焊盘的截面图。
如图4所示，互连结构400形成在ILD层370中且与焊盘320接触。焊盘320可以是如图3F所示的焊盘322、324、326和328中的任意一个。互连结构400包括金属层410、硅化物420、阻挡层430、和导体440。制造互连结构400的细节基本上与图2A至图2G中描述的方法相同。金属层410沉积在ILD层370的开口中，且金属层的底部与焊盘320反应且变成硅化物420。金属层410存在于阻挡层430和ILD370的侧壁之间且不存在于阻挡层430和硅化物420之间。阻挡层430与硅化物420直接接触。形成填充开口的导体440。
在沉积金属层和阻挡层之后，实施自对准多晶硅化物的退火工艺。金属层的底部与源极或漏极区域接触和反应且在退火工艺期间变成金属硅化物。结果，金属层存在于阻挡层和开口的侧壁之间且不存在于阻挡层和硅化物之间。阻挡层与硅化物直接接触，从而减小了互连结构的接触电阻。
根据本发明的一些实施例，一种半导体器件包括：包括接触区域的半导体衬底；在接触区域上存在的硅化物；在半导体衬底上存在的介电层，介电层包括暴露出接触区域的部分的开口；在开口中存在的导体；在导体和介电层之间存在的阻挡层；以及在阻挡层和介电层之间存在的金属层，其中，硅化物的Si浓度沿着硅化物的高度而变化。
在上述半导体器件中，其中，所述金属层存在于所述阻挡层和所述介电层之间且不存在于所述阻挡层和所述硅化物之间。
在上述半导体器件中，其中，所述Si浓度沿着所述硅化物的高度而减小。
在上述半导体器件中，其中，在所述硅化物和所述阻挡层之间的界面处的所述Si浓度小于在所述硅化物和所述接触区域之间的界面处的Si浓度。
在上述半导体器件中，其中，所述硅化物的材料包括TiSi。
在上述半导体器件中，其中，所述硅化物的材料包括TiSiGe，且如所述Si浓度，Ge浓度沿着所述硅化物的高度而变化。
在上述半导体器件中，其中，所述接触区域是外延结构。
在上述半导体器件中，其中，所述接触区域是半导体焊盘。
根据本发明的一些实施例，一种互连结构，包括硅化物、导体、硅化物和导体之间存在的阻挡层、以及阻挡层的侧壁处存在的金属层，其中，硅化物的Si浓度沿着硅化物的高度而减小。
在上述互连结构中，其中，所述金属层不存在于所述阻挡层和所述硅化物之间。
在上述互连结构中，其中，所述金属层包括Ti、Co、Ni、Pt或W。
在上述互连结构中，其中，所述阻挡层包括Ta或Ti。
在上述互连结构中，其中，所述硅化物的底部处的Si浓度小于所述硅化物的顶部处的Si浓度。
在上述互连结构中，其中，所述阻挡层与所述硅化物直接接触。
在上述互连结构中，其中，所述导体包括W或Cu。
根据本发明的一些实施例，一种制造互连结构的方法，包括：在介电层中形成开口以暴露出接触区域的部分；在开口的侧壁上和接触区域上形成金属层；在金属层上形成阻挡层；以及在金属层上形成阻挡层之后实施退火工艺以在阻挡层和接触区域之间形成硅化物。
在上述方法中，其中，所述接触区域包括硅。
在上述方法中，其中，所述金属层的位于所述阻挡层和所述接触区域之间的部分与所述接触区域反应，从而所述金属层不存在于所述阻挡层和所述硅化物之间。
在上述方法中，其中，通过实施沉积工艺分别地形成所述金属层和所述阻挡层。
在上述方法中，还包括：形成填充所述开口的导体。
上面概述了若干实施例的部件、使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实现与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围、并且在不背离本发明的精神和范围的情况下，在此他们可以做出多种变化、替换以及改变。

Claims (20)

1.一种半导体器件，包括：
半导体衬底，包括接触区域；
硅化物，存在于所述接触区域上，其中，所述接触区域的上表面具有凹进部，所述硅化物的底部与所述凹进部直接接触；
介电层，存在于所述半导体衬底上，所述介电层包括暴露出所述接触区域的部分的开口；
导体，存在于所述开口中；
阻挡层，存在于所述导体和所述介电层之间；以及
金属层，存在于所述阻挡层和所述介电层之间，其中，所述硅化物的Si浓度沿着所述硅化物的高度而变化。
2.根据权利要求1所述的半导体器件，其中，所述金属层存在于所述阻挡层和所述介电层之间且不存在于所述阻挡层和所述硅化物之间。
3.根据权利要求1所述的半导体器件，其中，所述Si浓度沿着所述硅化物的高度而减小。
4.根据权利要求1所述的半导体器件，其中，在所述硅化物和所述阻挡层之间的界面处的所述Si浓度小于在所述硅化物和所述接触区域之间的界面处的Si浓度。
5.根据权利要求1所述的半导体器件，其中，所述硅化物的材料包括TiSi。
6.根据权利要求1所述的半导体器件，其中，所述硅化物的材料包括TiSiGe，且如所述Si浓度，Ge浓度沿着所述硅化物的高度而变化。
7.根据权利要求1所述的半导体器件，其中，所述接触区域是外延结构。
8.根据权利要求1所述的半导体器件，其中，所述接触区域是半导体焊盘。
9.一种互连结构，包括：
硅化物，存在于接触区域上，其中，所述接触区域的上表面具有凹进部，所述硅化物的底部与所述凹进部直接接触；
导体；
阻挡层，存在于所述导体的侧壁上和存在于所述硅化物和所述导体之间；以及
金属层，存在于所述阻挡层的侧壁处，其中，所述硅化物的Si浓度沿着所述硅化物的高度而减小。
10.根据权利要求9所述的互连结构，其中，所述金属层不存在于所述阻挡层和所述硅化物之间。
11.根据权利要求9所述的互连结构，其中，所述金属层包括Ti、Co、Ni、Pt或W。
12.根据权利要求9所述的互连结构，其中，所述阻挡层包括Ta或Ti。
13.根据权利要求9所述的互连结构，其中，所述硅化物的底部处的Si浓度小于所述硅化物的顶部处的Si浓度。
14.根据权利要求9所述的互连结构，其中，所述阻挡层与所述硅化物直接接触。
15.根据权利要求9所述的互连结构，其中，所述导体包括W或Cu。
16.一种制造互连结构的方法，所述方法包括：
在介电层中形成开口以暴露出接触区域的部分；
在所述开口的侧壁上和所述接触区域上形成金属层；
在所述金属层上形成阻挡层；以及
在所述金属层上形成所述阻挡层之后，实施退火工艺以在所述阻挡层和所述接触区域之间形成硅化物并且在所述接触区域的上表面形成凹进部，其中，所述硅化物的底部与所述凹进部直接接触，所述硅化物的Si浓度沿着所述硅化物的高度而减小。
17.根据权利要求16所述的制造互连结构的方法，其中，所述接触区域包括硅。
18.根据权利要求16所述的制造互连结构的方法，其中，所述金属层的位于所述阻挡层和所述接触区域之间的部分与所述接触区域反应，从而所述金属层不存在于所述阻挡层和所述硅化物之间。
19.根据权利要求16所述的制造互连结构的方法，其中，通过实施沉积工艺分别地形成所述金属层和所述阻挡层。
20.根据权利要求16所述的制造互连结构的方法，还包括：形成填充所述开口的导体。
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