經濟部智慧財產局員工消費合作社印製 〆彳 ίΉ /、/、 ί (L (U A7 _____ _ B7 五、發明説明（I ) 發明之背景： (υ發明之技術領域： 本發明係有關於一種積體電路半導體裝 置，尤指一種用於製造積體電路用之具有自動 對準且無邊際之多晶矽及金屬接觸插塞的多 層內連線的方法。本方法在用於製作連接至基 板上之Ν_型接觸的低漏電流多晶矽Ν型摻雜 接觸插塞，以及同時製作連接至基板上之Ν+ 與Ρ+型接觸的低接觸電阻金屬接觸係特別地 有用。 (2)習知技術之說明： 製造於半導體基板上的極大型積體 (ULSI)電路需要多層金屬內連線，以將半導 體晶片上的半導體裝置做電性上的連接。在傳 統方法中，不同層的金屬相連係以絕緣材料層 隔離。這些置於中間的絕緣層係被蝕刻出接觸 孔及介層孔，該孔洞係被用以將金屬層電連接 至下面的半導體基板及其他定義下面導電 層，諸如摻雜多晶矽、多晶砂化金屬（多晶矽 /矽化物）層與其他相似者。 然而，在下一世代的積體電路中，由於半 導體裝置最小特徵尺寸的減少（例如，〇.25um 或更小的最小特徵尺寸）以及導線/間距的收 -______3 本紙張尺度適财關家轉（CNS>A4規格（2Η)>〇97公釐) ~ Μ--r------^------、訂------Φ (請先聞讀背面之注意事項再填寫本頁) ：7270 A7 B7 五、發明説明（>) 縮。此將使得接觸孔或介層孔的縱橫比（高度 /寬度）急遽地增加。因此，難以製作連接至下 面基板上之各N_、N+與P+接觸以及連接至矽 化鎢和/或鎢導線的接觸窗口，因爲接觸窗口具 有高縱橫比。此將使其難以在無損傷基板的情 況下，蝕刻連接至基板的接觸孔。 爲更瞭解該項問題，第1.圖係表示以習知 技術所製作之傳統式接觸窗口在一半導體基 板上部份完成的積體電路的示意截面圖。該截 面係表示一具有場效電晶體（FET )的基板1 0， 該電晶體的閘極電極1 6具有一覆蓋氧化物18 與間隙壁20及一閘極氧化物14。形成低漏電 流接觸用之微量摻雜源極/汲極區17(Ν·)在鄰 接於第一種形式的裝置區域中的部份FET上 的閘極電極旁，而Ν+及Ρ+型接觸19(Ν+或Ρ + 型）諸如CMOS電路之低接觸電阻（Rc)係形 成於第二種形式的裝置區域中。一平坦的第一 絕緣層或一中間多晶氧化矽（IP0 )層22係用 以將FET絕緣，且諸如矽化鎢或鎢等次一層的 導線23係被形成於其上，其中該導線具有一 覆蓋氧化物層26及間隙壁28。一第二絕緣層 40係被沈積以將導線24絕緣，並被平坦化。 其次，導線連接係藉由蝕刻連接至基板1 〇、連 接至FET閘極電極16以及連接至次層中間導 本紙張尺度適用中國國家標準（CNS ) A4規格（2!OX297公釐） ^ ：^-- (請先閱讀背面之注意事項再填寫本頁) -訂 線 經濟部智慧財產局員工消費合作钍印製 經濟部智慧財產局員工消資合作社印製 A7 B7 五、發明説明（一） 線23的高縱橫比接觸窗口 c而形成。當這些 接觸窗蝕刻至基板上的淺N_型接觸時，係難以 避免基板的過度飩刻（凹槽化）並將破壞N-、 N +及P +與基板之接觸面，如第1圖中的點n 所述。再者，對於這些緊密間距的閘極電極16 而言，難以在不傷害多晶矽閘極電極的情況下 將窗口 C蝕刻至基板，此將產生如第1圖的點 C所示的短路。再者，在蝕刻接觸C至基板的 期間，難以避免將接觸C1過度蝕刻至下一層之 中間導線23，如第1圖中的點0所示。 若干個製作高縱橫比無邊際接觸窗的方法 已於先前參考文獻中揭露。一種用於製作無邊 際接觸的方法係被說明於Mr. Barber等人所發 表的美國專利第4,966,870號中，其中當該無 邊際接觸窗蝕刻形成於沈積於上層的氧化矽 層中時，一氮化矽蝕刻終止層係使用於該基板 上。其他用於製作高縱橫比無邊際接觸於絕緣 體中的方法係說明於Mr. Liang等人所發表的 美國專利第5,665,623號中，其中小於目前光 學微影解析度最小特徵尺寸的無邊際接觸係 被製作於源極/汲極區上’其係利用局部矽氧化 法（LOCOS)時由場氧化物所產生的氧化。Mr. Huang等人所發表的美國專利第5,674,781號 及第5,654,589號係說明一鈦/氮化鈦（Ti/TiN) ^ Γ ^------、1T------線 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家橾準（CNS ) Α4規洛UIOXW7公釐） A7 B7 經濟部智慧財產局員工消費合作社印製 五'發明説明（g) 層被用以製作一鈦/氮化鈦堆疊內連線結構而 形成局部內連線及接觸插塞於相同層的方法 及結構。 因此，在工業上，提供一種用於製作多層 互連結構用之改良式接觸插塞的簡易方法係 爲所需，其將減少接觸窗口的縱橫比並避免基 板損傷。 發明之簡要說明： 本發明之主要目的係爲提供一種製作具有 多層內連用之自動對準無邊界接觸的多晶矽 及金屬接觸插塞於積體電路上。 本發明之另一目的係爲在多晶矽/金屬接 觸插塞形成期間，同時製作金屬/多晶矽內連導 線，因而簡化製造步驟。 本發明之再一目的係爲形成連接至N_型摻 雜基板接觸的N +型多晶矽接觸，並同時形成連 接至N +及P +型摻雜區的金屬接觸，以提供改 良式之低接觸電阻（Rc)。 本發明之又一目的係爲使用該多晶矽及金 屬接觸插塞，而蝕刻具有減少縱橫比的接觸窗 □。 本發明之另一目的係爲使用製作該等多晶 矽/金屬接觸插塞的方法，而製作改良式動態隨 機存取記憶體（DRAM)電路。 ___ 6 ^ ^^1τ------0 (請先閱讀背面之注土^^項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐} A7 B7 經濟部智慧財產局員工消費合作fi印製 五、發明説明（夕） 本發明主要係揭露一種用以製作具有多層 內連線用之自行對齊無邊界接觸的多晶矽及 金屬接觸插塞的方法。本方法提供用以形成低 漏電流之連接到Ν_型摻雜基板接觸的Ν +型摻 雜多晶矽插塞，如DRAM裝置上之電容器節點 接觸所欲者；並提供低接觸電阻（Rc)之連接到 基板上之N+及P+型摻雜接觸的金屬接觸，諸 如在CMOS電路用之DRAM晶片周邊區域中 者。 本方法係以提供一具有第一及第二裝置區 的半導體基板開始，其中該第一裝置區需要連 接至N·型基板接觸的N+型多晶矽接觸，而該 第二裝置區則需要連接至基板上之大量摻雜 N +及P +型接觸的金屬接觸。該基板係典型地爲 具有<1〇〇>結晶取向的單晶矽，並包含有用於 製作具有該等P +及N +型接觸的P通道及N通 道FET的N及P型井。一相當厚的場氧化物 (FOX)形成，該場氧化物係環繞基板中及基 板上之各裝置區並將其隔離。一種形成場氧化 物的傳統方法係爲工業界所普遍使用的淺溝 渠隔離法（STI)。其次，該FET係以熱氧化 法在裝置區上成長一薄的閘極氧化物而形 成。一 N +型摻雜多晶矽層及一耐高溫金屬矽化 物層係被沈積以形成一多晶金屬矽化物層。一 Μ民張尺度適用t國國家標準（cNS ) A4規格（210X297公釐 ^ ^^ΪΤ------m {諳先閱讀背面之注意事項再填寫本頁) 417273 A7 ________ B7 五、發明説明（么） 由氧化矽/氮化矽所組成的覆蓋氧化物係被沈 積於該多晶矽化金屬層上，且該多層結構係於 續序定義，以形成具有該覆蓋氧化物的閘極電 極。微量摻雜源極/汲極區（LDD )係於鄰接閘 極電極處植入，以改良裝置特性（使短通道效 應最小化）。無邊際多晶矽及金屬接觸插塞係 自動對準於閘極電極而形成。第一氮化矽 (Si3N4)層係沈積並部份地回蝕，以形成間隙壁 於閘極電極上並保護該裝置區。在第二裝置區 中的N+及P +型接觸區係藉由使用離子植入與 光阻罩幕植入砷（As)或磷（P)離子於N+型接 觸’以及植入硼（B)離子於P +接觸中形成。可 用氧化矽（Si〇2)所組成之一第一絕緣層係以低 壓化學氣相沈積法（LPC VD )沈積，並以諸如 化學機械硏磨法（CMP )平坦化。一第一光阻 罩幕及非等向性電漿蝕刻係用來做選擇性地 蝕刻第一接觸窗口於該第一裝置區中。用於多 晶矽接觸插塞之第一裝置區中的第一接觸窗 口係在該第一絕緣層中被蝕刻至的第一Si3N4 層處’並自行對齊於FET閘極電極。移除在第 .一接觸窗口中的該第一Si3N4層使於後續.與暴 露出基板上的N·接觸。移除該第一光阻罩幕 後，一 N+型摻雜多晶矽層係沈積於基板上，而 與>Γ源極/汲極接觸區接觸。一第二光阻罩幕 責家標 Γ(7ν·5 ) --- . „ '餐------IT------.4 (請先閲讀背面之注意事項再填寫本頁) 417270 at 五、發明説明（^ ) 及非等向性蝕刻係使用在多晶矽層及第一絕 緣層中選擇性地蝕刻第二窗口至閘極電極，並 在位於基板上之第二裝置區中的N +及P +接觸 區上方第一絕緣層中部份地蝕刻。在N+及P + 接觸上方之第二窗口中所殘留的部份Si02第 一絕緣層係於後續被選擇性地蝕刻至第一 31以4處。在第二窗口中的該第一 Si3N4層係於 後續使用選擇性地鈾刻，使其中暴露出基板上 的N +及P +接觸。一鈦/氮化鈦第一阻障層係被 沈積於N+型多晶矽層上以及第二接觸窗口 中，而與第二裝置區中的N+及P+型接觸做電 性接觸。一第一鎢金屬層係沈積於第一阻障層 上，且其足夠厚以塡充該第一及第二窗口。鎢 亦沈積至足以提供一平坦表面的厚度。一第二 Si3N4層係沈積，而該第二Si3N4層、該第一鎢 金屬層、該第一阻障層及該多晶砂層係定義以 形成局部之內連線。同時在定義期間，N+型摻 雜多晶矽接觸插塞係形成於該第一裝置區 中，且鎢金屬接觸插塞係形成以連接至第二裝 置區中的N +及P +接觸區^ 一第三Si3N4層係沈 積並回蝕，以形成間隙壁於局部內連線上。沈 積一CVD Si02第二絕緣層並以CMP法平坦 化。蝕刻多層接觸孔（介層孔）於第二絕緣層 中至多晶矽接觸插塞、至鎢金屬接觸插塞並至 9 玉紙張尺度適β中囡囤家標净（ΓΝ5 ) Λ4規格（：：丨OX 297公替） —'J. t -1 I L - -I II - II — ,11^- I (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（y) 內連線。該自動對準接觸插塞將避免基板中之 接觸的過度蝕刻，以及如習知技術所普遍發生 的蝕刻至閘極電極情況。再者，該自動對準接 觸插塞將減少介層孔的縱橫比，而使其更容易 蝕刻次微米寬的介層孔。藉由沈積一鈦/氮化鈦 第二阻障層及一第二鎢金屬層而完成至該方 法的第一層金屬=毯覆式地回蝕該鎢金屬層及 該第二阻障層，以將介層孔中的金屬插塞形成 多晶矽接觸插塞及鎢接觸插塞。被沈積並刻劃 由鈦-氮化鈦/鋁化銅/氮化鈦（Ti-TiN/AlCu/TiN) 所組成的導電金屬多層結構，以完成至第一層 的金屬相連的積體電路。 圖式之簡要說明： 第1圖係用於說明以習知技術所製作之一 多層內連結構的截面示意圖，並表示出將產生 可靠度方面之問題：基板上的N·接觸的接觸腐 蝕以及FET閘極電極的蝕刻。 第2圖至第12圖係爲表示藉由使用無邊際 自行對齊多晶矽及金屬接觸插塞，而用於製作 改良式多層內連的製程步驟順序的截面示意 圖，其將可避免習知技術所產生的可靠度問 題。 符號說明：Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs / 、 / 、 ί (L (U A7 _____ _ B7 V. Description of the Invention (I) Background of the Invention: (υ Field of Invention: The present invention relates to a Integrated circuit semiconductor device, especially a method for manufacturing multilayer circuits with automatic alignment and borderless polycrystalline silicon and metal contact plugs for manufacturing integrated circuits. The method is used for manufacturing a connection to a substrate Low leakage current polycrystalline silicon N-type doped contact plugs with N-type contacts, and low-contact resistance metal contacts that are simultaneously connected to N + and P + -type contacts on a substrate are particularly useful. (2) Known techniques Description: Ultra large integrated circuit (ULSI) circuits manufactured on semiconductor substrates require multiple layers of metal interconnects to electrically connect semiconductor devices on semiconductor wafers. In traditional methods, metal connections on different layers are connected by Isolation of insulating material layers. These interposed insulating layers are etched into contact holes and via holes, which are used to electrically connect the metal layer to the underlying semiconductor substrate and other definitions. Surface conductive layers, such as doped polycrystalline silicon, polycrystalline sanded metal (polycrystalline silicon / silicide) layers, and others are similar. However, in the next generation of integrated circuits, due to the reduction in the minimum feature size of semiconductor devices (for example, 0. 25um or less minimum feature size) and wire / pitch collection -______ 3 This paper is suitable for financial and family transfer (CNS > A4 size (2Η) > 〇97mm) ~ Μ--r ----- -^ ------ 、 Order ------ Φ (Please read the notes on the back before filling this page): 7270 A7 B7 V. Description of the invention (>) Shrink. This will make the contact hole Or the aspect ratio (height / width) of the via hole increases sharply. Therefore, it is difficult to make a contact window connected to each of N_, N + and P + on the underlying substrate and to a tungsten silicide and / or tungsten wire because the contact window Has a high aspect ratio. This will make it difficult to etch contact holes connected to the substrate without damaging the substrate. To better understand this problem, Figure 1. shows a traditional contact window made using conventional techniques Schematic cross-section of an integrated circuit partially completed on a semiconductor substrate The cross section represents a substrate 10 with a field effect transistor (FET), and the gate electrode 16 of the transistor has a covering oxide 18 and a spacer 20 and a gate oxide 14. A low leakage current is formed. The trace-doped source / drain region 17 (N ·) for the contact is next to the gate electrode on a part of the FET adjacent to the device region of the first form, and the N + and P + type contacts 19 (N + Or P + type) Low contact resistance (Rc) such as a CMOS circuit is formed in the device region of the second form. A flat first insulating layer or an intermediate polycrystalline silicon oxide (IP0) layer 22 is used to The FET is insulated, and a sub-layer wire 23 such as tungsten silicide or tungsten is formed thereon, wherein the wire has a cover oxide layer 26 and a spacer 28. A second insulating layer 40 is deposited to insulate the wires 24 and is planarized. Secondly, the wire connection is connected to the substrate 10 by etching, to the FET gate electrode 16 and to the sublayer intermediate guide. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (2! OX297 mm) ^: ^ -(Please read the precautions on the back before filling out this page)-Ordering line Consumer cooperation with the Intellectual Property Bureau of the Ministry of Economic Affairs 钍 Printing A7 B7 printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of invention (I) Line A high aspect ratio of 23 is formed by contacting the window c. When these contact windows are etched into shallow N_ contacts on the substrate, it is difficult to avoid excessive engraving (grooving) of the substrate and will damage the contact surfaces of N-, N +, and P + with the substrate, as shown in Figure 1. Point n in. Furthermore, it is difficult for these closely-spaced gate electrodes 16 to etch the window C to the substrate without damaging the polycrystalline silicon gate electrode, which will cause a short circuit as shown at point C in FIG. 1. Furthermore, it is difficult to avoid over-etching the contact C1 to the intermediate conductor 23 of the next layer during the period from the contact C to the substrate, as indicated by point 0 in the first figure. Several methods for making high-aspect-ratio borderless contact windows have been disclosed in previous references. A method for making a borderless contact is described in U.S. Patent No. 4,966,870 issued by Mr. Barber et al., Wherein when the borderless contact window is etched and formed in a silicon oxide layer deposited on an upper layer, a nitrogen A siliconized etching stop layer is used on the substrate. Other methods for making high aspect ratio non-marginal contact in insulators are described in U.S. Patent No. 5,665,623 issued by Mr. Liang et al., Where the non-marginal contact system is smaller than the smallest feature size of current optical lithography resolution. Fabricated on the source / drain region. It is the oxidation produced by field oxide when using local silicon oxidation (LOCOS). U.S. Patent Nos. 5,674,781 and 5,654,589 issued by Mr. Huang et al. Describe a titanium / titanium nitride (Ti / TiN) ^ Γ ^ ------, 1T ------ line (please Please read the notes on the back before filling in this page) This paper size is applicable to China National Standards (CNS) Α4 规 罗 OXOXW7mm) A7 B7 Printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs on the 5 'Invention (g) Method and structure for making a titanium / titanium nitride stack interconnect structure to form local interconnects and contact plugs in the same layer. Therefore, in the industry, it is desirable to provide a simple method for making an improved contact plug for a multilayer interconnect structure, which will reduce the aspect ratio of the contact window and avoid substrate damage. Brief description of the invention: The main object of the present invention is to provide a polycrystalline silicon and metal contact plug with automatic alignment without boundary contact for multilayer interconnections on a integrated circuit. Another object of the present invention is to simultaneously fabricate metal / polysilicon interconnecting leads during the formation of the polysilicon / metal contact plug, thereby simplifying the manufacturing steps. Another object of the present invention is to form an N + -type polycrystalline silicon contact connected to an N-type doped substrate contact, and simultaneously form a metal contact connected to the N + and P + -type doped regions to provide an improved low contact. Resistance (Rc). Another object of the present invention is to use the polycrystalline silicon and metal contact plugs to etch a contact window having a reduced aspect ratio. Another object of the present invention is to make an improved dynamic random access memory (DRAM) circuit by using the method of making the polycrystalline silicon / metal contact plugs. ___ 6 ^ ^^ 1τ ------ 0 (Please read the note on the back ^^ before filling this page) This paper size applies to China National Standard (CNS) A4 (210X297 mm) A7 B7 Ministry of Economic Affairs Intellectual Property Bureau employee consumer cooperation fi print 5. Description of the invention (Even) The present invention mainly discloses a method for making self-aligned, non-border contact polycrystalline silicon and metal contact plugs with multilayer interconnects. This method provides N + doped polycrystalline silicon plugs connected to N_ doped substrate contacts for forming low leakage current, such as capacitor nodes on DRAM devices contacting the desired one; and providing low contact resistance (Rc) connections to the substrate N + and P + -type doped contacts on metal contacts, such as those in peripheral areas of DRAM wafers for CMOS circuits. The method begins by providing a semiconductor substrate having first and second device regions, where the first device The second device region needs to be connected to a large number of doped N + and P + -type metal contacts on the substrate. The substrate is typically a < 1〇〇 > Crystal-oriented single crystal silicon, including N and P type wells for making P channel and N channel FETs with such P + and N + type contacts. A fairly thick field oxide (FOX) is formed, The field oxide system surrounds and isolates device regions in and on the substrate. A traditional method of forming field oxides is the shallow trench isolation (STI) method commonly used in industry. Second, the FET is based on The thermal oxidation method is formed by growing a thin gate oxide on the device region. An N + -type doped polycrystalline silicon layer and a high temperature resistant metal silicide layer are deposited to form a polycrystalline metal silicide layer. Zhang scale is applicable to the national standard (cNS) A4 specification (210X297 mm ^ ^^ ΪΤ ------ m {谙 Please read the precautions on the back before filling this page) 417273 A7 ________ B7 V. Description of the invention (? A capping oxide system composed of silicon oxide / silicon nitride is deposited on the polycrystalline metal silicide layer, and the multilayer structure is defined in a sequential order to form a gate electrode having the capping oxide. Trace doping The source / drain region (LDD) is planted adjacent to the gate electrode. In order to improve the device characteristics (minimize the short channel effect). Infinity polycrystalline silicon and metal contact plugs are formed by automatically aligning with the gate electrode. The first silicon nitride (Si3N4) layer is deposited and partially returned Etching to form a gap on the gate electrode and protect the device region. The N + and P + type contact regions in the second device region are implanted with arsenic (As) or Phosphorus (P) ions are formed in the N + contact and implanted boron (B) ions are formed in the P + contact. One of the first insulating layers composed of silicon oxide (SiO2) can be formed by a low-pressure chemical vapor deposition method ( LPC VD) is deposited and planarized by methods such as chemical mechanical honing (CMP). A first photoresist mask and anisotropic plasma etching are used to selectively etch the first contact window in the first device region. The first contact window in the first device region for the polysilicon contact plug is at the first Si3N4 layer etched in the first insulating layer 'and is aligned with the FET gate electrode by itself. The first Si3N4 layer in the first contact window is removed for subsequent contact with the N · on the exposed substrate. After the first photoresist mask is removed, an N + -type doped polycrystalline silicon layer is deposited on the substrate and is in contact with the > Γ source / drain contact region. A second photoresist cover curtain label Γ (7ν · 5) ---. „'Meal ------ IT ------. 4 (Please read the precautions on the back before filling this page ) 417270 at V. Description of the Invention (^) and anisotropic etching are used to selectively etch the second window to the gate electrode in the polycrystalline silicon layer and the first insulating layer, and in the second device region on the substrate Part of the first insulating layer above the N + and P + contact areas is partially etched. A portion of the Si02 first insulating layer remaining in the second window above the N + and P + contacts is selectively etched to The first 31 is 4 points. The first Si3N4 layer in the second window is subsequently etched selectively to expose N + and P + on the substrate. A titanium / titanium nitride first A barrier layer is deposited on the N + type polycrystalline silicon layer and the second contact window, and is in electrical contact with the N + and P + type contacts in the second device region. A first tungsten metal layer is deposited on the first barrier Layer, and it is thick enough to fill the first and second windows. Tungsten is also deposited to a thickness sufficient to provide a flat surface. A second Si3N4 layer is deposited, and The second Si3N4 layer, the first tungsten metal layer, the first barrier layer, and the polycrystalline sand layer are defined to form local interconnects. At the same time, during the definition period, an N + -doped polycrystalline silicon contact plug system is formed at In the first device region, a tungsten metal contact plug system is formed to connect to the N + and P + contact regions in the second device region. A third Si3N4 layer system is deposited and etched back to form a gap wall in the region. On the connection line, a second CVD Si02 insulating layer is deposited and planarized by the CMP method. A plurality of contact holes (via holes) are etched in the second insulating layer to a polycrystalline silicon contact plug, to a tungsten metal contact plug, and to 9 jade. Paper size is suitable for β 囡 囡 house standard net (ΓΝ5) Λ4 specifications (: 丨 OX 297 male replacement) —'J. T -1 IL--I II-II —, 11 ^-I (Please read the back Note: Please fill in this page again.) Order A7 B7 printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (y) Interconnect. Etching to gate electrode conditions that are common in the conventional technology. Furthermore, the automatic Quasi-contact plugs will reduce the aspect ratio of vias and make it easier to etch sub-micron-wide vias. This is accomplished by depositing a titanium / titanium nitride second barrier layer and a second tungsten metal layer The first layer of metal to the method is blanket-etched back the tungsten metal layer and the second barrier layer to form metal plugs in the vias of the interposer to form polycrystalline silicon contact plugs and tungsten contact plugs. Deposited The conductive metal multilayer structure composed of titanium-titanium nitride / copper aluminide / titanium nitride (Ti-TiN / AlCu / TiN) is scribed to complete the metal-connected integrated circuit to the first layer. Brief description of the drawings: Figure 1 is a schematic cross-sectional view illustrating a multilayer interconnect structure made by a conventional technique, and shows a reliability problem: contact corrosion of N · contact on a substrate And the etching of FET gate electrode. Figures 2 to 12 are cross-sectional schematic diagrams showing the sequence of process steps used to make an improved multilayer interconnection by using self-aligned polycrystalline silicon and metal contact plugs, which can avoid the occurrence of conventional technology Reliability issues. Symbol Description:
本纸張又度適用中國國家標準（CNS)A4規格（210 X 297公iT Γ — — — ! — — I I — I I I — II ^ 1!111111 {靖先閲讀背面之注意事項再填寫本頁}This paper is again applicable to China National Standard (CNS) A4 specifications (210 X 297 male iT Γ — — —! — — I I — I I I — II ^ 1! 111111 {Jingxian read the precautions on the back before filling in this page}
"-"可屮'φ:^"·^，ϋ〔-χ;ίί贽合：ΐτί(印 V A7 ___B7 五、發明説明（y) 1第一種形式 2第二種形式 4第一接觸窗口 6第二窗口 8接觸孔 10基板 12場氧化物（FOX) 14閘極氧化物 16蘭極電極 16A N +型摻雜多晶矽層 16B耐高溫金屬矽化物 17微量摻雜源極/汲極區 1厂微量摻雜植入 1 8覆蓋氧化物 19 N +及P +型接觸 20第一氮化砂（Si3N4)層 20’間隙壁 22第一絕緣層 23導線 24導線 26 Ν'型摻雜多晶矽層 28第二光阻罩幕 30第一阻障層 32第一鎢金屬層 32A內連線 32Β金屬插塞 32C多晶较接觸插塞 34第二氮化矽（Si3N4)層 36光阻罩幕 38間隙壁 40第二絕緣層 42金屬插塞 44導電金屬多層結構 44A鈦/氮化鈦層 44B錦銅合金層 44C氮化鈦層 --^-------^------ΪΤ------.^ (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適州中國S家標牟（（'NS ) Λ4規格（210..:097公淹） 五、發明説明（d ~~~ 發明之詳細說明： 首先，請參考第2圖至第12圖，一種用於 製造多層內連用之多晶矽及金屬接觸插塞於 積體電路上的詳細實施例說明。該方法同時形 成多晶砂接觸插塞及金屬接觸插塞，且亦形成 局部內連線路。該N+型多晶矽插塞與具有低漏 電流之基板上的N·型摻雜區間將形成良好的 歐姆式（ohmic)接觸，而該金屬插塞與基板上其 他位置的N +及P+型接觸間將形成具有低接觸 電阻的接觸。諸接觸插塞亦可避免基板的過度 蝕刻並減少蝕刻接觸窗口的縱橫比。雖然本方 法通常係說明用以製作多層內連用的改良式 接觸插塞，但亦應爲熟習本技藝之人士所完全 瞭解：本方法對於在DRAM電路上製作堆疊電 容器用的多晶矽接觸插塞係特別地有用，而該 金屬接觸插塞將可提供低Rc接觸於DRAM晶 片的周邊區域中。該N+型多晶矽插塞係形成於 記憶體單元區域中的N_型源極/汲極接觸區， 以減少漏電流；而連接至DRAM晶片之周邊區 域中之N通道及P通道FET ( CMOS)用之周 邊區域中的P +及N +型接觸的金屬接觸插塞將 減少接觸電阻（Rc)並改良電路性能。 參考第2圖，該方法係以提供一半導體基 板1 〇開始，其部份係表示於第2圖中。該基 (讀先閱讀背面之注意事項再填寫本買) 裝- 丁 ，-° 線 本紙張尺度適川+國囤家標苹（（'NS ) Λ4規格（210x297公犛） A7 B7"-" 可 屮 'φ: ^ " · ^ ， ϋ 〔-χ; ί 贽 贽 ： ΐτί (印 V A7 ___B7 V. Description of the invention (y) 1 the first form 2 the second form 4 the 4th A contact window 6 Second window 8 Contact hole 10 Substrate 12 Field oxide (FOX) 14 Gate oxide 16 Blue electrode 16A N + type doped polycrystalline silicon layer 16B High temperature resistant metal silicide 17 Trace doped source / drain Polar region 1 plant micro-doped implant 1 8 covered with oxide 19 N + and P + type contacts 20 first sand nitride (Si3N4) layer 20 'spacer 22 first insulation layer 23 lead 24 lead 26 26 N' type doped Heteropolycrystalline silicon layer 28 Second photoresist mask 30 First barrier layer 32 First tungsten metal layer 32A Interconnect 32B metal plug 32C Polycrystalline than contact plug 34 Second silicon nitride (Si3N4) layer 36 Photoresist Screen 38, gap wall 40, second insulation layer 42, metal plug 44, conductive metal multilayer structure 44A titanium / titanium nitride layer 44B bromide copper alloy layer 44C titanium nitride layer-^ ------- ^ --- --- ΪΤ ------. ^ (Please read the notes on the back before filling out this page) The paper size is Suzhou China S Jiamu Mou (('NS) Λ4 Specification (210 ..: 097)) ) 5. Description of the invention (D ~~~ Detailed description of the invention: First, please refer to Fig. 2 to Fig. 12 for a detailed embodiment of a polycrystalline silicon and metal contact plug used for manufacturing multilayer interconnects on a integrated circuit. The method is also Polycrystalline sand contact plugs and metal contact plugs are formed, and local interconnect lines are also formed. The N + type polycrystalline silicon plug and the N · type doping interval on the substrate with low leakage current will form a good ohmic ( ohmic) contact, and the metal plug will form a contact with a low contact resistance between the N + and P + contacts elsewhere on the substrate. The contact plugs can also avoid excessive etching of the substrate and reduce the aspect ratio of the etched contact window Although this method usually describes the improved contact plugs used to make multilayer interconnects, it should also be fully understood by those skilled in the art: this method is used to make polycrystalline silicon contact plug systems for stacked capacitors on DRAM circuits. Especially useful, and the metal contact plug will provide low Rc contact in the peripheral area of the DRAM chip. The N + type polycrystalline silicon plug is formed in the N in the memory cell area _-Type source / drain contact areas to reduce leakage current; and metal contacts for P + and N + -type contacts in peripheral areas for N-channel and P-channel FET (CMOS) peripheral areas of DRAM chips The plug will reduce the contact resistance (Rc) and improve the circuit performance. Referring to FIG. 2, the method starts with providing a semiconductor substrate 100, a portion of which is shown in FIG. The base (read the precautions on the back before filling in this purchase) Packing-Ding,-° Line This paper size is suitable for Sichuan + National Standard House (('NS) Λ4 size (210x297 cm) A7 B7
417C7U 五、發明説明（//) 板係典型地爲具有<100>結晶取向的單晶矽， 並包含有製作P通道及N通道FET用的N井 及P井。對於本發明而言，基板10具有一第 一種形式1的裝置區以及一第二種形式2的裝 置區；其中在第一種形式1的裝置區中連接至 基板上之N·型接觸的N型摻雜多晶矽接觸，而 在第二種形式2的裝置區中連接至基板上之 N +及P +型接觸的金屬接觸。該第一及第二種裝 置形式可交互散佈於基板上的各晶片中。例 如，對於DRAM電路而言，該第一種形式1的 裝置可爲位於晶片上之具有N·型接觸的記憶 體單元區，而第二種形式2的裝置可爲位於晶 片上之具有P +及N+型接觸的周邊電路。該裝 置區域係爲一相當厚的場氧化物（FOX) 12所 環繞，且各裝置區域係藉此而產生相互之電性 隔離。對於高密度電路而言，一種爲工業界所 實際使用之形成場氧化物區域的傳統方法係 爲淺溝渠隔離（STI)。這些STI區域的形成 通常係藉由蝕刻溝渠於矽基板10中，並塡充 以諸如Si02 12等絕緣材料於溝渠中，而該絕 緣材料係被蝕刻或硏磨而與基板表面同樣平 坦。其次，該FET係藉由成長一薄的閘極氧化 物14而形成，例如以將該裝置區熱氧化的方 式爲之。該閘極氧化物14係被成長至大約40 _____ _ 13 4、紙則，彳(rNS )罐格(2丨0/；!97公漦) ---- ----------¾------1T------^ (請先閲請背面之注意事項再填寫本頁} .:η·:ΐι-ν-局OC T;消许合竹权印公 "*;".部—'"^^-"T,消贽合竹科印 ^ A7 B7 五、發明説明（/>) 到80A間的厚度。一N+型摻雜多晶矽層16A 及一 _高溫金屬矽化物層1 6B係被沈積以形成 一閘極電極16。N +型摻雜多晶矽層16A係典 型地以使用矽烷（SiH4)做爲反應氣體的LPCVD 法而被沈積，並以諸如As或P摻雜至大約1.〇 E 20到1.0 E 22 atom/cm3間的濃度。N+型摻雜 多晶矽層16A係沈積至大約500到1500A間的 厚度。該耐高溫金屬矽化物層16B最好爲使用 諸如六氟化鎢（WF6)及矽烷做爲反應氣體的 CVD法所沈積的矽化鎢（WSi2)，且該矽化物最 好被沈積至大約500到1500A間的厚度。一覆 蓋氧化層18係藉由沈積一氧化矽層於閘極電 極16上而形成，接著沈積一氮化矽層於其上。 其次，層1 8、1 6A及1 6B係被刻劃以形成具有 該覆蓋氧化物1 8的閘極電極16。微量摻雜源 極/汲極（LDD)區17 ( N·)係於鄰接第一種 形式裝置區中的閘極電極16處被植入：而N+ 及P +型植入係皆被使用於第二種形式2裝置 中，其係使用植入阻止罩幕（block-out mask)， 以避免不欲植入的區域被植入。爲簡化該圖式 及說明，僅一在第二種形式2裝置中的微量摻 雜植入17’被說明於第2圖中，且其可爲N+型 或P+型植入。 再次參考第2圖，第一氮化矽（Si3N4)層20 --„------1¾.------IT------.^ (請先閱讀背面之注意事項再填寫本頁} 氺紙弦尺度適州中國K家標夺（r：\S ) Λ4规格（210 X;公釐） Α7 Β7 五、發明説明（/>) 係沈積於基板上的閘極電極1 6上方。該Si3N4 最好以使用諸如二氯矽烷（SiCl2H2)及氨氣 (NH3)等反應氣體的LPCVD法沈積之，並被沈 積至大約200到600A間的厚度。 參考第3圖，該第一 Si3N4層20係部份地 回蝕以形成間隙壁20'於閘極電極1 6上，同時 留下一部份20於裝置區域上，以提供一蝕刻 終止層而保護基板不會於後續加工步驟中被 蝕刻。該Si3N4最好使用活性離子蝕刻機 (RIE)及諸如三氟甲烷/四氟化碳/氬氣/氧氣 (CHF3/CF4/Ar/02)等蝕刻氣體回蝕。回蝕該 Si3N4層20以留下介於100至300A的厚度於 裝置區的基板10表面上。接著，N+及P+型接 觸區係形成於第二種形式2的裝置區中，其係 使用光阻式離子植入阻絕罩幕並植入N+型之 砷（As)或磷（P)離子及植入P+型的硼（B)離子。 爲簡化該圖式及說明，僅一在第二種形式2裝 置區中的大量摻雜植入區19 (N +或P +型）說 明於第3圖中，且依該FET爲N通道或P通道 FET而定，其可爲N+型或P +型植入。植入後 的較佳濃度係爲N +型植入介於1.0 E 19至1.0 E 21 atoms/cm3，而P+型植入介於i_〇 e 19至 1.0 E 21 atoms/cm3。 再次參考桌3圖，最好爲氧化砂（si〇2) 15 木紙张尺度適州中國阄家標卑〔(5 Τλ4規格（210X297公廢)"—~ --- --1------—It------IT--------.¾ (讀先閱請背面之注意事項再填寫本f) A7 B7 "·部中·^灼，·Η-Τ···,;;,·1ν"Μ ·τ-·η,ν 五、發明説明（i 士） 所組成的一第一絕緣層22係使用如四乙基正 矽酸鹽（TEOS )做爲反應氣體的低壓化學氣相 沈積法（LPCVD)沈積。其次，第一絕緣層22 係使用如化學機械硏磨法（CMP)平坦化其回 蝕厚度介於1000到3000A間的厚度於該FET 閛極電極1 6上方。 參考第4圖，一第一光阻罩幕24及非等向 性電漿蝕刻係使用以選擇性地蝕刻在第一種 形式1的裝置區中的自行對齊第一接觸窗口 4’其係延伸超過閘極電極16。該第一接觸窗 口 4係使用對於Si3N4有高度蝕刻選擇性的蝕 刻物質，而於該Si02第一絕緣層22中蝕刻至 該第一 Si3N4層20處。該蝕刻最好使用RIE及 一諸如C4F4 ' C5F8、CO、〇2與Ar的蝕刻氣體 混合物而執行’以提供一至少大於1 〇 ·· 1的蝕 刻速率選擇性。其次’移除在第一接觸窗口 4 中的第一Sl3N4層20係曝露出在基板1〇上方 的N·型接觸17(N>該第一 Si3N4層20係在與 以蝕刻窗口 4於Si〇2層22中之相同的RIE反 應室內即時地被移除，其係使用對於基板i 〇 有蝕刻選擇性的諸如CHF3、CH3F、02與Ar 等蝕刻氣體混合物蝕刻該S ι3Ν4。 參考第5圖’移除該第—光阻罩幕後，一 N +型摻雜多晶矽層26係被沈積於基板1 〇上， ___ 16 (請先閱讀背面之注意事項再填寫本頁) --1¾ Γ r 本紙浪凑標令.（rNS ) Λ4規格（ 4 ^*7 A7 B7 五、發明説明（<) 而與N-型源極/汲極接觸區17(1ST)接觸。N-型 摻雜多晶矽層26最好使用以SiH4做爲反應氣 體的LPCVD法沈積之，且沈積厚度介於300 到1000A間的厚度。N-型摻雜多晶矽層26係 在沈積期間可即時地摻雜添加如三氫化磷 (PH3)等摻質氣體，其摻雜濃度介於1.0 E 19 到 1.0 E 21 atoms/cm3。 參考第6圖，一第二光阻罩幕28及非等向 性蝕刻係用以在第二種形式裝置區2中選擇性 地蝕刻第二窗口 6。蝕刻第二窗口 6係於N+型 摻雜多晶矽層26中及第一絕緣層22中至閘極 電極16，並部份地蝕刻至位於N+及P+型接觸 區上方的第一絕緣層22中。如第6圖所示， 蝕刻至N型通道或P型通道FET基板上方之第 二裝置區中接觸區19 (N+或P+)。窗口 6最 好使用RIE及蝕刻氣體蝕刻之，其係以諸如 SF6' CF4、CHF3、CH3F、02 與 Ar 等飽刻氣體 蝕刻穿過該Ν+型摻雜多晶矽層26，並以對於 閘極電極1 6上的多晶矽化物層16Β具有蝕刻 選擇性的諸如C4F8、CHF3、CH3F、02與Ar等 蝕刻氣體蝕刻Si02。 如第7圖所示’位於N+及P +型接觸上方之 第二窗口 6中所殘餘的部份5102第一絕緣層 2 2遠擇性地触刻至該第—S i 3 N 4層2 0。該倉虫 木纸张乂度4 ϋϋι：標年（（、NS) Λ4規格（2mx 297公摩 - --：------ (¾------iT------^ (讀先閱讀背面之注意事項再填寫本頁) A7 B7 中 φ th ；ίί 什 印 五、發明説明（ 刻最好使用RIE及一蝕刻氣體執行，其係以如 C4F8、C5F8、C0、02 與 Ar 等對於 Si3N4 層 20 有蝕刻選擇性的鈾刻氣體來蝕刻3102層22。 其次，於第二窗口 6中曝露的第一Si3N4層20 係選擇性地蝕刻至N通道或P通道FET的N + 及p +型接觸，如元件1 9所示（N +或P+型）。 參考第8圖，移除光阻28後，沈積由鈦/ 氮化鈦（Ti/TiN)層所組成的一第一阻障層30 於N +多晶矽層26上及第二接觸窗口 6中，而 與第二種形式2的裝置區域中的N+及P+型接 觸1 9做電性接觸。第一阻障層30係以如物理 氣相沈積法（PVD )沈積之。鈦係首先被沈積 介於50到300A間的厚度，而氮化鈦則於後續 被沈積至介於5〇到300A間的厚度。沈積一第 一鎢（W )金屬層32於該第一阻障層30上方， 其厚度足夠厚以塡充該第一及第二窗口 4及 6，而提供一平坦表面。第一鎢金屬層32係以 使用WF6做爲反應氣體的CVD法沈積之。再 者，如第8圖所示，一第二Si3N4層34係被沈 積於第一鎢金屬層32上方。第二Si3N4層34 係以LPCVD法或電漿輔助CVD法沈積，沈積 介於1500到3000A的厚度。其次，一經定義 的光阻罩幕36係被使用爲蝕刻罩幕，以定義 第二Si3N4層34'第一鎢金屬層32、第一·阻障 --=------—装------IT-------- (請先閲讀背面之注意事項再填寫本頁) 本紙烺尺度適川中國囤家標苹（CNS ) Λ4规格（2IOX；!97公漦） Α7 Β7 五、發明説明（/7 ) 層3〇及Ν+型多晶矽層26，如第9圖所示。 再參閱9圖所示，非等向性電漿蝕刻係被 用以蝕刻第二Si3N4層34、第一鎢金屬層32、 第一阻障層30與N+型第一多晶矽層26所組成 的多層結構，以形成局部內連線32A。在定義 期間的同時，金屬係殘留於窗口 6中，以在第 二種形式2的裝置區域中形成金屬插塞32B ; 而N +型摻雜多晶矽26及部份的第一鎢金屬層 32係殘留於第一種形式1的裝置區中的窗口 4 內，以在基板上形成與N·型接觸17(Ν·)接觸的 Ν +型多晶矽接觸插塞32〇與Ν·型基板接觸17 連接的多晶矽插塞將提供低漏電流，諸如 DRAM晶片上的記憶體單元所需者；而連接至 基板上之N+及P+型接觸的金屬接觸窗將提供 低接觸電阻（Rc)，如CMOS電路用的DRAM晶 片周邊區域所需者。 該非等向性蝕刻最好使用RIE及一系列的 蝕刻氣體執行，其係以諸如CF4、CHF3、02與 Ar等蝕刻氣體蝕刻Si3N4層34,並以諸如Cl2、 SF6、02與Ar等蝕刻氣體蝕刻第一鎢金屬層 32、第一阻障層30及N +型多晶矽層26。417C7U 5. Description of the Invention (//) The board system is typically a single crystal silicon with a crystal orientation of < 100 >, and includes N-wells and P-wells for making P-channel and N-channel FETs. For the present invention, the substrate 10 has a device region of the first form 1 and a device region of the second form 2; wherein the device region of the first form 1 is connected to the N · type contact on the substrate. N-type doped polycrystalline silicon contacts, and metal contacts connected to N + and P + type contacts on the substrate in the device region of the second form 2. The first and second device forms can be interspersed among the wafers on the substrate. For example, for a DRAM circuit, the device of the first form 1 may be a memory cell region with N-type contacts on a chip, and the device of the second form 2 may be a P + device on a chip. And N + contacts. The device region is surrounded by a relatively thick field oxide (FOX) 12, and the device regions are thereby electrically isolated from each other. For high-density circuits, a traditional method of forming field oxide regions that is actually used in industry is shallow trench isolation (STI). These STI regions are usually formed by etching trenches in the silicon substrate 10 and filling the trenches with an insulating material such as Si02 12, and the insulating material is etched or honed to be as flat as the surface of the substrate. Second, the FET is formed by growing a thin gate oxide 14, such as by thermally oxidizing the device region. The gate oxide 14 is grown to about 40 _____ _ 13 4. Paper rule, 彳 (rNS) tank (2 丨 0 /;! 97 Gong) ---- --------- -¾ ------ 1T ------ ^ (Please read the notes on the back before filling out this page}.: Η ·: ΐι-ν- 局 OC T; *; ". 部 — '" ^^-" T, eliminate the combination of bamboo family seal ^ A7 B7 V. The thickness of the invention (/ >) to 80A. An N + doped polycrystalline silicon layer 16A and A high temperature metal silicide layer 16B is deposited to form a gate electrode 16. The N + type doped polycrystalline silicon layer 16A is typically deposited by LPCVD method using silane (SiH4) as a reactive gas, and Such as As or P doped to a concentration between about 1.0E 20 to 1.0 E 22 atom / cm3. The N + type doped polycrystalline silicon layer 16A is deposited to a thickness of about 500 to 1500A. The high temperature resistant metal silicide layer 16B It is preferable to deposit tungsten silicide (WSi2) using a CVD method such as tungsten hexafluoride (WF6) and silane as a reactive gas, and the silicide is preferably deposited to a thickness of about 500 to 1500 A. A cover oxidation The layer 18 is formed by depositing a silicon oxide layer on the gate electrode 16 Then, a silicon nitride layer is deposited thereon. Next, the layers 18, 16A, and 16B are scribed to form the gate electrode 16 having the cover oxide 18. The micro-doped source / drain The pole (LDD) region 17 (N ·) is implanted at the gate electrode 16 adjacent to the first form device area: and the N + and P + type implant systems are used in the second form 2 device It uses a block-out mask to prevent undesired areas from being implanted. To simplify the diagram and description, only a small amount of doping in the second form 2 device The implantation 17 'is illustrated in Fig. 2, and it can be an N + or P + implant. Referring again to Fig. 2, the first silicon nitride (Si3N4) layer 20 ----------- 1¾ .------ IT ------. ^ (Please read the precautions on the back before filling out this page} 弦 Paper string scale Shizhou China K House Standard (r: \ S) Λ4 specification (210 X; mm) Α7 Β7 V. Description of the invention (/ >) is deposited on the substrate above the gate electrode 16. The Si3N4 is best to use reactions such as dichlorosilane (SiCl2H2) and ammonia (NH3). Deposited by gas LPCVD and deposited to large 200 to 600 A. Referring to FIG. 3, the first Si3N4 layer 20 is partially etched back to form a spacer 20 'on the gate electrode 16 while leaving a portion 20 on the device area. To provide an etch stop layer to protect the substrate from being etched in subsequent processing steps. The Si3N4 is preferably etched back using an active ion etcher (RIE) and an etching gas such as trifluoromethane / carbon tetrafluoride / argon / oxygen (CHF3 / CF4 / Ar / 02). The Si3N4 layer 20 is etched back to leave a thickness between 100 and 300 A on the surface of the substrate 10 in the device region. Next, the N + and P + -type contact regions are formed in the device region of the second form 2, which uses a photoresistive ion implantation blocking mask and implants N + type arsenic (As) or phosphorus (P) ions and Implantation of P + type boron (B) ions. In order to simplify the diagram and description, only a large number of doped implanted regions 19 (N + or P + type) in the second form 2 device region are illustrated in FIG. 3, and the FET is an N-channel or Depending on the P-channel FET, it can be N + or P + implanted. The preferred concentration after implantation is that the N + type implant is between 1.0 E 19 and 1.0 E 21 atoms / cm3, while the P + type implant is between i_o e 19 and 1.0 E 21 atoms / cm3. Refer to the table 3 again, it is best to use oxidized sand (si〇2) 15 wood paper standard Shizhou China Jiajia standard [[5 Τλ4 specification (210X297 public waste) " — ~ --- --1-- ----— It ------ IT --------. ¾ (Read the first note, please fill in the notes on the back, then fill in this f) A7 B7 " · Ministry · ^ 灼, · Η -Τ ··, ;;, · 1ν " M · τ- · η, ν 5. Description of the Invention (i) A first insulating layer 22 composed of, for example, tetraethyl orthosilicate (TEOS) Low pressure chemical vapor deposition (LPCVD) deposition as a reactive gas. Secondly, the first insulating layer 22 is planarized using a chemical mechanical honing method (CMP), and the thickness of the etchback thickness is between 1000 and 3000 A. Above the FET cathode electrode 16. With reference to FIG. 4, a first photoresist mask 24 and anisotropic plasma etching are used to selectively etch the self-aligned capacitors in the device area of the first form 1. A contact window 4 'extends beyond the gate electrode 16. The first contact window 4 uses an etching substance having a high etching selectivity to Si3N4, and is etched to the first Si3N4 layer in the Si02 first insulating layer 22 20. The most etched It is performed using RIE and an etching gas mixture such as C4F4 'C5F8, CO, 〇2 and Ar' to provide an etch rate selectivity of at least greater than 1 〇 ·· 1. Secondly, 'removed in the first contact window 4 The first Sl3N4 layer 20 is an N · type contact 17 (N >) exposed above the substrate 10, and the first Si3N4 layer 20 is immediately in the same RIE reaction chamber as the etching window 4 in the Si02 layer 22 The ground is removed, which is used to etch the S3N4 using an etching gas mixture such as CHF3, CH3F, 02, and Ar that is selective to the substrate i. Refer to FIG. 5 'removing the first photoresist mask behind, The N + -doped polycrystalline silicon layer 26 is deposited on the substrate 10, ___ 16 (Please read the precautions on the back before filling out this page) --1¾ Γ r This paper waves the order. (RNS) Λ4 specifications (4 ^ * 7 A7 B7 V. Description of the invention (<) In contact with the N-type source / drain contact region 17 (1ST). The N-type doped polycrystalline silicon layer 26 preferably uses LPCVD with SiH4 as a reactive gas And deposited with a thickness between 300 and 1000 A. The N-type doped polycrystalline silicon layer 26 may be deposited during deposition. Dopant gas such as phosphorus trihydrogen (PH3) is added from time to time, and its doping concentration is between 1.0 E 19 to 1.0 E 21 atoms / cm3. Referring to Fig. 6, a second photoresist mask 28 and non-equivalent Anisotropic etching is used to selectively etch the second window 6 in the device region 2 of the second form. The second window 6 is etched in the N + type doped polycrystalline silicon layer 26 and in the first insulating layer 22 to the gate electrode 16, and is partially etched into the first insulating layer 22 above the N + and P + type contact regions. As shown in FIG. 6, the contact region 19 (N + or P +) in the second device region over the N-channel or P-channel FET substrate is etched. The window 6 is preferably etched with RIE and an etching gas. It is etched through the N + -type doped polycrystalline silicon layer 26 with a saturated gas such as SF6 'CF4, CHF3, CH3F, 02, and Ar, and is used for the gate electrode. The polysilicide layer 16B on 16 has an etching selectivity such as C4F8, CHF3, CH3F, 02, and Ar, etc. to etch Si02. As shown in FIG. 7 'the remaining portion 5102 of the second window 6 above the N + and P + type contacts 5102 the first insulating layer 2 2 is selectively etched to the -S i 3 N 4 layer 2 0. The paper size of this wormworm wood is 4 ϋϋι: the standard year ((, NS) Λ4 specification (2mx 297 MM----------- (¾ ------ iT ------ ^ (Read the precautions on the back before you fill in this page) A7 B7 φ th; 印 5. Description of the invention (It is best to use RIE and an etching gas to perform the engraving. It is based on C4F8, C5F8, C0, 02, and Ar etc. have an etching-selective uranium etching gas for the Si3N4 layer 20 to etch the 3102 layer 22. Next, the first Si3N4 layer 20 exposed in the second window 6 is selectively etched to the N + of the N-channel or P-channel FET. And p + contact, as shown in element 19 (N + or P + type). Referring to Figure 8, after removing the photoresist 28, a first layer consisting of a titanium / titanium nitride (Ti / TiN) layer is deposited. A barrier layer 30 is on the N + polycrystalline silicon layer 26 and in the second contact window 6, and makes electrical contact with the N + and P + type contacts 19 in the device region of the second form 2. The first barrier layer 30 It is deposited by, for example, physical vapor deposition (PVD). Titanium is first deposited to a thickness between 50 and 300 A, and titanium nitride is subsequently deposited to a thickness between 50 and 300 A. Deposition 1 First tungsten (W ) The metal layer 32 is above the first barrier layer 30, and its thickness is thick enough to fill the first and second windows 4 and 6 to provide a flat surface. The first tungsten metal layer 32 is made of WF6. The reactive gas is deposited by the CVD method. Furthermore, as shown in FIG. 8, a second Si3N4 layer 34 is deposited over the first tungsten metal layer 32. The second Si3N4 layer 34 is LPCVD or plasma-assisted CVD Method to deposit a thickness between 1500 and 3000 A. Secondly, a defined photoresist mask 36 is used as an etching mask to define a second Si3N4 layer 34 ', a first tungsten metal layer 32, and a first barrier. -= -------- install ------ IT -------- (Please read the precautions on the back before filling this page) CNS) Λ4 specification (2IOX;! 97 male) A7 B7 V. Description of the invention (/ 7) Layer 30 and N + type polycrystalline silicon layer 26, as shown in Fig. 9. Refer to Fig. 9 again, anisotropic The plasma etching system is used to etch a multilayer structure composed of the second Si3N4 layer 34, the first tungsten metal layer 32, the first barrier layer 30, and the N + type first polycrystalline silicon layer 26 to form local interconnects. 32A. Under decision At the same time, the metal system remains in the window 6 to form a metal plug 32B in the device region of the second form 2. The N + type doped polycrystalline silicon 26 and a portion of the first tungsten metal layer 32 remain. In the window 4 in the device area of the first form 1, an N + -type polycrystalline silicon contact plug 32 which is in contact with the N-type contact 17 (N ·) is formed on the substrate and is connected to the N-type substrate contact 17. Polycrystalline silicon plugs will provide low leakage currents, such as those required for memory cells on DRAM chips; and metal contact windows connected to N + and P + contacts on the substrate will provide low contact resistance (Rc), as used in CMOS circuits Required for peripheral areas of DRAM chips. This anisotropic etching is preferably performed using RIE and a series of etching gases, which etch the Si3N4 layer 34 with an etching gas such as CF4, CHF3, 02, and Ar, and etch with an etching gas such as Cl2, SF6, 02, and Ar. The first tungsten metal layer 32, the first barrier layer 30, and the N + type polycrystalline silicon layer 26.
再次參考第9圖，沈積並非等向性地回蝕 一第三Si3N4層，以形成間隙壁38於內連線 32A上。沈積該第三Si3N4層介於300到800A ,---------1裝--1----訂------線 (請先閱讀背面之注意事項再填寫本頁) 本紙张尺度過川中國阀家標率（（'NS ) Λ4規格（210X:97公f ) 417270 A7 B7 :t-::r,部屮士i?^"p-x;/i赀含竹扣印 y 五、發明説明（G) 間的厚度。 參考第1 〇圖，沈積並平坦化一第二絕緣層 40。該第二絕緣層40最好由CVD Si02或諸如 硼磷矽酸鹽玻璃（BPSG)等摻雜Si02所組成。 第二絕緣層最好以化學機械硏磨法（CMP) 平坦化至具有位於相連導線32A上方之介於 8000到12000A間的較佳厚度。 參考第11圖，蝕刻多層接觸孔（介層孔） 8係於第二絕緣層4〇中至多晶矽接觸插塞 32C、至鎢金屬接觸插塞32B以及至相連導線 32A。光學微影技術及非等向性電漿蝕刻係被 用以蝕刻接觸孔8。例如，該蝕刻可使用諸如 C5F8、C4FS、CHF3、CO、02 與 Ar 等含氟的蝕 刻氣體混合物的RIE而執行。自動對準接觸插 塞32B及32C將可避免如第1圖描述之習知技 術所普遍發生的基板中之接觸的過度蝕刻以 及蝕刻到閘極電極16中的情形。再者，該自 動對準接觸插塞將減少介層孔8的縱橫比，因 而使其更容易用於蝕刻未來高密度電路技術 用之次微米寬之介層孔。 參考第1 2圖，用以製作具有局部相連的多 晶矽及金屬接觸插塞的方法係藉由沈積一諸 如Ti/TiN的第二阻障層及一第二鎢金屬層而 完成，其係被毯覆式地蝕刻，以在接觸孔8中 20 本紙乐尺度適;《中國K家標年(rNShW%格（2!0 / 297公釐) _--^------—裝------訂 -------"線 (請先閱讀背面之注意事項再填寫本頁) 五、發明説明（1) 形成連接至多晶矽接觸插塞32c、連接至鎢金 屬接觸插塞32B以及連接至相連導線32A的金 屬插塞42。該Ti/TiN第二阻障層係典型地爲 大約100至600A間的厚度。沈積並定義一鈦/ 氮化欽層44A、一'錦銅合金層44B及一氮化駄 層44C所組成的一導電金屬多層結構44 ，以 完成積體電路的第一層金屬相連。該鈦/氮化鈦 層44A係爲介於100至600A厚。該鋁銅合金 層44B係爲介於4500至10000A厚，而該氮化 鈦層44C係爲介於200至500A厚。其次，一 導電金屬多層結構44係以傳統式光學微影及 電漿蝕刻刻劃，以形成下一層電相連。 雖然本發明已被特別地揭示並參考其較佳 實施例而被說明，然而應爲熟習本技藝之人士 所瞭解的是各種形式與細節的改變將可於不 背離本發明之精神與範疇下爲之。雖然該多晶 矽及金屬接觸插塞結構係於積體電路中做說 明，但應瞭解地是，連接至基板上之N·型接觸 的N +型多晶矽插塞可被使用爲DRAM電容器 用的節點接觸以減少漏電流，而連接N+及P+ 型接觸的金屬接觸插塞則可被使用於CMOS裝 置用之DRAM晶片的周邊電路中以減少RC並 改善電路性能。 ——-----.--1¾------IT------^ (請先閱讀背面之注意事項再填寫本頁) 本紙张尺度適川中囤围家標埤（CNS ) Λ4規格（210X297公f )Referring again to FIG. 9, the deposition is not an isotropic etchback of a third Si3N4 layer to form a spacer 38 on the interconnect 32A. Deposit the third Si3N4 layer between 300 and 800A, --------- 1 pack--1 ---- order ------ line (Please read the precautions on the back before filling this page ) This paper scales through the Chinese valve standard of Sichuan (('NS) Λ4 specifications (210X: 97 male f) 417270 A7 B7: t-:: r, ministry i? ^ &Quot;px; / i 赀 含 竹Button y 5. Thickness between descriptions of invention (G). Referring to FIG. 10, a second insulating layer 40 is deposited and planarized. The second insulating layer 40 is preferably made of CVD Si02 or borophosphosilicate glass. (BPSG) and other doped SiO2. The second insulating layer is preferably planarized by chemical mechanical honing (CMP) to have a preferred thickness between 8000 and 12000A above the connecting wire 32A. Refer to FIG. 11 , Etching multilayer contact holes (interlayer holes) 8 in the second insulating layer 40 to polycrystalline silicon contact plugs 32C, to tungsten metal contact plugs 32B, and to connecting wires 32A. Optical lithography technology and anisotropic electricity Slurry etching is used to etch the contact hole 8. For example, the etching can be performed using RIE using a fluorine-containing etching gas mixture such as C5F8, C4FS, CHF3, CO, 02, and Ar. Automatic contact contact insertion The plugs 32B and 32C will avoid over-etching of contacts in the substrate and etching into the gate electrode 16 which are common in the conventional technology described in FIG. 1. Furthermore, the self-aligning contact plugs will be reduced. The aspect ratio of via hole 8 makes it easier to etch submicron-wide via holes for future high-density circuit technology. Refer to Figure 12 for the fabrication of polycrystalline silicon and metal contact plugs with local connections. The method is completed by depositing a second barrier layer such as Ti / TiN and a second tungsten metal layer, which is blanket-etched to fit 20 paper sheets in the contact hole 8; K House Standard Year (rNShW% grid (2! 0/297 mm) _-- ^ -------- install ------ order ------- " line (please read first Note on the back, please fill out this page again.) 5. Description of the invention (1) Form a metal plug 42 connected to the polycrystalline silicon contact plug 32c, a tungsten metal contact plug 32B, and a connecting wire 32A. The Ti / TiN section The two barrier layers are typically between about 100 and 600 A thick. A titanium / nitride layer 44A, a brocade copper alloy layer 44B, and A conductive metal multilayer structure 44 composed of a hafnium nitride layer 44C to complete the first metal connection of the integrated circuit. The titanium / titanium nitride layer 44A is between 100 and 600A thick. The aluminum-copper alloy layer The 44B series is between 4500 and 10000A thick, and the titanium nitride layer 44C is between 200 and 500A thick. Second, a conductive metal multilayer structure 44 is scribed with traditional optical lithography and plasma etching to form The next layer is electrically connected. Although the present invention has been particularly disclosed and described with reference to preferred embodiments thereof, it should be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention. Of it. Although the polycrystalline silicon and metal contact plug structure is explained in the integrated circuit, it should be understood that the N + type polycrystalline silicon plug connected to the N · type contact on the substrate can be used as a node contact for a DRAM capacitor. In order to reduce leakage current, metal contact plugs connecting N + and P + type contacts can be used in peripheral circuits of DRAM chips for CMOS devices to reduce RC and improve circuit performance. ——-----.-- 1¾ ------ IT ------ ^ (Please read the notes on the back before filling out this page) This paper size is suitable for Chuanwei House Standard 埤 (CNS) ) Λ4 specification (210X297 male f)