KR20080061038A - Method of forming a polysilicon contact in semiconductor device - Google Patents

Abstract

A method for forming a polysilicon contact of a semiconductor apparatus is provided to decrease the contact resistance between first and second contacts and between the first contact and a substrate by forming a titanium silicide on the bottom surface of a contact hole. A first insulating layer comprising a first contact hole on a substrate having a conductive region. A first titanium layer is formed on the first insulating layer, and the bottom surface and sidewall of the first contact hole. A first conductive layer which is made of doped polysilicon is deposited on the first titanium layer, and the first titanium layer is transformed into a first titanium silicide(124). A first contact(128) is formed in the first contact hole by removing the first conductive layer and the first titanium silicide. A second insulating layer(130) having a second contact hole(132) is formed on the first contact. A second titanium layer is formed on the second insulating layer, and the bottom surface and sidewall of the second contact hole. The second titanium layer is transformed into a second titanium silicide(136). A second contact is formed in the second contact hole by removing by removing the second conductive layer and the second titanium silicide.

Description

Method of forming a polysilicon contact in semiconductor device

1A to 1I are cross-sectional views illustrating a method of forming a polysilicon contact of a semiconductor device according to the present invention.

Explanation of symbols on the main parts of the drawings

100 semiconductor substrate 102 device isolation layer

110: gate structure 114: source / drain regions

114a: drain region 114b: source region

116: single crystal silicon layer 118: first insulating layer

120: first contact hole 122: the first titanium layer

124: first titanium silicide 126: first polysilicon pattern

128: first contact 128a: first pad

128b: second pad 130: second insulating layer

132: second contact hole 134: second titanium layer

136: second titanium silicide 138: second polysilicon pattern

140: second contact 142: bit line

144: third insulating layer 146: third contact hole

148: third titanium layer 150: third titanium silicide

152: third polysilicon pattern 154: third contact

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a polysilicon contact method of a semiconductor device having a low contact resistance between an active region of a semiconductor device and polysilicon contacts and polysilicon contacts.

As semiconductor devices have been highly integrated, device design rules such as transistor channel length, active spacing, wiring width, wiring spacing, and contact pad size have been scaled down. In order to reduce contact resistance in such a reduced contact pad, there is a continuing invention. In particular, due to the miniaturization of patterns due to high integration in memory devices such as DRAMs, mis-alignment may occur when forming contacts such as bit lines or storage nodes, which causes various problems.

A method of forming a contact of a conventional semiconductor device will be briefly described as follows. A transistor (shown as a gate electrode, a capacitor contact region (eg, a source region), and a bit line contact region (eg, a drain region) provided as a word line on a semiconductor substrate is illustrated. Not formed). Polysilicon contact pads are formed on the source and drain regions of the transistors to reduce the aspect ratio of the contact holes to be formed thereon.

Subsequently, after forming an insulating layer on the front surface of the transistors and the polysilicon contact pads, the insulating layer is etched by a photolithography process to form contact holes exposing the polysilicon contact pads connected to the drain region of the substrate. Subsequently, as a barrier metal layer, for example, a titanium layer and a titanium nitride layer are sequentially deposited on the sidewalls and bottom surfaces of the contact holes and the insulating layer by a chemical vapor deposition method.

Subsequently, a metal layer, for example a tungsten layer, is deposited on the titanium nitride layer by a chemical vapor deposition method. The tungsten layer, titanium nitride layer and titanium layer are then patterned by photolithography to form direct contact pads electrically connected to polysilicon contact pads connected to the drain region of the substrate. Bit lines connected to the direct contact pads are formed on the direct contact pads.

Subsequently, after forming an additional insulating layer on the insulating layer to cover the bit lines, the additional insulating layer is etched by a photolithography process to form contact plugs in contact with the polysilicon contact pads connected to the source region of the substrate. do. Subsequently, doped polysilicon is buried in the contact plugs to form buried contact pads that are subsequently connected to the storage node.

Thus, in order to reduce the contact resistance on the polysilicon contact pads, when forming the direct contact pads made of a metal in contact with the contact pads, titanium as a barrier metal layer between the contact surface of the polysilicon contact pads and tungsten contacts There is a difficulty in the node separation process for removing a part of the barrier metal layer to form a nitride layer and a titanium layer.

That is, the removal of the barrier metal layer for the node separation is difficult to perform by the etch back process, and thus, the chemical mechanical polishing (hereinafter, referred to as "CMP") process is performed. However, when the node is separated by performing the CMP process, it is difficult to align the photo key of the subsequent process because the photo key is not visible. Therefore, the photolithography process for exposing the key portion has to be added, which is a cost burden.

As described above, in the semiconductor device according to the related art, misalignment is generated in the process of forming a contact for connecting the source / drain region and the outside.

Further, in the semiconductor device, since the direct contact pads made of metal and the buried contact pads in contact with the storage node are directly connected to the polysilicon contact pads in contact with the source / drain regions, the contact resistance at the contacted portion is increased. There is an increasing problem.

An object of the present invention to solve the above problems is to provide a method for forming a contact of a semiconductor device that can facilitate the node separation process while reducing the contact resistance between the substrate and the polysilicon contact and polysilicon contacts.

In order to achieve the above object, according to the method for forming a polysilicon contact of a semiconductor device according to the present invention, a first insulating layer including a first contact hole exposing the conductive region is formed on a substrate having a conductive region. . A first titanium layer is formed on the sidewalls, the bottom surface of the first contact hole, and the first insulating layer. While filling the first contact hole, the first titanium layer is converted into the first titanium silicide while depositing a first conductive layer made of polysilicon doped on the first titanium layer. The first conductive layer and the first titanium silicide are removed until the first insulating layer is exposed to form a first contact in the first contact hole. A second insulating layer having a second contact hole exposing the first contact is formed on the first insulating layer and the first contact. A second titanium layer is formed on the sidewalls, the bottom surface, and the second insulating layer of the second contact hole. While filling the second contact hole, the second titanium layer is converted into second titanium silicide while depositing a second conductive layer made of polysilicon doped on the second titanium layer. The second conductive layer and the second titanium silicide are removed until the second insulating layer is exposed to form a second contact in the second contact hole.

As an example of the present invention, the first and second titanium layers are deposited by a chemical vapor deposition (CVD) process.

As an example of the present invention, a single crystal silicon layer may be further formed on the conductive region by a selective epitaxial growth method before the process of forming the first insulating layer on the substrate having the conductive region.

Here, the second contact may be a direct contact in contact with the bit line. In addition, the second contact may be a buried contact in contact with the storage node.

According to the present invention, by forming titanium silicide on the bottom surface of the contact hole when forming contacts made of doped polysilicon, contact resistance can be reduced at the interface between the substrate and the first contact and at the interface between the first and second contacts. have. In addition, by using titanium silicide, the problem of misalignment of polysilicon contacts is solved because node separation is easier than in the case of forming a tungsten layer in order to reduce contact resistance on a conventional polysilicon contact and separating the nodes by CMP. Can be blocked. In addition, when the node separation process is performed by CMP, alignment is difficult, and thus, an additional photolithography process is not required, thereby reducing the cost increase due to the addition of the process.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the following examples and may be implemented in other forms. The embodiments introduced herein are provided to make the disclosure more complete and to fully convey the spirit and features of the invention to those skilled in the art. In the drawings, the thickness of each device or layer and regions has been exaggerated for clarity of the invention and, if the layer is said to be located on another layer or substrate, directly formed on another layer or substrate Or an additional layer may be interposed therebetween.

1A to 1I are cross-sectional views for explaining a polysilicon contact forming method of a semiconductor device according to the present invention.

FIG. 1A illustrates forming a first insulating layer 118 including a first contact hole 120 exposing a conductive region on a substrate 100.

A plurality of active regions are defined by forming the device isolation layer 102 on the surface portion of the substrate 100. For example, a shallow trench isolation (STI) process is performed to form a device isolation layer 102 for electrically isolating active regions from each other on a surface portion of the substrate 100.

A gate insulating layer (not shown) of a gate structure subsequently formed on the device isolation layer 102 and the active regions is formed. The gate insulating layer may be formed of silicon oxide, and is formed by performing a thermal oxidation process. Subsequently, a conductive layer (not shown) that can function as a gate electrode is formed on the gate insulating layer. The conductive layer may include titanium or titanium nitride. Subsequently, a mask pattern 108 made of silicon nitride is formed on the conductive layer. The mask pattern 108 is formed by forming a silicon nitride layer and patterning the silicon nitride layer to be formed on the gate structure by a photolithography process.

Subsequently, an anisotropic etching process is performed using the mask pattern 108 as an etch mask to form a gate structure including the gate insulating layer pattern 104, the gate electrode pattern 106, and the mask pattern 108 on the substrate 100. Form 110. A gate spacer 112 is formed on sidewalls of the gate structure 110 to provide a word line. Subsequently, source / drain regions 114 are formed on the surface portions of the substrate 100 adjacent to the gate structure 110 as conductive regions to complete transistors. The source / drain regions 114 include a drain region 114a used as a bit line contact region and a source region 114b used as a capacitor contact region.

In some embodiments, a portion of the first contact hole 120 may be filled to reduce an aspect ratio of the first contact hole 120 to be subsequently formed on the source / drain regions 114 of the transistors. The single crystal silicon layer 116 may be formed. The single crystal silicon layer 116 is formed by a selective epitaxial growth method.

Subsequently, silicon oxide is deposited on the entire surface of the substrate 100 including the transistors to form a first insulating layer 118, and then the first insulating layer 118 is removed to the surface of the substrate 100. The first contact hole 120 is formed to expose the formed conductive region, that is, the single crystal silicon layer 116 connected to the source / drain regions 114 of the transistor. That is, the first contact hole 120 is formed between the gate structures 110 through a process of forming a self aligned contact using the gate structures 110 as an etch mask. In this case, the first contact hole 120 is formed through an anisotropic etching process.

1B illustrates forming a first titanium layer 122.

The first insulating layer 118 is planarized by CMP or etch back to expose the gate structure 110.

Subsequently, a natural oxide film formed on the surface of the substrate 100 exposed through the first contact hole 120 is removed through a pre-cleaning process, and then the reaction chamber is performed in a reaction chamber in which a CVD process is performed. Titanium tetrachloride (TiCl ₄ ) gas is supplied into the first contact hole 120 to form a first refractory metal layer, for example, a first titanium layer 122 on the sidewall, bottom surface, and the gate structure 110. The first titanium layer 122 serves as a layer to prevent diffusion of doped atoms of the doped polysilicon material that forms the first contact 128 (FIG. 1C) subsequently formed with the substrate 100.

Preferably, the first titanium layer 122 is formed to a thickness of about 50 to 100 kPa by the CVD method at a temperature of about 500 ~ 650 ℃.

FIG. 1C illustrates the conversion of the first titanium layer 122 to the first titanium silicide 124 and the formation of a first contact 128.

After the first titanium layer 122 is formed as described above, a first conductive layer (not shown) made of doped polysilicon is sufficiently filled with the first contact hole 120 by a CVD process. Form to thickness.

Preferably, the first conductive layer is formed while heating to a deposition temperature of about 550 ~ 600 ℃.

At this time, the titanium atoms in the first titanium layer 122 and the silicon atoms of the first conductive layer formed at the deposition temperature react to convert the first titanium layer 122 to the first titanium silicide 124. do. Therefore, the first titanium silicide 124 is uniformly formed on the bottom, sidewalls, and gate structure 110 of the first contact hole 120. The first titanium silicide 124 improves current conductivity by forming a ohmic contact by lowering a work function between the substrate 100 and the first conductive layer.

Subsequently, the first conductive layer and the first titanium silicide 124 are removed until the gate structure 110 is exposed, so that the first titanium silicide 124 and the first poly in the first contact hole 120 are removed. The first contact 128 made of the silicon pattern 126 is formed. The removal process may be performed by an etch back process, a CMP process, or a combination thereof. In this case, the first contact 128 includes a first pad 128a to which a bit line contact is connected and a second pad 128b to a storage node contact.

FIG. 1D illustrates a second insulating layer 130 including a second contact hole 132 exposing a portion of the first contact 128 on the first insulating layer 118 and the first contact 128. The step of forming is shown.

The first contact 128 where the portion is exposed is the first pad 128a to which the bit line contact is connected.

As described above, after the silicon oxide is deposited on the entire surfaces of the gate structures 100 and the first contact 128 to form the second insulating layer 130, the second insulating layer 130 is polished to have a flat upper surface. Subsequently, the second insulating layer 130 is removed to form the second contact hole 132 to expose the first pad 128a of the first contact 128 by a photolithography process. The second contact hole 132 is provided to form a bit line contact in contact with the first pad 128a of the first contact 128.

1E illustrates forming a second titanium layer 134.

As described above, the etching residue formed on the surface of the first pad 128a exposed through the second contact hole 132 is removed through a wet etching process, and then titanium tetrachloride is added to the reaction chamber in which the CVD process is performed. (TiCl ₄ ) gas is supplied to form a second refractory metal layer, for example, a second titanium layer 134, on the sidewalls, the bottom surface, and the second insulating layer 130 of the second contact hole 132. The second titanium layer 134 is provided as a layer for preventing diffusion of metal atoms forming a bit line (not shown) and a bit line contact (not shown).

Preferably, the second titanium layer 134 is formed to a thickness of about 50 to 100 kPa by the CVD method at a temperature of about 500 ~ 650 ℃.

FIG. 1F illustrates the conversion of the second titanium layer 134 to the second titanium silicide 136 and the formation of the second contact 140.

As described above, after the second titanium layer 134 is formed, the second contact hole 132 may be sufficiently filled with a second conductive layer (not shown) made of doped polysilicon by a chemical vapor deposition method. Deposit as thick as possible.

Preferably, the second conductive layer is formed by heating to a deposition temperature of about 550 ~ 600 ℃.

At this time, the titanium atoms in the second titanium layer 134 and the silicon atoms in the second conductive layer formed at the deposition temperature react to form the second titanium layer 134 as the second titanium silicide 136. Is converted. Therefore, the second titanium silicide 136 is uniformly formed on the bottom, sidewalls and the second insulating layer 130 of the second contact hole 132. The second titanium silicide 136 improves current conductivity by forming an ohmic contact by lowering a work function between the first polysilicon pattern 126 of the first pad 128a and the second conductive layer.

Subsequently, the second conductive layer and the second titanium silicide 136 are removed until the second insulating layer 130 is exposed to form a second contact 140. The second contact 140 includes a second titanium silicide 136 and a second polysilicon pattern 138 in the second contact hole 132. The removal process is performed by an etch back process, a CMP process, or a combination thereof.

The second contact 140 is a direct contact to which a bit line 142 (FIG. 1G) subsequently formed on the first pad 128a of the first contact 128 contacts. As such, by forming a second titanium silicide 136 between the first polysilicon pattern 126 and the second polysilicon pattern 138, the first contact 128 and the second contact 140 made of polysilicon are formed. The contact resistance at the interface of can be reduced.

A third contact (FIGS. 1H and 154) is formed on the second pad 128b of the first contact 128 as a buried contact to which a subsequent storage node (not shown) is formed. .

FIG. 1G illustrates forming a third insulating layer 144 including a bit line 142 and a third contact hole 146 exposing a second pad 128b of the first contacts 128. .

As described above, after the second contact 140 is formed, the second polysilicon pattern 138 of the second contact 140 on the second contact 140 and the second insulating layer 130. Form a metal layer (not shown) connected to the. The metal layer is provided to the bit lines 142 through a subsequent patterning process. For example, the metal layer may be formed of tungsten (W), aluminum (Al), or copper (Cu). The metal layer is preferably formed at a height sufficient to ensure a low resistance enough to be used as the bit lines 142.

A hard mask layer (not shown) is formed on the metal layer. For example, the hard mask layer may be formed of a nitride such as silicon nitride (SiN). The hard mask layer may be formed to a height sufficient to serve as a buffer for the anisotropic etching process for patterning the metal layer and forming a storage node contact hole (not shown) in a subsequent process.

Subsequently, the hard mask layer and the metal layer are sequentially etched by a photolithography process to form bit line structures (not shown) including hard mask patterns (not shown) and bit lines 142. The bit line structures have a line shape extending in a first direction.

Spacers (not shown) are formed on sidewalls of the bit lines 142 to prevent the storage node contacts (not shown) to be formed between the hard mask patterns from contacting the bit lines 142.

Subsequently, silicon oxide is deposited on the second insulating layer 130 and the second contact 140 to cover the bit line structures including the bit lines 142 to form a third insulating layer 144. Thereafter, the third insulating layer 144 is removed to form a third contact hole 146 to expose the second pad 128b of the first contact 128. The third contact hole 146 is formed by performing an anisotropic etching process.

1H illustrates forming a third titanium layer 148.

As described above, the etching residue formed on the surface of the second pad 128b exposed through the third contact hole 146 through the wet etching process is removed, and then titanium tetrachloride in the reaction chamber in which the CVD process is performed. (TiCl ₄ ) gas is supplied to form a third refractory metal layer, for example, a third titanium layer 148 on the sidewalls, the bottom surface of the third contact hole 146, and the third insulating layer 144.

Preferably, the third titanium layer 148 is formed to a thickness of about 50 to 100 kPa by the CVD method at a temperature of about 500 ~ 650 ℃.

FIG. 1I illustrates the conversion from the third titanium layer 148 to the third titanium silicide 150 and the formation of a third contact 154.

After the third titanium layer 148 is formed as described above, the third contact hole 146 can be sufficiently filled with a third conductive layer (not shown) made of doped polysilicon by a chemical vapor deposition method. To a thickness of.

Preferably, the third conductive layer is formed by heating to a deposition temperature of about 550 ~ 600 ℃.

At this time, the titanium atoms in the third titanium layer 148 and the silicon atoms in the third conductive layer formed at the deposition temperature react to form the third titanium silicide 150. Is converted. Therefore, the third titanium silicide 150 is uniformly formed on the bottom, sidewalls, and third insulating layer 144 of the third contact hole 146. The third titanium silicide 150 improves current conductivity by forming a ohmic contact by lowering a work function between the first polysilicon pattern 126 of the second pad 128b and the third conductive layer.

Next, the third conductive layer and the third titanium layer 148 are removed until the third insulating layer 144 is exposed to form a third contact 154. The second contact 154 includes a third titanium silicide 150 and a third polysilicon pattern 152 formed in the third contact hole 146. The removal process is performed by an etch back process, a CMP process, or a combination thereof. The third contact 154 is provided as a buried contact bonded to the second pad 128b of the first contact 128, and a storage node (not shown) is formed on the third contact 154.

According to the conventional method, when a contact is formed by filling doped polysilicon, a metal contact is formed on the polysilicon contact to reduce the resistance of the contact, and a barrier metal layer such as Ti / TiN is formed on the interface. However, in this case, there is a problem in that a misalignment occurs due to a defect in a pattern during an etch back or a CMP process for node separation.

In contrast, in the present invention, titanium silicide is formed between the contacts made of doped polysilicon and between the contacts and the silicon substrate, thereby obtaining a lower resistance contact at the interface of the contacts, and node separation. It can also be easily performed.

Finally, a DRAM device is completed by forming a capacitor connecting to the storage node contact and metal wires (not shown) for electrically connecting the capacitor and the bit line structures.

According to the present invention as described above, after forming a first insulating layer including a first contact hole on the substrate and the first titanium silicide formed on the bottom surface of the first contact hole, the doped in the first contact hole A first contact made of polysilicon is formed. A second insulating layer including a second contact hole is formed on the first contact, a second titanium silicide is formed on a bottom surface of the second contact hole, and a second contact is formed in the second contact hole.

Accordingly, by forming titanium silicide on the bottom surface of the contact hole when forming the contacts made of doped polysilicon, contact resistance may be reduced at the interface between the substrate and the first contact and at the interface between the first and second contacts. In addition, by using titanium silicide, the problem of misalignment of polysilicon contacts is solved because node separation is easier than in the case of forming a tungsten layer in order to reduce contact resistance on a conventional polysilicon contact and separating the nodes by CMP. Can be blocked. In addition, when the node separation process is performed by CMP, alignment is difficult, and thus, an additional photolithography process is not required, thereby reducing the cost increase due to the addition of the process.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (5)

Forming a first insulating layer including a first contact hole exposing the conductive region on a substrate having the conductive region; Forming a first titanium layer on the sidewalls, the bottom surface, and the first insulating layer of the first contact hole; Converting the first titanium layer to first titanium silicide while depositing a first conductive layer of polysilicon doped on the first titanium layer while filling the first contact hole; Removing the first conductive layer and the first titanium silicide until the first insulating layer is exposed to form a first contact in the first contact hole; Forming a second insulating layer having a second contact hole exposing the first contact on the first insulating layer and the first contact; Forming a second titanium layer on the sidewalls, the bottom surface, and the second insulating layer of the second contact hole; Converting the second titanium layer to a second titanium silicide while depositing a second conductive layer of polysilicon doped on the second titanium layer while filling the second contact hole; And Removing the second conductive layer and the second titanium silicide until the second insulating layer is exposed to form a second contact in the second contact hole. The method of claim 1, wherein the first and second titanium layers are deposited by a chemical vapor deposition (CVD) process. The method of claim 1, further comprising forming a single crystal silicon layer on the conductive region by a selective epitaxial growth method before forming the first insulating layer on the substrate having the conductive region. A polysilicon contact forming method of a semiconductor device. The method of claim 1, wherein the second contact is a direct contact in contact with the bit line. The method of claim 1, wherein the second contact is a buried contact in contact with a storage node.

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