KR100543459B1 - Method of forming a self-aligned contact - Google Patents

Abstract

A method of forming a self-aligned contact is provided. According to this method, first, a contact hole is formed on the semiconductor substrate through the interlayer insulating film to expose the first spacer covering the sidewall of the conductive film pattern and the conductive portion under the interlayer insulating film. A second spacer is formed to cover sidewalls of the interlayer insulating layer exposed by the contact hole. A cleaning process is performed to remove the native oxide film. The contact hole is filled with a conductive material. Accordingly, by forming a second spacer covering only sidewalls of the interlayer insulating layer exposed by the contact hole, it is possible to prevent a bridge phenomenon between the contacts and to increase the contact resistance of the contact, thereby improving reliability of the semiconductor device.

SAC, USG

Description

Method of forming a self-aligned contact

1A to 1C are cross-sectional views illustrating a method of forming a self-aligned contact according to the prior art.

2A through 2F are process cross-sectional views sequentially illustrating a method of forming a self-aligned contact according to an embodiment of the present invention.

3A through 3F are cross-sectional views sequentially illustrating a method of forming a self-aligned contact according to another exemplary embodiment of the present invention.

4 is a graph showing deposition thickness over time of a USG film formed according to a selective deposition method.

The present invention relates to a method of forming a semiconductor device, and more particularly, to a method of forming a self-aligned contact.

As semiconductor devices are highly integrated, the cell size occupied by memory cells per unit area is also rapidly decreasing. Small cell size is possible by reducing the spacing between the conductive lines that make up the cell. In such a highly integrated semiconductor device, the distance between the contact hole connecting the lower wiring layer and the upper wiring layer and its adjacent wirings is reduced, and the aspect ratio of the contact hole is increased. Therefore, in a highly integrated semiconductor device employing a multilayer wiring structure, it is difficult to realize a desired process reproducibly when forming a contact hole using a photolithography process. To overcome this, self-aligned contact technology has been developed.

1A to 1C are cross-sectional views illustrating a method of forming a self-aligned contact according to the prior art.

Referring to FIG. 1A, an isolation region 3 is formed on a semiconductor substrate 1 to define an active region. Although not shown, a word line (not shown) is formed to cross the active region, a capping film made of a silicon nitride film is formed on the word line, and a spacer made of silicon nitride film is formed to cover sidewalls of the word line. Protect the line. An interlayer insulating film 5 is formed to cover the word line surrounded by the silicon nitride film to fill the space between the word lines. As the interlayer insulating film 5, a BPSG (Boron Phosphorus Silicate Glss) or a SOG (Spin On Glass) film having good layer covering property is used. The interlayer insulating film 5 between the word lines is patterned to form a contact hole 7 exposing the semiconductor substrate 1. In this case, the patterning process is performed by using a high etching selectivity of the interlayer insulating film 5 made of a silicon oxide film and the spacer made of a silicon nitride film. FIG. 1A shows a cross-sectional view of the semiconductor substrate 1 including the interlayer insulating film 5 in which contact holes 7 are formed in a direction parallel to the word line. When the wafer after the completion of the process is exposed to the atmosphere, a natural oxide film 9 is formed on the semiconductor substrate 1 exposed by the contact hole 7. This increases the resistance of the interface between the contact to be subsequently formed and the semiconductor substrate 1, thereby inhibiting the driving of the semiconductor element.

Referring to FIG. 1B, a cleaning process for removing the natural oxide film 9 is performed. The BPSG or SOG film forming the interlayer insulating film 5 has good layer covering property but low density. Accordingly, in the cleaning process, the interlayer insulating film 5 is excessively etched to form holes E in the sidewall of the interlayer insulating film 5, as shown in FIG. 1B, so that the contact holes 7 are adjacent to the contact holes 7. Can be connected.

Referring to FIG. 1C, the contact layer 7 may be formed by stacking conductive layers to fill the contact hole 7. At this time, the contact 11 is connected to the neighboring contact 11 (bridge between the contacts) by the hole E, thereby reducing the reliability of the semiconductor device.

In order to prevent this, in the related art, after forming the contact hole, the silicon nitride film is conformally thinly stacked, and then the silicon nitride film at the bottom of the contact hole is removed by anisotropic etching, and then a cleaning process is performed. In this case, although the hole E is not formed, the area of the bottom of the contact hole is narrowed by the silicon nitride film, thereby increasing the resistance of a subsequent contact.

Accordingly, an object of the present invention to solve the above problems is to provide a self-aligned contact forming method that can improve the reliability of the semiconductor device while sufficiently securing the bottom area of the contact hole.

The self-aligned contact forming method according to the present invention for achieving the above technical problem is characterized by forming a spacer covering only the sidewall of the interlayer insulating film exposed by the contact hole.

In more detail, the method is as follows. First, a first hole covering the sidewall of the conductive layer pattern and a contact hole exposing the conductive portion under the interlayer insulating layer are formed on the semiconductor substrate through the interlayer insulating layer. A second spacer is formed to cover sidewalls of the interlayer insulating layer exposed by the contact hole. A cleaning process is performed to remove the native oxide film. The contact hole is filled with a conductive material.

In the method, the first spacer is formed of a silicon nitride film.

In the above method, the second spacer may be formed by selectively forming a USG (Undoped Silicate Glass) film on the surface of the interlayer insulating film and the semiconductor substrate and etching the USG film anisotropically. At this time, the USG film is supplied at least one source gas selected from the group containing ozone (O ₃ ), oxygen (O ₂ ), TEOS (tetracthyl orthosilicate) at a temperature of 400 ~ 480 ℃ and a pressure of 500 ~ 700 Torr Can be formed.

Self-aligned contact forming method according to an aspect of the present invention is as follows. First, a gate insulating film and a conductive film are sequentially formed on a semiconductor substrate including the device isolation film. A capping layer pattern is formed on the conductive layer. By using the capping layer pattern as an etching mask, the conductive layer and the gate insulating layer are sequentially patterned to form a gate pattern including a gate insulating layer pattern and a conductive layer pattern. An impurity region is formed in the semiconductor substrate using the capping layer pattern as an ion implantation mask. A first spacer covering sidewalls of the gate pattern and the capping layer pattern is formed. An interlayer insulating film is formed to fill the gate patterns. The interlayer insulating layer is patterned to form a contact hole exposing the first spacer and the impurity region. A second spacer is formed to cover sidewalls of the interlayer insulating layer exposed by the contact hole. A cleaning process is performed to remove the native oxide film. The contact hole is filled with a conductive material.

Self-aligning contact forming method according to another aspect of the present invention is as follows. First, a conductive film is formed on the lower interlayer insulating film including the conductive portion. A capping layer pattern is formed on the conductive layer. The conductive layer is patterned by using the capping layer pattern as an etching mask to form a conductive layer pattern. A first spacer covering sidewalls of the conductive layer pattern and the capping layer pattern is formed. An interlayer insulating film is formed to fill between the conductive film patterns. The interlayer insulating layer is patterned to form a contact hole exposing the first spacer and the conductive portion. A second spacer is formed to cover sidewalls of the interlayer insulating layer exposed by the contact hole. A cleaning process is performed to remove the native oxide film. The contact hole is filled with a conductive material.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the spirit of the present invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Portions denoted by like reference numerals denote like elements throughout the specification.

<Example 1>

2A through 2F are process cross-sectional views sequentially illustrating a method of forming a self-aligned contact according to an embodiment of the present invention.

Referring to FIG. 2A, an isolation region 102 is formed in the semiconductor substrate 100 to define an active region. The device isolation layer 102 may be formed by a conventional shallow trench isolation method. A gate insulating film and a conductive film are sequentially formed on the semiconductor substrate 100. The gate insulating film may be formed of a thermal oxide film or deposited by a CVD method. The conductive layer may be formed of one material selected from the group including polysilicon, tungsten, aluminum, copper, titanium, tantalum, tantalum nitride, and titanium nitride, which are doped or doped with impurities. Although not shown, a metal silicide film (not shown) may be formed on the conductive film. A capping film is formed on the conductive film. The capping layer may be formed of a silicon nitride layer. The capping layer is patterned to form a capping layer pattern 108. The capping layer pattern 108 is used as an etching mask to sequentially pattern the conductive layer and the gate insulating layer to form a gate pattern including the gate insulating layer pattern 104 and the conductive layer pattern 106.

Referring to FIG. 2B, the impurity region 109 is formed in the active region of the semiconductor substrate 100 using the capping layer pattern 108 as an ion implantation mask. The impurity region may be P-type or N-type depending on the required characteristics of the semiconductor device. An insulating film is conformally stacked on the semiconductor substrate on which the gate pattern is formed. The insulating film may be formed of a silicon nitride film. The insulating layer is etched back to form a first spacer 110 covering sidewalls of the capping layer pattern 108 and the gate pattern.

Referring to FIG. 2C, an interlayer insulating layer 111 is formed on the entire surface of the semiconductor substrate 110 on which the first spacers 110 are formed to fill the gaps between the gate patterns. The interlayer insulating film 111 may be formed of a BPSG or SOG film having good layer covering property. A planarization process is performed on the interlayer insulating layer 111 to expose an upper portion of the capping layer pattern 108. In this case, the planarization process may be CMP or etch back.

Referring to FIG. 2D, a predetermined region of the interlayer insulating layer 111 is patterned to form a contact hole 112 exposing the first spacer 110 and the impurity region 109.

Referring to FIG. 2E, a USG (Undoped Silicate Glass) film is selectively formed on the surface of the impurity region 1109 and the interlayer insulating film 111 of the semiconductor substrate. The USG film may be formed by supplying at least one source gas selected from the group consisting of ozone (O ₃ ), oxygen (O ₂ ), and TEOS (tetracthyl orthosilicate) at a temperature of 400-480 ° C. and a pressure of 500-700 Torr. Can be. In this case, the USG film may be formed by a CVD method and He may be used as a carrier gas. When the USG film is formed under the above conditions, the USG film is not deposited on the surfaces of the capping film pattern 108 and the first spacer 110 made of a silicon nitride film. The USG film is etched back or anisotropically etched to form the second spacer 114 that exposes the impurity region 109 and covers sidewalls of the interlayer insulating layer 111 exposed by the contact hole 112. The second spacer 114 formed of the USG film has a higher film density than the interlayer insulating film 111.

Referring to FIG. 2F, a cleaning process is performed to remove a natural oxide film (not shown) that may be formed on the impurity region 109. Since the second spacer 114 made of the USG film has a hard film, the amount of etching of the second spacer 114 in the cleaning process is small. Therefore, the interlayer insulating film 111 may be protected by the second spacer 114, so that the hole (E of FIG. 1B) is not formed as in the prior art. The contact hole 114 is filled with a conductive material to form a contact 116 electrically connected to the impurity region 109. The conductive material may be formed of one material selected from the group consisting of polysilicon, tungsten, aluminum, copper, titanium, tantalum, tantalum nitride film, and titanium nitride film doped with or without doping impurities.

In the above method, since the second spacer 114 covers only the sidewalls of the interlayer insulating layer 111, it does not occupy much of the bottom area of the contact hole 112, and thus the contact area of the subsequent contact is not narrowed. . Therefore, the contact resistance of the contact does not increase significantly, and the bridge between the contacts can be prevented.                     

<Example 2>

3A through 3F are cross-sectional views sequentially illustrating a method of forming a self-aligned contact according to another exemplary embodiment of the present invention.

Referring to FIG. 3A, a lower interlayer insulating film 200 is formed on a semiconductor substrate (not shown). The lower interlayer insulating film 200 may be formed of a BPSG or SOG film. Although not shown, various devices such as transistors and contacts may be formed on the semiconductor substrate (not shown), and the lower interlayer insulating film 200 may cover the various devices. A conductive part 201 is formed through the lower interlayer insulating film 200 to be electrically connected to the various devices. A conductive film and a capping film are sequentially formed on the lower interlayer insulating film 200 having the conductive portion 201. The capping layer is etched by a photolithography process to form a capping layer pattern 204. The conductive layer is patterned using the capping layer pattern 204 as an etch mask to form a conductive layer pattern 202 that crosses the lower interlayer insulating layer 200. Forming materials of the conductive film and the capping film are the same as those of the conductive film and the capping film in the first embodiment.

Referring to FIG. 3B, an insulating film is conformally stacked on the semiconductor substrate on which the conductive film pattern 202 is formed. The insulating film may be formed of a silicon nitride film. The insulating layer is etched back to form a first spacer 206 covering sidewalls of the capping layer pattern 204 and the conductive layer pattern 202.

Referring to FIG. 3C, an interlayer insulating layer 208 is formed on an entire surface of the lower interlayer insulating layer 200 on which the first spacer 206 is formed to fill the gaps between the conductive layer patterns 202. The material of forming the interlayer insulating layer 208 may be the same as that of the interlayer insulating layer 111 of the first embodiment. A planarization process is performed on the interlayer insulating layer 208 to expose an upper portion of the capping layer pattern 204.

Referring to FIG. 3D, a predetermined region of the interlayer insulating layer 208 is patterned to form a contact hole 210 exposing the first spacer 206 and the conductive portion 201.

Referring to FIG. 3E, a second spacer 212 is formed on sidewalls of the interlayer insulating layer 208 exposed by the contact hole 210. The second spacer 212 may be formed of the same material and method as the first embodiment.

Referring to FIG. 3F, a cleaning process for removing a natural oxide film (not shown) that may be formed on the conductive portion 201 is performed. In this case, like the first embodiment, the interlayer insulating layer 208 may be protected by the second spacer 212 having a hard film quality. The contact hole 212 is filled with a conductive material to form a contact 214 electrically connected to the impurity region 201.

Therefore, according to the self-aligned contact forming method according to the present invention, by forming a spacer covering only the sidewalls of the interlayer insulating film exposed by the contact hole to prevent the bridge phenomenon between the contacts, and to increase the contact resistance of the contact to reduce the semiconductor device Can improve the reliability.

Claims (12)

Forming a contact hole through the interlayer insulating layer on the semiconductor substrate to expose the first spacer covering the sidewalls of the conductive layer pattern and the conductive portion under the interlayer insulating layer; Forming a second spacer covering a sidewall of the interlayer insulating film exposed by the contact hole; Performing a cleaning process for removing a native oxide film; And And filling the contact hole with a conductive material. The method of claim 1, And the first spacer is formed of a silicon nitride film. The method of claim 1, Forming the second spacer, Selectively forming an Undoped Silicate Glass (USG) film on the surface of the interlayer insulating film and the semiconductor substrate, and Etching the USG film. The method of claim 3, wherein The USG film is formed by supplying at least one source gas selected from the group comprising ozone (O ₃ ), oxygen (O ₂ ), and TEOS (tetracthyl orthosilicate) at a temperature of 400-480 ° C. and a pressure of 500-700 Torr. Method for forming a self-aligned contact, characterized in that. Sequentially forming a gate insulating film and a conductive film on the semiconductor substrate including the device isolation film; Forming a capping layer pattern on the conductive layer; Forming a gate pattern including a gate insulating layer pattern and a conductive layer pattern by sequentially patterning the conductive layer and the gate insulating layer using the capping layer pattern as an etching mask; Forming an impurity region in the semiconductor substrate using the capping layer pattern as an ion implantation mask; Forming a first spacer covering sidewalls of the gate pattern and the capping layer pattern; Forming an interlayer insulating film to fill the gaps between the gate patterns; Patterning the interlayer insulating layer to form a contact hole exposing the first spacer and the impurity region; Forming a second spacer covering a sidewall of the interlayer insulating film exposed by the contact hole; Performing a cleaning process for removing a native oxide film; And And filling the contact hole with a conductive material. The method of claim 5, And the first spacer is formed of a silicon nitride film. The method of claim 5, Forming the second spacer, Selectively forming an Undoped Silicate Glass (USG) film on the surface of the interlayer insulating film and the semiconductor substrate, and Etching the USG film. The method of claim 7, wherein The USG film is formed by supplying at least one source gas selected from the group comprising ozone (O ₃ ), oxygen (O ₂ ), and TEOS (tetracthyl orthosilicate) at a temperature of 400-480 ° C. and a pressure of 500-700 Torr. Method for forming a self-aligned contact, characterized in that. Forming a conductive film on the lower interlayer insulating film including the conductive part; Forming a capping layer pattern on the conductive layer; Patterning the conductive layer using the capping layer pattern as an etching mask to form a conductive layer pattern; Forming a first spacer covering sidewalls of the conductive layer pattern and the capping layer pattern; Forming an interlayer insulating film to fill the gaps between the conductive film patterns; Patterning the interlayer insulating layer to form a contact hole exposing the first spacer and the conductive portion; Forming a second spacer covering a sidewall of the interlayer insulating film exposed by the contact hole; Performing a cleaning process for removing a native oxide film; And And filling the contact hole with a conductive material. The method of claim 9, And the first spacer is formed of a silicon nitride film. The method of claim 9, Forming the second spacer, Selectively forming an Undoped Silicate Glass (USG) film on the surface of the interlayer insulating film and the semiconductor substrate, and Etching the USG film. The method of claim 11, The USG film is formed by supplying at least one source gas selected from the group comprising ozone (O ₃ ), oxygen (O ₂ ), and TEOS (tetracthyl orthosilicate) at a temperature of 400-480 ° C. and a pressure of 500-700 Torr. Method for forming a self-aligned contact, characterized in that.

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