TWI677053B - 氣隙閘極側壁間隔件及方法 - Google Patents

氣隙閘極側壁間隔件及方法 Download PDF

Info

Publication number
TWI677053B
TWI677053B TW106119240A TW106119240A TWI677053B TW I677053 B TWI677053 B TW I677053B TW 106119240 A TW106119240 A TW 106119240A TW 106119240 A TW106119240 A TW 106119240A TW I677053 B TWI677053 B TW I677053B
Authority
TW
Taiwan
Prior art keywords
gate
dielectric layer
dielectric
plug
sacrificial
Prior art date
Application number
TW106119240A
Other languages
English (en)
Other versions
TW201841303A (zh
Inventor
丹尼爾 恰尼莫蓋姆
Daniel Chanemougame
恩德 拉伯特
Andre Labonte
瑞龍 謝
Ruilong Xie
拉爾斯 賴柏曼
Lars Liebmann
尼格爾 凱夫
Nigel Cave
古拉密 波奇
Guillaume Bouche
Original Assignee
格羅方德半導體公司
Globalfoundries Us Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 格羅方德半導體公司, Globalfoundries Us Inc. filed Critical 格羅方德半導體公司
Publication of TW201841303A publication Critical patent/TW201841303A/zh
Application granted granted Critical
Publication of TWI677053B publication Critical patent/TWI677053B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
    • H01L29/4991—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material comprising an air gap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H01L21/28141—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects insulating part of the electrode is defined by a sidewall spacer, e.g. dummy spacer, or a similar technique, e.g. oxidation under mask, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/764—Air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/845—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1211—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/6681—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET using dummy structures having essentially the same shape as the semiconductor body, e.g. to provide stability
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/66689—Lateral DMOS transistors, i.e. LDMOS transistors with a step of forming an insulating sidewall spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66719—With a step of forming an insulating sidewall spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13067—FinFET, source/drain region shapes fins on the silicon surface
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/36—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being a FinFET

Abstract

所揭示為積體電路(IC)結構和其形成方法。在該等方法中，在通道區域上形成具有犧牲性閘極蓋和犧牲性閘極側壁間隔件的閘極。該蓋和側壁間隔件被移除，形成空穴，其具有位於該閘極的側壁和相鄰金屬栓塞之間的下部部分以及具有在該下部部分和該閘極上方的上部部分。沉積第一介電質層，在該下部部分中形成氣隙並對齊該上部部分。沉積第二介電質層，填補該上部部分。在形成閘極接點開口(視需要在主動區上)期間，該第二介電質層被移除而該第一介電質層被非等向性蝕刻，從而曝露該閘極並產生具有下氣隙段和上實心段的介電質間隔件。沉積進入開口內的金屬形成該閘極接點。

Description

氣隙閘極側壁間隔件及方法
本發明有關於積體電路(IC)結構，更具體而言，關於一種形成IC結構的方法，該方法使用一個或多個具有氣隙閘極側壁的電晶體且視需要地，具有在主動區(CBoA)上方或其附近的閘極接點(CB)。
近來，形成積體電路(IC)結構之方法已經被發展到能夠形成具有氣隙閘極側壁間隔件的場效電晶體(FET)了。以這種氣隙閘極側壁間隔件，與具有傳統閘極側壁間隔件之FET相比，寄生電容(例如，在FET源極/汲極區域上之FET閘極與金屬栓塞之間的電容)被減少了。此外，形成積體電路(IC)結構之方法已經發展到能夠形成在主動區(CBoA)上具有閘極接點的FET以允許區域進行縮放。更具體而言，中段製程(MOL)接點為將場效電晶體(FET)連接至後段製程(BEOL)金屬層之接點。這些MOL接點包括至少一個閘極接點(CB)和源極/汲極接點(CAs)。閘極接點通過層間介電質(ILD)材料從第一BEOL金屬層(本文稱為M 0 層)中的金屬線或通孔垂直延伸到FET之閘極。每個源極/汲極接點通過ILD材料從該 第一BEOL金屬層中的金屬線或通孔垂直延伸到位於FET的源極/汲極區域之上且與其緊緊相鄰的金屬栓塞(TS)。用於形成這些MOL接點之傳統技術固有地包括以下風險：(a)在該閘極接點與金屬栓塞之間發生短路，特別是如果該閘極接點係位於主動區域上方或其附近；以及(b)在源極/汲極接點與該閘極之間發生短路。然而，在不會引起上述短路風險之下，新技術已經被開發以提供這些MOL接點之形成。不幸的是，目前用於形成具有氣隙閘極側壁間隔件之FET的技術與用於形成在主動區(CBoA)上具有閘極接點之FET的技術不相容。
鑑於上述內容，本文所揭示為用於形成具有一個或多個電晶體之積體電路(IC)結構的方法，每個電晶體都具有氣隙閘極側壁間隔件，以及視需要地，在主動區上或其附近的閘極接點(例如，CBoA)。
一般而言，每個方法可以包括形成至少一個電晶體。在形成該電晶體期間，閘極能形成在通道區域上與半導體本體相鄰，其中該通道區域橫向定位在源極/汲極區域之間，而該閘極具有犧牲性閘極蓋和犧牲性閘極側壁間隔件。具有塞蓋之金屬栓塞能被形成於源極/汲極區域上，以便被橫向定位且緊緊相鄰於犧牲性閘極側壁間隔件。隨後，犧牲性閘極蓋和犧牲性閘極側壁間隔件能被選擇性地從閘極被蝕刻掉，以在該閘極周圍形成空穴。這空穴能具有下部部分和上部部分，其中下部部分曝露閘極之 側壁和在該閘極相對側的金屬栓塞，以及其中上部部分位於該下部部分和閘極上方。
在該閘極周圍形成空穴之後，第一介電質層能以這樣的方式沉積到空穴中，以在空穴的下部部分內形成氣隙以及對空穴上部部分進行排列。第二介電質層可能被沉積於第一介電質層上，填補空穴的上部部分。在後續用於閘極接點的閘極接點開口的形成期間，第二介電質層能被移除以及第一介電質層能被非等向性蝕刻，從而產生具有下氣隙段和上實心段之介電質間隔件。由於用於金屬栓塞上塞蓋、第一介電質層及第二介電質層為不同介電質材料，閘極接點開口將會被自動對準到閘極。因此，閘極接點能形成於主動區之上(或靠近其上)，而不具導致相鄰金屬栓塞短路之風險。
本文揭示的一個特定方法實施例形成具有多個FET之積體電路(IC)結構，每個FET具有氣隙閘極側壁間隔件和視需要地，在主動區上或與其附近之閘極接點(例如，CBoA)。
在這方法實施例中，可以形成多個電晶體。在形成電晶體期間，閘極能形成在通道區域上與半導體本體相鄰，其中每個通道區域橫向定位於源極/汲極區域之間。每個閘極能具體地被形成以致於具有犧牲性閘極蓋和犧牲性閘極側壁間隔件。另外，金屬栓塞能被形成於源極/汲極區域上，使得每個金屬栓塞橫向定位且緊緊相鄰於至少一個犧牲性閘極側壁間隔件。金屬栓塞能被回蝕以在金 屬栓塞上方形成凹槽，並且能在凹槽內形成塞蓋。隨後，犧牲性閘極蓋和犧牲性閘極側壁間隔件能從每個閘極選擇性地被蝕刻掉以在閘極周圍形成空穴。每個在各個閘極周圍的各個空穴能具有下部部分和上部部分，其中下部部分曝露閘極之側壁和閘極相對側之相鄰金屬栓塞，以及其中上部部分位於下部部分和閘極上方。
在閘極周圍形成空穴之後，第一介電質層能沉積到空穴中，使得在每個空穴中，氣隙形成於空穴的下部部分中，以及第一介電質層排列上部部分空穴。第二介電質層能被沉積到第一介電質層上的空穴中，從而填補每個空穴的上部部分。第一介電質層和第二介電質層之後能從塞蓋上方被移除(例如，透過執行化學機械拋光(CMP)製程)以及層間介電質層能被形成於塞蓋之上並與其緊緊相鄰，且進一步在空穴中的第一和第二介電質層上橫向延伸。
接點能形成通過層間介電質層到至少一個閘極和至少一個金屬栓塞。在形成閘極接點開口期間，第二介電質層能被移除和第一介電質層能被非等向性蝕刻，從而產生具有下氣隙段和上實心段之介電質間隔件。由於用於塞蓋、第一介電質層及第二介電質層為不同介電質材料，所以閘極接點開口將會自動對準到閘極。因此，閘極接點能形成於主動區之上(或其附近)，而不具導致相鄰金屬栓塞短路之風險。
本文還揭示了根據上述方法形成的積體電路 (IC)結構，以便具有一個或多個電晶體，每個電晶體都具有氣隙閘極側壁間隔件以及，視需要地，在主動區(例如，CBoA)上或與其附近的閘極接點。每個IC結構能被併入至少一個電晶體。每個電晶體能在通道區域上具有與半導體本體相鄰的閘極。通道區域能被橫向定位於源極/汲極區域之間。閘極接點能被定位於閘極之上並與其緊緊相鄰。金屬栓塞能在源極/汲極區域上，而塞蓋能在金屬栓塞之上並與其緊緊相鄰。每個電晶體還能進一步具有介電質間隔件，其具有下氣隙段和上實心段。下氣隙段能橫向定位於閘極與金屬栓塞之間，而上實心段能位於下氣隙段之上並橫向位於閘極接點與塞蓋之間。視需要地，介電質間隔件能在半導體本體與下氣隙段之間具有附加區段。介電質間隔件之上實心段、介電質間隔件之視需要的附加區段及塞蓋能由三種不同介電質材料製成。
101‧‧‧流程
102‧‧‧流程
104‧‧‧流程
106‧‧‧流程
108‧‧‧流程
110‧‧‧流程
112‧‧‧流程
114‧‧‧流程
115‧‧‧流程
116‧‧‧流程
117‧‧‧流程
118‧‧‧流程
119‧‧‧流程
120‧‧‧流程
121‧‧‧流程
122‧‧‧流程
123‧‧‧流程
124‧‧‧流程
125‧‧‧流程
200‧‧‧IC結構
201‧‧‧第一finFET、第一FET、第一電晶體
202‧‧‧第二finFET、第二電晶體
203‧‧‧半導體晶圓
204‧‧‧半導體基板
205‧‧‧絕緣體層
210‧‧‧半導體本體、單一半導體鰭片
211‧‧‧通道區域
212‧‧‧源極/汲極區域
213‧‧‧凸起磊晶源極/汲極區域
231‧‧‧犧牲性閘極
232‧‧‧犧牲性閘極蓋、第一犧牲性閘極蓋
240‧‧‧犧牲性閘極側壁間隔件
241‧‧‧區段、附加區段
243‧‧‧閘極開口
248‧‧‧金屬栓塞
249‧‧‧塞蓋、氧化矽塞蓋、氧化塞蓋
250‧‧‧層間介電質(ILD)層、覆面ILD層
260‧‧‧替代金屬閘極、閘極
261‧‧‧共形高K閘極介電質層、閘極介電質層
262‧‧‧一個或多個金屬層
263‧‧‧第二犧牲性閘極蓋、犧牲性閘極蓋
265‧‧‧空穴
2651‧‧‧空穴下部部分
2652‧‧‧空穴上部部分
270‧‧‧第一介電質層
271‧‧‧氣隙
275‧‧‧第二介電質層
276‧‧‧介電質間隔件
277‧‧‧下氣隙段、氣隙
278‧‧‧上實心段
281‧‧‧第一遮罩層
282‧‧‧第二遮罩層
290‧‧‧ILD層
291‧‧‧源極/汲極接點開口
293‧‧‧閘極接點開口
294‧‧‧源極/汲極接點
295‧‧‧閘極接點
從以下參照附圖之詳細說明，本發明將會更好被理解，其附圖不一定按比例繪製，其中：第1圖係為一流程圖，其示出了形成具有一個或多個電晶體之積體電路(IC)結構的方法，每個電晶體都具有氣隙閘極側壁間隔件以及視需要地，在主動區(CBoA)上或與其靠近的閘極；第2A圖與第2B圖分別為一俯視圖與一剖面圖，其示出了根據第1圖之流程圖而形成的部分完成結構；第3A圖與第3B圖分別為一俯視圖與一剖面 圖，其示出了根據第1圖之流程圖而形成的部分完成結構；第4圖係為一俯視圖，其示出了根據第1圖之流程圖而形成的部分完成結構；第5圖係為一俯視圖，其示出了根據第1圖之流程圖而形成的部分完成結構；第6A圖與第6B-D圖分別為一俯視圖與剖面圖，其示出了根據第1圖之流程圖而形成的部分完成結構；第7A圖與第7B圖分別為一俯視圖與一剖面圖，其示出了根據第1圖之流程圖而形成的部分完成結構；第8A圖與第8B圖分別為一俯視圖與一剖面圖，其示出了根據第1圖之流程圖而形成的部分完成結構；第9A圖與第9B-9C圖分別為一俯視圖與剖面圖，其示出了根據第1圖之流程圖而形成的部分完成結構；第10A圖與第10B-10C圖分別為一俯視圖與剖面圖，其示出了根據第1圖之流程圖而形成的部分完成結構；第11-21圖係為剖面圖，其示出了根據第1圖之流程圖而形成的部分完成結構；以及，第22圖係為一剖面圖，其示出了根據第1圖之流程圖而形成的完成結構。
如上所述，形成積體電路(IC)結構之方法已經發展到能夠形成具有氣隙閘極側壁間隔件的場效電晶 體(FET)。以這種氣隙閘極側壁間隔件，與具有傳統閘極側壁間隔件之FET相比，寄生電容(例如，FET閘極與FET源極/汲極區域上金屬栓塞之間的電容)能被減少。此外，形成積體電路(IC)結構之方法已經發展到能夠在主動區(CBoA)上形成具有閘極接點的FET以允許區域進行縮放。更具體而言，中段製程(MOL)接點為將場效電晶體(FET)連接至後段製程(BEOL)金屬層之接點。這些MOL接點包括至少一個閘極接點(CB)和源極/汲極接點(CAs)。該閘極接點通過層間介電質(ILD)材料從第一BEOL金屬層(本文稱為M 0 層)中的金屬線或通孔垂直延伸到FET之閘極。每個源極/汲極接點通過ILD材料從第一BEOL金屬層中的金屬線或通孔垂直延伸到位於FET的源極/汲極區域之上並與其緊緊相鄰的金屬栓塞(TS)。用於形成這些MOL接點之傳統技術固有地包括以下風險：(a)在閘極接點與金屬栓塞之間發生短路，特別是如果閘極接點係位於主動區域上方或其附近；以及(b)在源極/汲極接點與閘極之間發生短路。然而，新技術已經被開發以提供這些MOL接點之形成而不會引起上述短路風險。不幸的是，目前用於形成具有氣隙閘極側壁間隔件之FET的技術與用於形成在主動區(CBoA)上具有閘極接點之FET的技術不相容。
鑑於上述內容，本文揭示了具有一個或多個電晶體之積體電路(IC)結構，其每個電晶體都具有氣隙閘極側壁間隔件且視需要地，在主動區上(例如，CBoA) 或其附近的閘極接點。在該等方法中，具有犧牲性閘極蓋和犧牲性閘極側壁間隔件之閘極能被形成於通道區域上，而具有塞蓋之金屬栓塞能被形成於源極/汲極區域。該犧牲性閘極蓋與犧牲性閘極側壁間隔件能被選擇性移除，從而產生具有下部部分和上部部分之空穴，其中下部部分位於閘極的側壁和閘極相對側上的相鄰的金屬栓塞之間，而該上部部分位於下部部分與閘極的上方。可以沉積第一介電質層，在空穴之下部部分內形成氣隙並對齊上部部分。可以沉積第二介電質層於第一介電質層上，填補空穴之上部部分。在為閘極接點形成閘極接點開口期間，第二介電質層能被移除而第一介電質層被非等向性蝕刻，從而產生具有橫向定位且相鄰於閘極之下空隙段和位於下氣隙段上方之上實心段的介電質間隔件。由於用於塞蓋、第一介電質層及第二介電質層為不同介電質材料，這閘極接點開口被自動對準到閘極。因此，在不具導致相鄰金屬栓塞短路之風險之下，該閘極接點能被形成於主動區之上(或其附近)。本文還揭示了根據這些方法而形成的IC結構。
參照第1圖的流程圖，一般在本文所揭示的方法中會提供半導體晶圓203(101)。在流程101所提供的半導體晶圓203能是例如，絕緣層上半導體晶圓(例如，矽晶絕緣體(SOI)晶圓)，其包括半導體基板204(例如，矽基板)、絕緣體層205(例如，埋藏氧化(BOX)層或其它在半導體基板上合適的絕緣體層)以及在絕緣體層205上的半導體層(例如，矽層或其它合適的半導體層)(見第 2A-2B圖)。或者，可以使用大塊半導體晶圓(例如，大塊矽晶圓或其它合適的大塊半導體晶圓)。
至少一個場效電晶體(FET)能被形成於半導體晶圓203上(102)。為了說明之用意，該等方法會在以下做描述並在附圖中示出了關於共享單個半導體本體(例如單個半導體鰭片)和具有相同類型導電性的兩個非平面FET(例如，鰭式FET)的形成。然而，應當理解的是，根據這些方法而形成的FET數量和類型不限於此。舉例而言，視需要地，所揭示之方法可以被用來形成多鰭片鰭式FET、平面FET、具不同類型導電性之FET等等。
在任何情況下，在流程102中，至少一個半導體本體210能被形成。半導體本體210能例如是半導體鰭片(例如，相對薄之矩形或鰭片狀半導體本體)。該半導體本體210能被圖案化並從SOI晶圓之半導體層中(或可替代地，當通過埋藏井區從大塊半導體基板的下部部分隔離時，從大塊半導體基板之上部部分脫開，)被蝕刻。用於形成這種半導體本體的技術(例如，光蝕刻圖案化技術或側壁影像轉移技術)在所屬技術領域中眾所周知，因此這些細節會從說明書中省略以讓讀者能夠集中在所揭示方法的顯著態樣上。
對於每個FET，該半導體本體210能具有指定區域，其用於源極/汲極區域212和橫向地被定位於源極/汲極區域212之間的通道區域211。為了說明之用意，第2A-2B圖示出了具有用於第一finFET201之第一通道區域 和用於第二finFET202之第二通道區域的單一半導體鰭片210，其中第一通道區域和第二通道區域被共享源極/汲極區域被隔開。在這種情況下，半導體本體210能在形成之前或之後與第一摻雜劑進行摻雜，使得每個通道區域211具有在相對低導電性水平的第一類型導電性。或者，每個通道區域211能保持未摻雜。
對於每個FET，具有犧牲性閘極蓋和犧牲性閘極側壁間隔件的閘極可以形成於與在通道區域211上半導體本體210相鄰。該等閘極能使用例如替代金屬閘極形成技術而形成。或者，該等閘極能使用常規閘極-第一閘極形成技術能被形成。為了說明之用意，以下會描述示例性替代金屬閘極形成技術。
具體而言，覆面第一犧牲性層(例如，犧牲性多晶矽層、犧牲性非晶矽層或其它合適之犧牲性層)可以形成於半導體本體210上。不同於第一犧牲性層的第二犧牲性層(例如，犧牲性氮化物層)，可以形成於該第一犧牲性層的頂面上。隨後，該第一和第二犧牲性層能被圖案化與被蝕刻以形成具有犧牲性閘極蓋232之犧牲性閘極231(在此也稱為虛擬閘極)，其與每個通道區域211相鄰。就finFET而言，如第3A-3B圖所示，每個犧牲性閘極231將會被定位在半導體本體210之頂面之上和與其相對側相鄰。接下來，犧牲性閘極側壁間隔件240能被形成於每個犧牲性閘極231的側壁上(見第4圖)。也就是說，相對薄之共形間隔件層(例如，氮化矽層)，能被沉積在部分完成 結構之上。然後，可以執行非等向性蝕刻製程以從水平面和在源極/汲極區域212之半導體本體210的側壁上移除共形間隔件層。那些所屬技術領域具有技術者將會意識到在每個犧牲性閘極231之第一犧牲性閘極蓋232的高度應該大約等於或大於半導體本體210之高度，使得共形間隔件層可以從源極/汲極區域212之半導體本體210的側壁被移除而不曝露犧牲性閘極側壁。
隨後可以執行摻雜劑注入製程，使得源極/汲極區域212具有例如在相對高導電性水平的第二類型導電性。另外或可替代地，磊晶半導體材料(例如，磊晶矽或其它合適的磊晶半導體材料)能被沉積在半導體本體210的已曝露部分(例如，在源極/汲極區域212上)，以形成凸起磊晶源極/汲極區域213(見第5圖)。磊晶半導體材料能被原位摻雜或隨後被注入，使得凸起磊晶源極/汲極區域213具有相對高導電性水平的第二類型導電性。或者，在沉積磊晶半導體材料之前，如上所述，源極/汲極區域212能被凹陷(未示出)，從而確保源極/汲極區域212和凸起磊晶源極/汲極區域213將會被摻雜，以便具有所需的導電性類型和程度。
接下來，層間介電質(ILD)層250可以形成於部分完成結構之上，然後被平坦化(見第6A-6D圖)。具體而言，覆面ILD層250(例如，覆面氧化矽層或其它合適的覆面ILD層)能被沉積，以覆蓋在每個犧牲性閘極231上的第一犧牲性閘極蓋232和犧牲性閘極側壁間隔件 240，以及覆蓋每個源極/汲極區域212(或凸起磊晶源極/汲極區域213，如果可以應用的話)。然後可以執行化學機械拋光(CMP)製程，以便至少曝露每個第一犧牲性閘極蓋232的頂部和相鄰的犧牲性閘極側壁間隔件240。
然後第一犧牲性閘極蓋232和下面的犧牲性閘極231能被移除，並由具有第二犧牲性閘極蓋263之替代金屬閘極260來代替(見第7A-7B和8A-8B圖)。舉例而言，每個第一犧牲性閘極蓋232和犧牲性閘極231的犧牲性材料能被選擇性地使用於犧牲性閘極側壁間隔件240和ILD層250的介電質材料上被蝕刻(見第7A-7B圖)。或者，如上所述的CMP製程能被繼續用於曝露每個第一犧牲性閘極蓋232的頂部直到每個犧牲性閘極蓋232被移除，從而曝露每個犧牲性閘極231之頂部。之後每個犧牲性閘極231能被選擇性蝕刻，從而移除每個犧牲性閘極231。在任何情況下，每個第一犧牲性閘極蓋232和下面的每個犧牲性閘極231的移除將在每個通道區域211上之ILD層250內形成閘極開口243，而每個閘極開口243將具有與犧牲性閘極側壁間隔件240對齊的側壁。
然後替代金屬閘極260可以形成於在通道區域211上之每個閘極開口243內並與犧牲性閘極側壁間隔件240緊緊相鄰。舉例而言，共形高K閘極介電質層261能被沉積以對齊閘極開口，而一個或多個金屬層262能被沉積到閘極介電質層261上。那些所屬技術領域中具有技術者將會意識到用於替代金屬閘極之介電質和金屬層的材 料和厚度能被預先選定，以實現在給定FET導電性類型下所需的功函數。在任何情況下，可以執行化學機械拋光(CMP)製程以從ILD層250的頂面上方移除所有閘極材料。然後，替代金屬閘極260之材料能被凹陷，使得每個替代金屬閘極的頂面低於ILD層250的頂面，而介電質蓋層能被沉積與平坦化以在每個替代金屬閘極260上形成第二犧牲性閘極蓋263(見第8A-8B圖)。該第二犧牲性閘極蓋263能由與犧牲性閘極側壁間隔件240相同的材料製成。舉例而言，第二犧牲性閘極蓋263和犧牲性閘極側壁間隔件240能分別由氮化矽製成。因此，每個替代金屬閘極260具有側壁和橫向定位且緊緊相鄰於該些側壁的犧牲性閘極側壁間隔件240以及頂面和與頂面緊緊相鄰的犧牲性閘極蓋263。
對於每個FET，具有塞蓋249之金屬栓塞248也能形成於源極/汲極區域212(或如果適用的話，在凸起磊晶源極/汲極區域213上)，使得每個金屬栓塞248被橫向定位且緊緊相鄰於至少一個犧牲性閘極側壁間隔件240(見第9A-9B和10A-10C圖)。為了形成具有塞蓋249的金屬栓塞248，金屬栓塞開口能在穿過ILD層250被形成(例如。光蝕刻圖案化和蝕刻)到源極/汲極區域212(或如果適用的話，至凸起磊晶源極/汲極區域213，如圖所示)。然後，金屬栓塞248能被形成於金屬栓塞開口中。也就是說，金屬(例如，鎢、鈷、鋁或任何其它合適的金屬栓塞材料)可以沉積到金屬栓塞開口中，而可以執行CMP製程以在ILD層250的頂面上方移除金屬(見第9A-9B圖)。此外，可以執行蝕刻製程以使金屬栓塞凹陷(例如，在ILD層250中形成在每個金屬栓塞248上方對準的凹槽)。應當注意的是，可以執行這個蝕刻製程，使得金屬栓塞248的頂面相等於、低於、或高於相鄰替代金屬閘極的頂面。然後，另一個介電質蓋層能被沉積和被平坦化，以便在每個金屬栓塞248上方的凹槽內形成塞蓋249。塞蓋249能具體地由與第二犧牲性閘極蓋263和犧牲性閘極側壁間隔件240不同的材料製成。舉例而言，塞蓋249能由與ILD層250相同的介電質材料(例如，氧化矽)製成。
隨後，如上所述，第二犧牲性閘極蓋263和犧牲性閘極側壁間隔件240能由從每個閘極260選擇性蝕刻掉的相同介電質材料(例如，氮化矽)製成(104，見第11圖)。對第二犧牲性閘極蓋263和犧牲性閘極側壁間隔件240的蝕刻在閘極260周圍產生空穴265。空穴265將具有下部部分2651和上部部分2652。下部部分2651將曝露閘極260的側壁和閘極260相對側上的相鄰金屬栓塞248。上部部分2652將位於下部部分2651和閘極260的上方，而因此將會曝露在相鄰金屬栓塞248上之塞蓋249的側壁。應當注意的是，從每個閘極260所蝕刻掉的第二犧牲性閘極蓋263和犧牲性閘極側壁間隔件240的流程104能被定時，使得其在曝露半導體本體210的頂面之前停止(以及如果適用的話，凸起磊晶源極/汲極區域213)。因此，如圖所示，犧牲性閘極側壁間隔件240的區段241能保持在與閘極260緊緊相鄰之半導體本體210的頂面上。
在空穴被形成在圍繞在每個閘極260以後，第一介電質層270能被沉積於該ILD層250、塞蓋249之上，並進入每個空穴265(106，見第12圖)。第一介電質層270能被沉積以在每個空穴之下部部分2651中產生氣隙271，使得第一介電質層270與每個空穴265的上部部分2652對齊。舉例而言，原子層沉積(ALD)製程能被調整，使得所得到的該第一介電質層270為半共形的，因為它對齊每個空穴的上部部分2652，但僅部分地對齊下部部分2651，在空穴的下部部分2651被對齊或被填補前，在閘極260與相鄰金屬栓塞248之間的狹小空間的頂部夾斷。結果，氣隙271(也稱為空隙)在閘極260的側壁和相鄰金屬栓塞248之間的空穴265的下部部分2651內形成。在已提供的例子中沉積製程本身被定制以確保該已沉積的第一介電質層夾斷，從而在空穴265的下部部分中形成所需的氣隙271。
然而，應當理解的是，在第一介電質層270的沉積期間，其它流程能可代替地被用於確保氣隙271在空穴265之下部部分2651中形成。舉例而言，雖然未示出，T形替代金屬閘極能在最初被形成以在T形閘極之寬頂部和相鄰金屬栓塞之間提供非常狹小的空間。於是，當第一介電質層被沉積，會發生夾斷，導致下部部分2651中形成氣隙271。在這種情況下，將執行額外蝕刻流程以移除T形閘極的寬頂部，而第一介電質層將重新沉積以便對齊空 穴265之上部部分2652。
在任何情況下，第一介電質層270能具體地為與用於塞蓋249之不同的介電質。舉例而言，第一介電質層270能由碳氧化矽製成。
接下來，第二介電質層275能被沉積在第一介電質層270上，以填補每個空穴265的上部部分2652(108，見第13圖)。或者，第二介電質層275能由與之前使用於犧牲性閘極側壁間隔件240的相同介電質材料製成。舉例而言，第二介電質層275能由氮化矽製成。在任何情況下，第二介電質層275能由不同於第一介電質層270和塞蓋249的介電質材料製成。也就是說，第一介電質層270、第二介電質層275和塞蓋249能由三種不同的介電質層材料製成(例如分別為碳氧化矽、氮化矽、以及氧化矽)。在第二介電質層275被沉積之後，第二介電質層275和第一介電質層270能從塞蓋249和ILD層250上方被移除(例如，使用化學機械拋光(CMP)製程)(110)。
然後，另一個ILD層290可以形成(例如，沉積)在ILD層250與塞蓋249的實質共平面頂面上，並與其緊緊相鄰，以及進一步在每個空穴265上橫向地延伸，以便在對齊空穴的上部部分之第一介電質層270的上方，並與其緊緊相鄰。而第二介電質層275，其在第一介電質層270上，並填補空穴的上部部分(112，見第14圖)。ILD層290能由相同於ILD層250和塞蓋249的介電質材料製成(例如，氧化矽)。
隨後，可以形成中段製程(MOL)接點，其垂直地延伸穿過ILD層290而向下至每個FET之金屬栓塞248與閘極260(114)。用於形成這種MOL接點的流程步驟在以下詳細描述，並在第15-22圖中繪出。應該注意的是，由於空間限制和臨界尺寸，通常給定FET之閘極的閘極接點和相同FET之金屬栓塞的源極/汲極接點將不會沿著半導體本體的長度完全對準(即圖中所示之沿著橫截面Z-Z’)。因此，為了說明之用意及避免混雜，圖中僅示出兩個接點開口和對應接點的形成包括，第一FET201之閘極的閘極接點開口和閘極接點，以及第二finFET202之其中一個金屬栓塞的源極/汲極接點開口和源極/汲極接點。然而，應當理解的是，每個finFET 201-202的其它MOL接點也將同時形成於所示的橫截面Z-Z’之外側。
為了在流程114形成MOL接點，第一遮罩層281(例如，第一光學聚合層(OPL))能被形成於ILD層290之上(115)。第一遮罩層281能與源極/汲極接點開口291進行光蝕刻圖案化，其垂直延伸穿過第一遮罩層281至ILD層290並且在塞蓋249上方對齊(116，見第15圖)。接下來，源極/汲極接點開口291能延伸穿過ILD層290與塞蓋249至下面的金屬栓塞248(117，見第16圖)。由於ILD層290和塞蓋249的介電質材料相同(例如，氧化矽)以及由於這介電質材料與第一介電質層270和第二介電質層275不同(例如分別為碳氧化矽和氮化矽)，其對齊/填補每個閘極260上的空穴，延伸源極/汲極接點開口291的 製程能是對第一介電質層270和第二介電質層275材料有選擇性的非等向性蝕刻製程。舉例而言，這種非等向性蝕刻流程能是常規氧化矽非等向性蝕刻，其選擇性蝕刻在碳氧化矽第一介電質層270和氮化矽第二介電質層275上方的氧化矽ILD層290和氧化矽塞蓋249(即以比碳氧化矽或氮化矽更快的速度蝕刻氧化矽)，以不(或僅最低性)蝕刻該第一和該第二介電質層270、275的方式，曝露通過ILD氧化物和氧化塞蓋249之金屬栓塞248的頂部，從而確保閘極260保持未曝露。因此，由於在系統中曝露的不同材料之間的現有蝕刻選擇性，這種蝕刻將會以自我對準的方式進行，使得這種製程比起諸如光蝕刻重疊控制等製程變化性更強健。
一旦源極/汲極接點開口291被延伸到金屬栓塞248，第一遮罩層281能被選擇性移除(118)，而第二遮罩層282(例如，第二OPL)能被形成於ILD層290上(119，見第17圖)。這第二遮罩層282能與根據該方法形成之每個FET的每個閘極的至少一個閘極接點開口293進行光蝕刻圖案化(120，見第18圖)。具體而言，閘極接點開口293能垂直延伸穿過第二遮罩層282至ILD層290，並且能在閘極260上被對準。
然後能執行多個選擇性蝕刻製程以延伸閘極接點開口293至下面的閘極260。具體而言，閘極接點開口293能延伸穿過ILD層290，並停在下面的第二介電質層275上方(121，見第19圖)。由於ILD層290之介電質 材料(例如，氧化矽)不同於閘極260上方的第一介電質層270和第二介電質層275的介電質材料(例如分別為碳氧化矽和氮化矽)，所以延伸閘極接點開口293至下面的第二介電質層275之流程可以是對第一介電質層270和第二介電質層275的材料有選擇性的非等向性蝕刻製程。例如，這蝕刻製程可以是用於蝕刻源極/汲極接點開口291之相同的常規氧化矽非等向性蝕刻製程，如上所述。最理想的是，當第二介電質層275的頂面被曝露時，流程121的蝕刻將會停止。然而，由於塞蓋249和ILD層290由相同材料製成，所以在與第一介電質層270之上角緊緊相鄰的塞蓋249中可能形成凹陷。因此，塞蓋249之高度和流程121中蝕刻的時間應該預先確定，以確保有足夠的幅度讓金屬栓塞248不被曝露。
每個閘極接點開口293能進一步延伸穿過第二介電質層275之已曝露部分，在下面的第一介電質層270之水平部分上停止(122，見第20圖)。由於第二介電質層275之介電質材料(例如，氮化矽)不同於第一介電質層270和塞蓋249之介電質材料(例如分別為碳氧化矽和氧化矽)，延伸閘極接點開口293至下面的第一介電質層270的水平部分之製程可以是對第一介電質層270和塞蓋249的材料有選擇性的非等向性蝕刻製程。舉例而言，這非等向性蝕刻製程能是常規氮化矽非等向性蝕刻，其選擇性蝕刻在碳氧化矽第一介電質層270和氧化矽塞蓋249上方的氮化矽第二介電質層275(即以比碳氧化矽或氧化矽更快 的速度蝕刻氮化矽)，以移除第二介電質層275。
每個閘極接點開口293能進一步延伸穿過第一介電質層270之水平部分的已曝露部分，在下面的閘極260上停止(123，見第21圖)。由於第一介電質層270之介電質材料(例如，碳氧化矽)不同於塞蓋249之介電質材料(例如，氧化矽)，延伸閘極接點開口293至下面的閘極260之製程能是對塞蓋249的材料有選擇性的非等向性蝕刻製程。舉例而言，這非等向性蝕刻製程能是常規碳氧化矽非等向性蝕刻，其選擇性蝕刻在氧化矽塞蓋249和閘極260之材料上方的碳氧化矽第一介電質層270(即以比氧化矽或閘極材料更快的速度蝕刻碳氧化矽)，以不(或僅最低性)蝕刻塞蓋249的方式從閘極260頂部移除第一介電質層270，從而曝露閘極260而不曝露任何相鄰的金屬栓塞248。
另外，由於用於將閘極接點開口293延伸至下面閘極260的蝕刻製程本質上為非等向性的，它將從每個閘極之頂面上移除第一介電質層270之水平部分的已曝露部分，但將完整地留下第一介電質層270之垂直部分，該垂直部分橫向定位於與塞蓋249相鄰並且位於氣隙271上方。結果，對於每個閘極，將產生具有下氣隙段277和上實心段278的介電質間隔件276(即間隔件)。介電質間隔件276之下氣隙段277將包含氣隙277，並將橫向定位於閘極260的側壁和閘極260相對側之相鄰金屬栓塞248之間。介電質間隔件276之上實心段278將實質上是實心 的，將位於下氣隙段277上方並將橫向定位於與相鄰金屬栓塞248上之塞蓋249的側壁緊緊相鄰。因此，由於在系統中曝露的不同材料之間的現有蝕刻選擇性，所以與用於形成源極/汲極接點開口蝕刻製程一樣，用於延伸閘極接點開口293至下面的閘極260的多選擇性蝕刻製程將以自我對準方式執行，使得這種製程比起諸如光蝕刻重疊控制等製程變化性更強健。
然後可以選擇性移除第二遮罩層282(124)而金屬能沉積以填補源極/汲極和閘極接點開口291和293，從而分別形成源極/汲極和閘極接點294和295(125，見第22圖)。在流程122沉積的金屬能例如是銅、鎢、鋁、鈷、或任何適於MOL接點形成的其它金屬材料。用於沉積各種金屬材料以填補接點開口的技術在所屬技術領域中眾所周知，因此這些細節會從說明書中省略以讓讀者能夠集中在所揭示方法的顯著態樣上。
應當注意的是，作為用於ILD層290和塞蓋249(例如，氧化矽)、用於第二介電質層275(例如，氮化矽)以及用於第一介電質層270(即碳氧化矽)的三種不同介電質材料的結果，能執行上述之選擇性蝕刻製程118，使得源極/汲極接點開口291與金屬栓塞248自我對準。也就是說，即使源極/汲極接點開口291寬於金屬栓塞和/或偏位，每個源極/汲極接點開口291將落在金屬栓塞248上，而稍微有或沒有曝露相鄰閘極260的風險，以與閘極重疊。因此，所揭示之方法避免了源極/汲極接點294 與相鄰閘極260的短路。
類似地，由於用於ILD層290和塞蓋249(例如，氧化矽)、用於第二介電質層275(例如，氮化矽)以及用於第一介電質層270(例如，碳氧化矽)之三種不同的介電質材料，能執行上述之選擇性蝕刻製程121-123，使得每個閘極接點開口293被自我對準至閘極260。也就是說，即使在閘極接點開口293寬於閘極和/或偏移的情況下，每個閘極接點開口293將稍微有或沒有曝露相鄰金屬栓塞248的風險而降落在閘極260上，以便重疊相鄰金屬栓塞。因此，閘極接點開口293以及形成在那閘極接點開口293的閘極接點295能具有被介電質間隔件276之上實心段278橫向包圍的狹小部分，以及在狹小部分上方和在介電質間隔件276之上實心段278橫向延伸的更寬部分(例如，延伸到塞蓋249上)。因此，本揭示之方法避免了將閘極接點295與相鄰金屬栓塞248短路。所以，視需要地，閘極接點開口293以及(更具體而言，)閘極接點開口中的閘極接點295能被形成於FET之主動區域上方(例如，如第21和22圖所示在通道區域211的正上方)或其附近以最小化裝置尺寸而不會有短路到相鄰金屬栓塞之風險。
參照第22圖，也在這裡揭示了根據上述方法形成的積體電路(IC)結構，以具有一個或多個具有氣隙閘極側壁間隔件之電晶體，以及視需要的在主動區域(例如，CBoA)上或其附近的閘極接點。為了說明之用意，本文揭示的IC結構會在下文中被描述，並在附圖中示出關於 兩個非平面FET(即，第一finFET 201和第二finFET 202)，其共享單個半導體本體(例如，半導體鰭片)，並且具有相同類型的導電性。然而，應當理解的是，所示之FET的數量和類型不止在限制性。舉例而言，視需要地，這種IC結構可以包括多鰭片鰭式FET、平面FET、不同類型導電性之FET等。
在任何情況下，本文所揭示的每個IC結構200能併入至少一個電晶體(例如，見第一電晶體201和第二電晶體202)。
每個電晶體201、202能具有半導體本體210(例如，半導體鰭片，如矽鰭片)，並且在該半導體本體210內，通道區域211橫向定位於源極/汲極區域212之間。該通道區域211能例如摻雜有第一摻雜劑，以便在相對低導電性之水平上具有第一類型導電性。該源極/汲極區域212能例如摻雜有第二摻雜劑，以便在相對高導電性之水平上具有第二類型導電性。視需要地，磊晶半導體材料(例如，磊晶矽或任何其它合適之磊晶半導體材料)能在源極/汲極區域212上生長，從而形成凸起磊晶源極/汲極區域213(如圖所示)。該磊晶半導體材料能被原位摻雜或隨後被注入，使得凸起磊晶源極/汲極區域213在相對高導電性水平上具有第二類型導電性。視需要地，半導體本體210能被凹陷在源極/汲極區域212處(例如，半導體本體210能具有已凹陷源極/汲極區域212)且磊晶源極/汲極區域213能位在該已凹陷源極/汲極區域上(未示出)。
每個電晶體201、202還能具有閘極260，其在通道區域211上相鄰於半導體本體210。閘極260能為替代金屬閘極。舉例而言，該閘極260能包括共形高K閘極介電質層261以及在該閘極介電質層261上的一個或多個金屬層262。那些所屬技術領域具有技術者將會意識到用於替代金屬閘極之介電質和金屬層的材料與厚度能被預選以在給定FET導電性類型的情況下達成想要的功函數。或者，該閘極260能為具有例如二氧化矽閘極介電質層和多晶矽摻雜閘極導電層之常規的閘極先製(gate-first)閘極。
每個電晶體201、202還能具有在該源極/汲極區域212上的金屬栓塞248(或，如果可以適用的話，在凸起磊晶源極/汲極區域213)以及在金屬栓塞248上方並與其緊緊相鄰之塞蓋249。該金屬栓塞248能由例如鎢、鈷、鋁或任何其它合適之金屬栓塞材料製成。該塞蓋能為由例如氧化矽所製成的介電質塞蓋。
每個電晶體201、202還能具有中段製程(MOL)接點。具體而言，每個電晶體201、202能包括源極/汲極接點294，其垂直延伸穿過層間介電質(ILD)層290(例如，氧化矽ILD層)進一步向下到金屬栓塞248以及閘極接點295，其垂直延伸穿過該ILD層290進一步向下到該閘極260。應當注意的是，由於空間限制和臨界尺寸，通常給定FET之閘極接點295到閘極260以及相同FET之源極/汲極接點294到金屬栓塞248將不會沿著半導體本體210之長度完全地被對準(即，沿著第22圖所示的橫截面 Z-Z’)。因此，為了說明之用意，第22圖中僅示出了兩個MOL接點：第一電晶體201之閘極接點295到閘極260以及第二電晶體202之源極/汲極接點294到其中一個金屬栓塞248。然而，應當理解的是，該IC結構200還將包括所示橫截面Z-Z’之外的每個電晶體201-202之其它MOL接點。
每個電晶體201、202還能具有介電質間隔件276，其具有下氣隙段277和上實心段278。該下氣隙段277和上實心段能分別由相同之介電質材料製成，其介電質材料不同於塞蓋249的。舉例而言，該下氣隙段277和該上實心段能分別由碳氧化矽製成。該下氣隙段277能包含在該介電質材料內(例如，碳氧化矽內)之氣隙271，並且可以被橫向定位且緊緊相鄰於閘極260之側壁和閘極260之相對側的相鄰金屬栓塞248之間。該上實心段278能位於該下氣隙段277上方並且橫向定位且緊緊相鄰於閘極接點295與金屬栓塞248之相鄰塞蓋249之間。視需要地，該介電質間隔件276能具有在半導體本體210和該下氣隙段277之間的附加區段241。這個介電質間隔件276之附加區段241能由不同於上方區段和不同於該塞蓋249之介電質材料製成。舉例而言，介電質間隔件276之該附加區段241能由氮化矽製成，並且尤其能在製成期間從閘極260蝕刻掉之氮化矽犧牲性閘極側壁間隔件240的殘留部分，如上方有關於該等方法所詳細討論過的。
因此，在IC結構200中，介電質間隔件276 之上實心段278和下氣隙段277、視需要的介電質間隔件276之附加區段241、以及塞蓋249與ILD層290能由三種不同的介電質材料製成(例如，分別為碳氧化矽、氮化矽及氧化矽)。
應當注意的是，由於在製程期間使用不同的介電質材料(參見以上關於該等方法的詳細討論)，即使用於那源極/汲極接點之源極/汲極接點開口被圖案化為比金屬栓塞更寬和/或金屬栓塞之偏移，每個源極/汲極接點294將會降落在金屬栓塞248上，而介電質間隔件276之上實心段278將會防止源極/汲極接點294至相鄰閘極260的短路，以便重疊該閘極。類似地，由於在製程期間使用不同的介電質材料(參見以上關於該等方法的詳細討論)，即使在那閘極接點之閘極接點開口被圖案化為比該閘極更寬和/或偏移，每個閘極接點295將會降落在閘極上，而該介電質間隔件276之上實心段278和塞蓋249將會防止該閘極接點295到相鄰金屬栓塞248的短路，以便重疊相鄰金屬栓塞。因此，如圖所示，該閘極接點295能具有狹小部分，其被該介電質間隔件276之上實心段278橫向包圍，以及更寬部分，其在狹小部分上方，其在該介電質間隔件276之上實心段278上橫向地延伸(例如，到該塞蓋429上)而不會短路到該下方的金屬栓塞248。因此，該閘極接點295能選擇性地降落在該FET主動區域的上方(例如，如第22圖所示的在該通道區域211的正上方)或與其靠近，以最小化裝置尺寸而不會有短路到相鄰金屬栓塞的風險。
在上述方法和結構中，該電晶體201、202能為N型或P型場效電晶體。對於N型FET，該通道區域之第一類型導電性能為P型導電性而該源極/汲極區域之第二類型導電性能為N型導電性；而對於P型FET，該通道區域之第一類型導電性能為N型導電性而該源極/汲極區域之該第二類型導電性能為P型導電性。那些所屬領域中具有技術者將會意識到不同摻雜劑能用來達成不同導電性類型，而該摻雜劑能根據所使用之不同的半導體材料而改變。舉例而言，一種具有N型導電性之矽基半導體材料通常摻雜有N型摻雜劑(例如，第5族摻雜劑，如砷(As)、磷(P)或銻(Sb))，而一種具有P型導電性之矽基半導體材料通常摻雜有P型摻雜劑(例如，第3族摻雜劑，如硼(B)或銦(In))。或者，一種具有P型導電性之氮化鎵(GaN)基半導體材料通常摻雜有鎂(Mg)，而具有N型導電性之氮化鎵(GaN)基半導體材料通常摻雜有矽(Si)。那些所屬技術領域中具有技術者也將會意識到不同的導電性水平將取決於摻雜劑的相對濃度程度。
上文所描述之方法是使用於積體電路晶片之製造。所得到的積體電路晶片能由製造者以原始晶圓形式(意即，作為具有多個未封裝晶片之單一晶圓)、作為裸晶粒、或以封裝形式而銷售。在後者的例子中，晶片是安裝在單一晶片封裝中(諸如塑膠載板，具有固定至主機板或其它較高位階的載板之導線)或在多重晶片封裝中(諸如具有表面互連線或埋入式互連線之任一個或兩者之陶瓷載 板)。在任何例子中，晶片是與其它晶片、離散電路元件及/或其它訊號處理裝置整合成為下列任一者之一部分：(a)中間產品，諸如主機板或(b)終端產品。終端產品可以是包含積體電路晶片的任何產品，範圍從玩具及其它低端應用至具有顯示器、鍵盤或其它輸入裝置、以及中央處理器之先進的電腦產品。
應該理解的是，本文所使用的術語為說明本揭示方法和結構之用途，而不旨在限制。舉例而言，如本文中所用的，單數形式“一”、“一種”、“一個”、以及“該”也旨在包括該複數形式，除非上下文另有所指。另外，如本文中所用的，術語“包含”和/或“包括”註明所述特徵、整數、步驟、操作、元素和/或構件的存在，但不排除存在或附加一個或多個其它特徵、整數、步驟、操作、元素、構件和/或其組合。此外，如本文中所用的，諸如“右”、“左”、“垂直的”、“水平的”、“頂部”、“底部”、“上部”、“下部”、“下面”、“底下”、“下伏的”、“上方”、“重疊”、“平行”、“垂直”等術語旨在描述如它們在圖中被定向和示出的相對位置(除非另有說明)。舉例而言，元件的低層或下部部分將會被定為比該相同元件之高層或更高部分更靠近於該基板的實質平面底面；水平表面將會實質平行於該基板的平面底面以及垂直表面將會實質垂直於該基板的平面底面等。如本文所使用的，諸如“碰觸”、“在”、“直接接觸”、“靠合”、“直接相鄰於”、“緊緊相鄰於”等術語旨在 表示至少一個元件物理接觸另一個元件(沒有其它元件分離所述元件)。此外，如本文所使用的，片語“橫向定位且相鄰於”和“橫向定位且緊緊相鄰於”是指一個元件被定為於另一個元件的側面(即，位於另一個元件的一側)，而不是定位於該其它元件的上方或下方，那些元件在附圖中被定向和示出。在以下所附的申請專利範圍對應之結構、材料、動作以及相同之所有手段或步驟加上功能元件旨在包括任何結構、材料、或執行與其它特別保護之被保護元件組合功能的動作。
已提出本說明內容之各種具體實施例的說明是為了圖解說明而非旨在窮盡或限定所揭示的具體實施例。本技藝一般技術人員明白在不脫離所揭示具體實施例的精神及範疇下仍有許多修改及變體。選擇使用於本文的術語以最佳地解釋該等具體實施例的原理，實際應用或優於出現於市上之技術的技術改善，或致能其他本技藝一般技術人員了解揭示於本文的具體實施例。

Claims (20)

  1. 一種形成積體電路結構之方法，該方法包含：在通道區域形成與半導體本體相鄰的閘極，該通道區域橫向定位於源極/汲極區域，而該閘極具有犧牲性閘極蓋與犧牲性閘極側壁間隔件；在源極/汲極區域上形成具有塞蓋之金屬栓塞，並橫向定位且緊緊相鄰於該犧牲性閘極側壁間隔件；蝕刻該犧牲性閘極蓋與該犧牲性閘極側壁間隔件以創造具有下部部分及上部部分之空穴，該空穴之該下部部分曝露在該閘極之側壁和該金屬栓塞，而該空穴之該上部部分位於該空穴之該下部部分上方及曝露該閘極；共形沉積第一介電質層進入該空穴，使得氣隙建立在該閘極之該側壁和該金屬栓塞之間的該空穴之該下部部分中以及使得該第一介電質層對齊該空穴之該上部部分；在該第一介電質層之該共形沉積之後，於該第一介電質層上沉積第二介電質層以填補該空穴；以及從該塞蓋上方移除該第一介電質層和該第二介電質層。
  2. 如申請專利範圍第1項所述之方法，該犧牲性閘極蓋和該犧牲性閘極側壁間隔件之蝕刻在曝露該半導體本體之頂面之前停止。
  3. 如申請專利範圍第1項所述之方法，該閘極包含替代金屬閘極，而該犧性性閘極蓋與該犧牲性閘極側壁間隔件包含氮化矽。
  4. 如申請專利範圍第1項所述之方法，其中，該第一介電質層、該第二介電質層以及該塞蓋包含三種不同介電質材料。
  5. 如申請專利範圍第4項所述之方法，該第一介電質層包含碳氧化矽、該第二介電質層包含氮化矽、以及該塞蓋包含氧化矽。
  6. 如申請專利範圍第4項所述之方法，還包含：在該塞蓋上方形成層間介電質層，與其緊緊相鄰，並在該空穴上方進一步橫向延伸；以及形成閘極接點，包含：形成閘極接點開口，其在該閘極上方對準並延伸穿過該層間介電質層至該第二介電質層；延伸該閘極接點開口穿過該第二介電質層到該第一介電質層；延伸該閘極接點開口穿過該第一介電質層到該閘極，穿過該第一介電質的該閘極接點開口之延伸包含執行選擇性非等向性蝕刻製程，其從該閘極之頂面移除該第一介電質層之水平部分，並在該氣隙上方完整地留下該第一介電質層的垂直區段，以創造一種包含下氣隙段和在該下氣隙段上方之上實心段的介電質間隔件；以及以金屬填補該閘極接點開口以形成該閘極接點。
  7. 如申請專利範圍第6項所述之方法，該閘極接點的形成包含形成該閘極接點落在與主動區域相鄰之該閘極上。
  8. 一種形成積體電路結構之方法，該方法包含：在通道區域形成相鄰於半導體本體的閘極，每個通道區域橫向定位於源極/汲極區域之間，而每個閘極具有犧牲性閘極蓋和犧牲性閘極側壁間隔件；在該源極/汲極區域上形成金屬栓塞，每個金屬栓塞被橫向定位且緊緊相鄰於至少一個犧性性閘極側壁間隔件；蝕刻該金屬栓塞以在該金屬栓塞上方形成凹槽；在該凹槽中形成塞蓋；從每個該閘極選擇性蝕刻掉該犧牲性閘極蓋和該犧牲性閘極側壁間隔件以創造空穴，每個空穴具有下部部分和上部部分，該下部部分曝露在閘極之側壁與相鄰該金屬栓塞，而該上部部分位於該下部部分與該閘極上方；沉積第一介電質層進入該等空穴，使得在每個空穴中，氣隙被創造於該下部部分中，並且使得該第一介電質層對齊該上部部分；沉積第二介電質層在該第一介電質層上的該等空穴內以填補該等空穴、該等塞蓋，該第一介電質層和該第二介電質層包含三種不同的介電質材料；從該等塞蓋上方移除該第一介電質層和該第二介電質層；在該等塞蓋上方形成層間介電質層，與其緊緊相鄰，並進一步橫向延伸於該等空穴上方；以及形成接點通過該層間介電質層至至少一個閘極以及至少一個金屬栓塞。
  9. 如申請專利範圍第8項所述之方法，該犧牲性閘極蓋和該犧牲性閘極側壁間隔件之選擇性蝕刻在曝露該半導體本體之頂面前停止。
  10. 如申請專利範圍第8項所述之方法，該閘極包含替代金屬閘極以及該犧牲性閘極蓋與該犧牲性閘極側壁間隔件包含氮化矽。
  11. 如申請專利範圍第8項所述之方法，該第一介電質層包含碳氧化矽、該第二介電質層包含氮化矽、以及該塞蓋包含氧化矽。
  12. 如申請專利範圍第8項所述之方法，該等接點的形成包含：形成在金屬栓塞上之塞蓋上方對準的源極/汲極接點開口；延伸該源極/汲極接點開口至該金屬栓塞；在該層間介電質層上形成遮罩層，該遮罩層填補該源極/汲極接點開口，並與閘極上方所對準之閘極接點開口被圖案化；延伸該閘極接點開口穿過該層間介電質層至該第二介電質層；延伸該閘極接點開口穿過該第二介電質層至該第一介電質層；延伸該閘極接點開口穿過該第一介電質層至該閘極，該閘極接點開口之穿過該第一介電質層的延伸包含執行選擇性非等向性蝕刻製程，其從該閘極頂面移除該第一介電質層之水平區段，並在該氣隙上方完整地留下該第一介電質層之垂直區段，以創造包含下氣隙段和在該下氣隙段上方之上實心段的介電質間隔件；以及以金屬填補該源極/汲極接點開口與該閘極接點開口以形成源極/汲極接點和閘極接點。
  13. 如申請專利範圍第12項所述之方法，該閘極接點開口降落在與主動區域相鄰之該閘極。
  14. 一種積體電路結構，包含：閘極，其在通道區域相鄰於半導體本體，且該通道區域橫向定位於源極/汲極區域之間；閘極接點，其在該閘極上方且與其緊緊相鄰；複數金屬栓塞，其在該源極/汲極區域上；複數塞蓋，其在該金屬栓塞上方且與其緊緊相鄰；以及介電質間隔件，包含：下氣隙段，其橫向定位於該閘極和該等金屬栓塞之間；上實心段，其橫向定位於該閘極接點和該等塞蓋之間；以及附加區段，在該半導體本體與該下氣隙段之間。
  15. 如申請專利範圍第14項所述之積體電路結構，該上實心段和該下氣隙段包含一種介電質材料，其中，該下氣隙段還包含在該介電質材料內的空隙。
  16. 如申請專利範圍第14項所述之積體電路結構，其中，該附加區段和該上實心段包含兩種不同的介電質材料。
  17. 如申請專利範圍第14項所述之積體電路結構，該塞蓋，該介電質間隔件之上實心段和該介電質間隔件之附加區段分別包含三種不同的介電質材料。
  18. 如申請專利範圍第14項所述之積體電路結構，該介電質間隔件之該上實心段包含碳氧化矽、該介電質間隔件之附加區段包含氮化矽以及該塞蓋包含氧化矽。
  19. 如申請專利範圍第14項所述之積體電路結構，該閘極接點還包含被該介電質間隔件之該上實心段橫向包圍的狹小部分和在狹小部分上方的更寬部分，該更寬部分橫向延伸於該上實心段上。
  20. 如申請專利範圍第14項所述之積體電路結構，該閘極包含替代金屬閘極，並且該閘極上之該閘極接點與主動區域相鄰。
TW106119240A 2017-01-18 2017-06-09 氣隙閘極側壁間隔件及方法 TWI677053B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/408,540 2017-01-18
US15/408,540 US10026824B1 (en) 2017-01-18 2017-01-18 Air-gap gate sidewall spacer and method

Publications (2)

Publication Number Publication Date
TW201841303A TW201841303A (zh) 2018-11-16
TWI677053B true TWI677053B (zh) 2019-11-11

Family

ID=62837331

Family Applications (1)

Application Number Title Priority Date Filing Date
TW106119240A TWI677053B (zh) 2017-01-18 2017-06-09 氣隙閘極側壁間隔件及方法

Country Status (3)

Country Link
US (2) US10026824B1 (zh)
CN (2) CN108336015B (zh)
TW (1) TWI677053B (zh)

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9190496B2 (en) * 2014-01-23 2015-11-17 Taiwan Semiconductor Manufacturing Company, Ltd. Method of making a FinFET device
US10998228B2 (en) * 2014-06-12 2021-05-04 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned interconnect with protection layer
CN108573926B (zh) * 2017-03-09 2020-01-21 联华电子股份有限公司 半导体存储装置以及其制作方法
US10522392B2 (en) * 2017-05-31 2019-12-31 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of fabricating the same
CN109216451A (zh) * 2017-07-03 2019-01-15 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US10211092B1 (en) * 2018-01-28 2019-02-19 International Business Machines Corporation Transistor with robust air spacer
US10367076B1 (en) * 2018-01-31 2019-07-30 International Business Machines Corporation Air gap spacer with controlled air gap height
US10388770B1 (en) * 2018-03-19 2019-08-20 Globalfoundries Inc. Gate and source/drain contact structures positioned above an active region of a transistor device
US10608096B2 (en) 2018-06-11 2020-03-31 International Business Machines Corporation Formation of air gap spacers for reducing parasitic capacitance
US11205700B2 (en) * 2018-07-16 2021-12-21 Taiwan Semiconductor Manufacturing Co., Ltd. Air gap spacer and related methods
US10854503B2 (en) 2018-07-16 2020-12-01 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure with air gap and method sealing the air gap
US10700180B2 (en) 2018-07-27 2020-06-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure and manufacturing method thereof
US11195753B2 (en) * 2018-09-18 2021-12-07 International Business Machines Corporation Tiered-profile contact for semiconductor
US10825721B2 (en) * 2018-10-23 2020-11-03 Taiwan Semiconductor Manufacturing Co., Ltd. Insulating cap on contact structure and method for forming the same
US10892338B2 (en) 2018-10-24 2021-01-12 Globalfoundries Inc. Scaled gate contact and source/drain cap
US10957604B2 (en) * 2018-10-31 2021-03-23 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
KR20200066959A (ko) * 2018-12-03 2020-06-11 엘지디스플레이 주식회사 투명표시장치
US10886378B2 (en) 2019-01-02 2021-01-05 Globalfoundries Inc. Method of forming air-gap spacers and gate contact over active region and the resulting device
US10832961B1 (en) 2019-04-22 2020-11-10 International Business Machines Corporation Sacrificial gate spacer regions for gate contacts formed over the active region of a transistor
US11031485B2 (en) 2019-06-04 2021-06-08 International Business Machines Corporation Transistor with airgap spacer
US11152486B2 (en) * 2019-07-15 2021-10-19 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET semiconductor device having source/drain contact(s) separated by airgap spacer(s) from the gate stack(s) to reduce parasitic capacitance
US11038038B2 (en) * 2019-08-13 2021-06-15 Micron Technology, Inc. Transistors and methods of forming transistors
US11011638B2 (en) 2019-08-26 2021-05-18 International Business Machines Corporation Transistor having airgap spacer around gate structure
DE102020114875B4 (de) 2019-08-30 2024-02-22 Taiwan Semiconductor Manufacturing Co., Ltd. Finfet-vorrichtung und verfahren
US11456383B2 (en) 2019-08-30 2022-09-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having a contact plug with an air gap spacer
US11004750B2 (en) 2019-09-16 2021-05-11 International Business Machines Corporation Middle of the line contact formation
US11282920B2 (en) 2019-09-16 2022-03-22 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with air gap on gate structure and method for forming the same
EP3817038A1 (en) 2019-10-29 2021-05-05 Imec VZW A method for producing self-aligned gate and source/drain via connections for contacting a fet transistor
US11189706B2 (en) 2020-02-11 2021-11-30 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET structure with airgap and method of forming the same
US11302802B2 (en) 2020-02-19 2022-04-12 Taiwan Semiconductor Manufacturing Co., Ltd. Parasitic capacitance reduction
US11444018B2 (en) * 2020-02-27 2022-09-13 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device including recessed interconnect structure
US11404537B2 (en) 2020-04-17 2022-08-02 Taiwan Semiconductor Manufacturing Company Limited Semiconductor device with air-void in spacer
CN113809044A (zh) * 2020-06-12 2021-12-17 联华电子股份有限公司 半导体元件
US11349014B2 (en) * 2020-06-30 2022-05-31 Taiwan Semiconductor Manufacturing Co., Ltd. Air spacer and method of forming same
CN114068394B (zh) * 2020-07-31 2024-04-16 中芯国际集成电路制造(上海)有限公司 半导体结构的形成方法
CN113161295B (zh) * 2021-04-07 2022-04-12 长鑫存储技术有限公司 半导体器件及其制备方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9362355B1 (en) * 2015-11-13 2016-06-07 International Business Machines Corporation Nanosheet MOSFET with full-height air-gap spacer

Family Cites Families (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6787469B2 (en) 2001-12-28 2004-09-07 Texas Instruments Incorporated Double pattern and etch of poly with hard mask
US8093651B2 (en) 2005-02-11 2012-01-10 Alpha & Omega Semiconductor Limited MOS device with integrated schottky diode in active region contact trench
US8362547B2 (en) 2005-02-11 2013-01-29 Alpha & Omega Semiconductor Limited MOS device with Schottky barrier controlling layer
US8283723B2 (en) 2005-02-11 2012-10-09 Alpha & Omega Semiconductor Limited MOS device with low injection diode
CN101271860B (zh) * 2007-03-19 2010-09-15 联华电子股份有限公司 自行对准接触窗及其制造方法
US7741663B2 (en) 2008-10-24 2010-06-22 Globalfoundries Inc. Air gap spacer formation
US9142462B2 (en) * 2010-10-21 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit having a contact etch stop layer and method of forming the same
US8390079B2 (en) * 2010-10-28 2013-03-05 International Business Machines Corporation Sealed air gap for semiconductor chip
US20120199886A1 (en) * 2011-02-03 2012-08-09 International Business Machines Corporation Sealed air gap for semiconductor chip
JP6092205B2 (ja) 2011-07-14 2017-03-08 アラーガン、インコーポレイテッドＡｌｌｅｒｇａｎ，Ｉｎｃｏｒｐｏｒａｔｅｄ 性的行為に関連した失禁の治療方法
US8471343B2 (en) * 2011-08-24 2013-06-25 International Bussiness Machines Corporation Parasitic capacitance reduction in MOSFET by airgap ild
US9461143B2 (en) 2012-09-19 2016-10-04 Intel Corporation Gate contact structure over active gate and method to fabricate same
US9190486B2 (en) * 2012-11-20 2015-11-17 Globalfoundries Inc. Integrated circuits and methods for fabricating integrated circuits with reduced parasitic capacitance
KR20140086645A (ko) * 2012-12-28 2014-07-08 에스케이하이닉스 주식회사 자기정렬된 에어갭을 구비한 반도체장치 및 그 제조 방법
CN104105120B (zh) * 2013-04-08 2019-03-12 中兴通讯股份有限公司 一种干扰测量方法、网络侧设备及终端设备
US9390928B2 (en) * 2013-10-22 2016-07-12 Globalfoundries Inc. Anisotropic dielectric material gate spacer for a field effect transistor
US9397004B2 (en) 2014-01-27 2016-07-19 GlobalFoundries, Inc. Methods for fabricating FinFET integrated circuits with simultaneous formation of local contact openings
US9515172B2 (en) * 2014-01-28 2016-12-06 Samsung Electronics Co., Ltd. Semiconductor devices having isolation insulating layers and methods of manufacturing the same
KR102154085B1 (ko) * 2014-02-12 2020-09-09 에스케이하이닉스 주식회사 에어갭을 구비한 반도체장치 및 그 제조 방법
US9305835B2 (en) 2014-02-26 2016-04-05 International Business Machines Corporation Formation of air-gap spacer in transistor
US9252233B2 (en) 2014-03-12 2016-02-02 Taiwan Semiconductor Manufacturing Co., Ltd. Air-gap offset spacer in FinFET structure
US9478636B2 (en) * 2014-05-16 2016-10-25 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming semiconductor device including source/drain contact having height below gate stack
US9515156B2 (en) 2014-10-17 2016-12-06 Lam Research Corporation Air gap spacer integration for improved fin device performance
CN105810565B (zh) * 2014-12-31 2019-07-23 联华电子股份有限公司 形成半导体元件的方法
US9412659B1 (en) * 2015-01-29 2016-08-09 Globalfoundries Inc. Semiconductor structure having source/drain gouging immunity
US9559184B2 (en) * 2015-06-15 2017-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Devices including gate spacer with gap or void and methods of forming the same
US9853110B2 (en) * 2015-10-30 2017-12-26 Globalfoundries Inc. Method of forming a gate contact structure for a semiconductor device
US9536982B1 (en) * 2015-11-03 2017-01-03 International Business Machines Corporation Etch stop for airgap protection
US9368572B1 (en) * 2015-11-21 2016-06-14 International Business Machines Corporation Vertical transistor with air-gap spacer
TWI663729B (zh) * 2016-01-05 2019-06-21 聯華電子股份有限公司 半導體結構及其製造方法
US9608065B1 (en) * 2016-06-03 2017-03-28 International Business Machines Corporation Air gap spacer for metal gates
US9786760B1 (en) * 2016-09-29 2017-10-10 International Business Machines Corporation Air gap and air spacer pinch off
US9941352B1 (en) * 2016-10-05 2018-04-10 International Business Machines Corporation Transistor with improved air spacer

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9362355B1 (en) * 2015-11-13 2016-06-07 International Business Machines Corporation Nanosheet MOSFET with full-height air-gap spacer

Also Published As

Publication number Publication date
CN114843333A (zh) 2022-08-02
CN108336015B (zh) 2022-05-17
US10026824B1 (en) 2018-07-17
US20180240883A1 (en) 2018-08-23
CN108336015A (zh) 2018-07-27
TW201841303A (zh) 2018-11-16
US20180204927A1 (en) 2018-07-19
US10249728B2 (en) 2019-04-02

Similar Documents

Publication Publication Date Title
TWI677053B (zh) 氣隙閘極側壁間隔件及方法
US10971601B2 (en) Replacement metal gate structures
TWI723288B (zh) 半導體裝置及其製造方法
TWI708318B (zh) 具有獨立閘極控制之垂直堆疊互補ｆｅｔ裝置
US10269933B2 (en) Recessing STI to increase Fin height in Fin-first process
US10411010B2 (en) Tall single-fin FIN-type field effect transistor structures and methods
CN103187304B (zh) 制造半导体器件和晶体管的方法
TWI668767B (zh) 具有氣隙閘極側壁間隔件之場效電晶體及方法
KR101637679B1 (ko) Ｆⅰｎｆｅｔ을 형성하기 위한 메커니즘들을 포함하는 반도체 디바이스및 그 형성 방법
KR102480219B1 (ko) 반도체 장치 및 반도체 장치의 제조 방법
US10074564B2 (en) Self-aligned middle of the line (MOL) contacts
US10804403B2 (en) Method of fabricating semiconductor devices
US11616016B2 (en) Semiconductor devices and method of manufacturing the same
TWI749363B (zh) 在閘極與源極/汲極接觸之間具有絕緣層的ｆｉｎｆｅｔ
US10679894B2 (en) Airgap spacers formed in conjunction with a late gate cut
US8928091B2 (en) Field-effect-transistor with self-aligned diffusion contact
US10903331B2 (en) Positioning air-gap spacers in a transistor for improved control of parasitic capacitance
US10008385B1 (en) Enlarged sacrificial gate caps for forming self-aligned contacts
TW202407879A (zh) 半導體裝置及其製造方法
TW202301479A (zh) 穿過金屬閘極切口的鰭對鰭溝槽接點