CN108336015B - 气隙栅极侧壁间隔件及方法 - Google Patents

气隙栅极侧壁间隔件及方法 Download PDF

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CN108336015B
CN108336015B CN201711059486.6A CN201711059486A CN108336015B CN 108336015 B CN108336015 B CN 108336015B CN 201711059486 A CN201711059486 A CN 201711059486A CN 108336015 B CN108336015 B CN 108336015B
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gate
dielectric layer
plug
cavity
cap
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CN108336015A (zh
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丹尼尔·恰尼莫盖姆
恩德·拉伯特
谢瑞龙
拉尔斯·赖柏曼
尼格尔·凯夫
古拉密·波奇
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GlobalFoundries US Inc
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GlobalFoundries US Inc
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Abstract

本发明涉及气隙栅极侧壁间隔件及方法，所揭示为集成电路(IC)结构和其形成方法。在该方法中，在沟道区域上形成具有牺牲性栅极盖和牺牲性栅极侧壁间隔件的栅极。该盖和侧壁间隔件被移除，形成空穴，其具有位于该栅极的侧壁和相邻金属栓塞之间的下部部分以及具有在该下部部分和该栅极上方的上部部分。沉积第一介电质层，在该下部部分中形成气隙并对齐该上部部分。沉积第二介电质层，填补该上部部分。在形成栅极接点开口(视需要在主动区上)期间，该第二介电质层被移除而该第一介电质层被非等向性蚀刻，从而曝露该栅极并产生具有下气隙段和上实心段的介电质间隔件。沉积进入开口内的金属形成该栅极接点。

Description

气隙栅极侧壁间隔件及方法
技术领域
本发明有关于集成电路(IC)结构，更具体而言，关于一种形成IC结构的方法，该方法使用一个或多个具有气隙栅极侧壁的晶体管且视需要地，具有在主动区(CBoA)上方或其附近的栅极接点(CB)。
背景技术
近来，形成集成电路(IC)结构的方法已经被发展到能够形成具有气隙栅极侧壁间隔件的场效应晶体管(FET)了。以这种气隙栅极侧壁间隔件，与具有传统栅极侧壁间隔件的FET相比，寄生电容(例如，在FET源极/漏极区域上的FET栅极与金属栓塞之间的电容)被减少了。此外，形成集成电路(IC)结构的方法已经发展到能够形成在主动区(CBoA)上具有栅极接点的FET以允许区域进行缩放。更具体而言，中段工艺(MOL)接点为将场效应晶体管(FET)连接至后段工艺(BEOL)金属层的接点。这些MOL接点包括至少一个栅极接点(CB)和源极/漏极接点(CAs)。栅极接点通过层间介电质(ILD)材料从第一BEOL金属层(本文称为M0层)中的金属线或通孔垂直延伸到FET的栅极。每个源极/漏极接点通过ILD材料从该第一BEOL金属层中的金属线或通孔垂直延伸到位于FET的源极/漏极区域之上且与其紧紧相邻的金属栓塞(TS)。用于形成这些MOL接点的传统技术固有地包括以下风险：(a)在该栅极接点与金属栓塞之间发生短路，特别是如果该栅极接点位于主动区域上方或其附近；以及(b)在源极/漏极接点与该栅极之间发生短路。然而，在不会引起上述短路风险之下，新技术已经被开发以提供这些MOL接点的形成。不幸的是，目前用于形成具有气隙栅极侧壁间隔件的FET的技术与用于形成在主动区(CBoA)上具有栅极接点的FET的技术不相容。
发明内容
鉴于上述内容，本文所揭示为用于形成具有一个或多个晶体管的集成电路(IC)结构的方法，每个晶体管都具有气隙栅极侧壁间隔件，以及视需要地，在主动区上或其附近的栅极接点(例如，CBoA)。
一般而言，每个方法可以包括形成至少一个晶体管。在形成该晶体管期间，栅极能形成在沟道区域上与半导体本体相邻，其中该沟道区域横向定位在源极/漏极区域之间，而该栅极具有牺牲性栅极盖和牺牲性栅极侧壁间隔件。具有塞盖的金属栓塞能被形成于源极/漏极区域上，以便被横向定位且紧紧相邻于牺牲性栅极侧壁间隔件。随后，牺牲性栅极盖和牺牲性栅极侧壁间隔件能被选择性地从栅极被蚀刻掉，以在该栅极周围形成空穴。这空穴能具有下部部分和上部部分，其中下部部分曝露栅极的侧壁和在该栅极相对侧的金属栓塞，以及其中上部部分位于该下部部分和栅极上方。
在该栅极周围形成空穴之后，第一介电质层能以这样的方式沉积到空穴中，以在空穴的下部部分内形成气隙以及对空穴上部部分进行排列。第二介电质层可能被沉积于第一介电质层上，填补空穴的上部部分。在后续用于栅极接点的栅极接点开口的形成期间，第二介电质层能被移除以及第一介电质层能被非等向性蚀刻，从而产生具有下气隙段和上实心段的介电质间隔件。由于用于金属栓塞上塞盖、第一介电质层及第二介电质层为不同介电质材料，栅极接点开口将会被自动对准到栅极。因此，栅极接点能形成于主动区之上(或靠近其上)，而不具导致相邻金属栓塞短路的风险。
本文揭示的一个特定方法实施例形成具有多个FET的集成电路(IC)结构，每个FET具有气隙栅极侧壁间隔件和视需要地，在主动区上或与其附近的栅极接点(例如，CBoA)。
在这方法实施例中，可以形成多个晶体管。在形成晶体管期间，栅极能形成在沟道区域上与半导体本体相邻，其中每个沟道区域横向定位于源极/漏极区域之间。每个栅极能具体地被形成以致于具有牺牲性栅极盖和牺牲性栅极侧壁间隔件。另外，金属栓塞能被形成于源极/漏极区域上，使得每个金属栓塞横向定位且紧紧相邻于至少一个牺牲性栅极侧壁间隔件。金属栓塞能被回蚀以在金属栓塞上方形成凹槽，并且能在凹槽内形成塞盖。随后，牺牲性栅极盖和牺牲性栅极侧壁间隔件能从每个栅极选择性地被蚀刻掉以在栅极周围形成空穴。每个在各个栅极周围的各个空穴能具有下部部分和上部部分，其中下部部分曝露栅极的侧壁和栅极相对侧的相邻金属栓塞，以及其中上部部分位于下部部分和栅极上方。
在栅极周围形成空穴之后，第一介电质层能沉积到空穴中，使得在每个空穴中，气隙形成于空穴的下部部分中，以及第一介电质层排列于空穴的上部部分。第二介电质层能被沉积到第一介电质层上的空穴中，从而填补每个空穴的上部部分。第一介电质层和第二介电质层之后能从塞盖上方被移除(例如，透过执行化学机械抛光(CMP)工艺)以及层间介电质层能被形成于塞盖之上并与其紧紧相邻，且进一步在空穴中的第一和第二介电质层上横向延伸。
接点能形成通过层间介电质层到至少一个栅极和至少一个金属栓塞。在形成栅极接点开口期间，第二介电质层能被移除和第一介电质层能被非等向性蚀刻，从而产生具有下气隙段和上实心段的介电质间隔件。由于用于塞盖、第一介电质层及第二介电质层为不同介电质材料，所以栅极接点开口将会自动对准到栅极。因此，栅极接点能形成于主动区之上(或其附近)，而不具导致相邻金属栓塞短路的风险。
本文还揭示了根据上述方法形成的集成电路(IC)结构，以便具有一个或多个晶体管，每个晶体管都具有气隙栅极侧壁间隔件以及，视需要地，在主动区(例如，CBoA)上或与其附近的栅极接点。每个IC结构能被并入至少一个晶体管。每个晶体管能在沟道区域上具有与半导体本体相邻的栅极。沟道区域能被横向定位于源极/漏极区域之间。栅极接点能被定位于栅极之上并与其紧紧相邻。金属栓塞能在源极/漏极区域上，而塞盖能在金属栓塞之上并与其紧紧相邻。每个晶体管还能进一步具有介电质间隔件，其具有下气隙段和上实心段。下气隙段能横向定位于栅极与金属栓塞之间，而上实心段能位于下气隙段之上并横向位于栅极接点与塞盖之间。视需要地，介电质间隔件能在半导体本体与下气隙段之间具有附加区段。介电质间隔件的上实心段、介电质间隔件的视需要的附加区段及塞盖能由三种不同介电质材料制成。
附图说明
从以下参照附图的详细说明，本发明将会更好被理解，其附图不一定按比例绘制，其中：
图1为一流程图，其示出了形成具有一个或多个晶体管的集成电路(IC)结构的方法，每个晶体管都具有气隙栅极侧壁间隔件以及视需要地，在主动区(CBoA)上或与其靠近的栅极；
图2A与图2B分别为一俯视图与一剖面图，其示出了根据图1的流程图而形成的部分完成结构；
图3A与图3B分别为一俯视图与一剖面图，其示出了根据图1的流程图而形成的部分完成结构；
图4为一俯视图，其示出了根据图1的流程图而形成的部分完成结构；
图5为一俯视图，其示出了根据图1的流程图而形成的部分完成结构；
图6A与图6B-D分别为一俯视图与剖面图，其示出了根据图1的流程图而形成的部分完成结构；
图7A与图7B分别为一俯视图与一剖面图，其示出了根据图1的流程图而形成的部分完成结构；
图8A与图8B分别为一俯视图与一剖面图，其示出了根据第1图的流程图而形成的部分完成结构；
图9A与图9B-9C分别为一俯视图与剖面图，其示出了根据图1的流程图而形成的部分完成结构；
图10A与图10B-10C分别为一俯视图与剖面图，其示出了根据图1的流程图而形成的部分完成结构；
图11至21为剖面图，其示出了根据图1的流程图而形成的部分完成结构；以及，
图22为一剖面图，其示出了根据图1的流程图而形成的完成结构。
具体实施方式
如上所述，形成集成电路(IC)结构的方法已经发展到能够形成具有气隙栅极侧壁间隔件的场效应晶体管(FET)。以这种气隙栅极侧壁间隔件，与具有传统栅极侧壁间隔件的FET相比，寄生电容(例如，FET栅极与FET源极/漏极区域上金属栓塞之间的电容)能被减少。此外，形成集成电路(IC)结构的方法已经发展到能够在主动区(CBoA)上形成具有栅极接点的FET以允许区域进行缩放。更具体而言，中段工艺(MOL)接点为将场效应晶体管(FET)连接至后段工艺(BEOL)金属层的接点。这些MOL接点包括至少一个栅极接点(CB)和源极/漏极接点(CAs)。该栅极接点通过层间介电质(ILD)材料从第一BEOL金属层(本文称为M0层)中的金属线或通孔垂直延伸到FET的栅极。每个源极/漏极接点通过ILD材料从第一BEOL金属层中的金属线或通孔垂直延伸到位于FET的源极/漏极区域之上并与其紧紧相邻的金属栓塞(TS)。用于形成这些MOL接点的传统技术固有地包括以下风险：(a)在栅极接点与金属栓塞之间发生短路，特别是如果栅极接点位于主动区域上方或其附近；以及(b)在源极/漏极接点与栅极之间发生短路。然而，新技术已经被开发以提供这些MOL接点的形成而不会引起上述短路风险。不幸的是，目前用于形成具有气隙栅极侧壁间隔件的FET的技术与用于形成在主动区(CBoA)上具有栅极接点的FET的技术不相容。
鉴于上述内容，本文揭示了具有一个或多个晶体管的集成电路(IC)结构，其每个晶体管都具有气隙栅极侧壁间隔件且视需要地，在主动区上(例如，CBoA)或其附近的栅极接点。在该方法中，具有牺牲性栅极盖和牺牲性栅极侧壁间隔件的栅极能被形成于沟道区域上，而具有塞盖的金属栓塞能被形成于源极/漏极区域。该牺牲性栅极盖与牺牲性栅极侧壁间隔件能被选择性移除，从而产生具有下部部分和上部部分的空穴，其中下部部分位于栅极的侧壁和栅极相对侧上的相邻的金属栓塞之间，而该上部部分位于下部部分与栅极的上方。可以沉积第一介电质层，在空穴的下部部分内形成气隙并对齐上部部分。可以沉积第二介电质层于第一介电质层上，填补空穴的上部部分。在为栅极接点形成栅极接点开口期间，第二介电质层能被移除而第一介电质层被非等向性蚀刻，从而产生具有横向定位且相邻于栅极的下空隙段和位于下气隙段上方的上实心段的介电质间隔件。由于用于塞盖、第一介电质层及第二介电质层为不同介电质材料，这栅极接点开口被自动对准到栅极。因此，在不具导致相邻金属栓塞短路的风险之下，该栅极接点能被形成于主动区之上(或其附近)。本文还揭示了根据这些方法而形成的IC结构。
参照图1的流程图，一般在本文所揭示的方法中会提供半导体晶片203(101)。在流程101所提供的半导体晶片203能是例如，绝缘层上半导体晶片(例如，硅晶绝缘体(SOI)晶片)，其包括半导体衬底204(例如，硅衬底)、绝缘体层205(例如，埋藏氧化(BOX)层或其它在半导体衬底上合适的绝缘体层)以及在绝缘体层205上的半导体层(例如，硅层或其它合适的半导体层)(见图2A-2B)。或者，可以使用大块半导体晶片(例如，大块硅晶片或其它合适的大块半导体晶片)。
至少一个场效应晶体管(FET)能被形成于半导体晶片203上(102)。为了说明的用意，该方法会在以下做描述并在附图中示出了关于共享单个半导体本体(例如单个半导体鳍片)和具有相同类型导电性的两个非平面FET(例如，鳍式FET)的形成。然而，应当理解的是，根据这些方法而形成的FET数量和类型不限于此。举例而言，视需要地，所揭示的方法可以被用来形成多鳍片鳍式FET、平面FET、具不同类型导电性的FET等等。
在任何情况下，在流程102中，至少一个半导体本体210能被形成。半导体本体210能例如是半导体鳍片(例如，相对薄的矩形或鳍片状半导体本体)。该半导体本体210能被图案化并从SOI晶片的半导体层中(或可替代地，当通过埋藏井区从大块半导体衬底的下部部分隔离时，从大块半导体衬底的上部部分脱开，)被蚀刻。用于形成这种半导体本体的技术(例如，光蚀刻图案化技术或侧壁影像转移技术)在所属技术领域中众所周知，因此这些细节会从说明书中省略以让读者能够集中在所揭示方法的显著态样上。
对于每个FET，该半导体本体210能具有指定区域，其用于源极/漏极区域212和横向地被定位于源极/漏极区域212之间的沟道区域211。为了说明的用意，图2A-2B示出了具有用于第一finFET201的第一沟道区域和用于第二finFET202的第二沟道区域的单一半导体鳍片210，其中第一沟道区域和第二沟道区域被共享源极/漏极区域被隔开。在这种情况下，半导体本体210能在形成之前或之后与第一掺杂剂进行掺杂，使得每个沟道区域211具有在相对低导电性水平的第一类型导电性。或者，每个沟道区域211能保持未掺杂。
对于每个FET，具有牺牲性栅极盖和牺牲性栅极侧壁间隔件的栅极可以形成于与在沟道区域211上半导体本体210相邻。该栅极能使用例如替代金属栅极形成技术而形成。或者，该栅极能使用常规栅极-第一栅极形成技术能被形成。为了说明的用意，以下会描述示例性替代金属栅极形成技术。
具体而言，覆面第一牺牲性层(例如，牺牲性多晶硅层、牺牲性非晶硅层或其它合适的牺牲性层)可以形成于半导体本体210上。不同于第一牺牲性层的第二牺牲性层(例如，牺牲性氮化物层)，可以形成于该第一牺牲性层的顶面上。随后，该第一和第二牺牲性层能被图案化与被蚀刻以形成具有牺牲性栅极盖232的牺牲性栅极231(在此也称为虚拟栅极)，其与每个沟道区域211相邻。就finFET而言，如图3A-3B所示，每个牺牲性栅极231将会被定位在半导体本体210的顶面之上和与其相对侧相邻。接下来，牺牲性栅极侧壁间隔件240能被形成于每个牺牲性栅极231的侧壁上(见图4)。也就是说，相对薄的共形间隔件层(例如，氮化硅层)，能被沉积在部分完成结构之上。然后，可以执行非等向性蚀刻工艺以从水平面和在源极/漏极区域212的半导体本体210的侧壁上移除共形间隔件层。那些所属技术领域具有技术者将会意识到在每个牺牲性栅极231的第一牺牲性栅极盖232的高度应该大约等于或大于半导体本体210的高度，使得共形间隔件层可以从源极/漏极区域212的半导体本体210的侧壁被移除而不曝露牺牲性栅极侧壁。
随后可以执行掺杂剂注入工艺，使得源极/漏极区域212具有例如在相对高导电性水平的第二类型导电性。另外或可替代地，外延半导体材料(例如，外延硅或其它合适的外延半导体材料)能被沉积在半导体本体210的已曝露部分(例如，在源极/漏极区域212上)，以形成凸起外延源极/漏极区域213(见图5)。外延半导体材料能被原位掺杂或随后被注入，使得凸起外延源极/漏极区域213具有相对高导电性水平的第二类型导电性。或者，在沉积外延半导体材料之前，如上所述，源极/漏极区域212能被凹陷(未示出)，从而确保源极/漏极区域212和凸起外延源极/漏极区域213将会被掺杂，以便具有所需的导电性类型和程度。
接下来，层间介电质(ILD)层250可以形成于部分完成结构之上，然后被平坦化(见图6A-6D)。具体而言，覆面ILD层250(例如，覆面氧化硅层或其它合适的覆面ILD层)能被沉积，以覆盖在每个牺牲性栅极231上的第一牺牲性栅极盖232和牺牲性栅极侧壁间隔件240，以及覆盖每个源极/漏极区域212(或凸起外延源极/漏极区域213，如果可以应用的话)。然后可以执行化学机械抛光(CMP)工艺，以便至少曝露每个第一牺牲性栅极盖232的顶部和相邻的牺牲性栅极侧壁间隔件240。
然后第一牺牲性栅极盖232和下面的牺牲性栅极231能被移除，并由具有第二牺牲性栅极盖263的替代金属栅极260来代替(见图7A-7B和8A-8B)。举例而言，每个第一牺牲性栅极盖232和牺牲性栅极231的牺牲性材料能被选择性地使用于牺牲性栅极侧壁间隔件240和ILD层250的介电质材料上被蚀刻(见图7A-7B)。或者，如上所述的CMP工艺能被继续用于曝露每个第一牺牲性栅极盖232的顶部直到每个牺牲性栅极盖232被移除，从而曝露每个牺牲性栅极231的顶部。之后每个牺牲性栅极231能被选择性蚀刻，从而移除每个牺牲性栅极231。在任何情况下，每个第一牺牲性栅极盖232和下面的每个牺牲性栅极231的移除将在每个沟道区域211上的ILD层250内形成栅极开口243，而每个栅极开口243将具有与牺牲性栅极侧壁间隔件240对齐的侧壁。
然后替代金属栅极260可以形成于在沟道区域211上的每个栅极开口243内并与牺牲性栅极侧壁间隔件240紧紧相邻。举例而言，共形高K栅极介电质层261能被沉积以对齐栅极开口，而一个或多个金属层262能被沉积到栅极介电质层261上。那些所属技术领域中具有技术者将会意识到用于替代金属栅极的介电质和金属层的材料和厚度能被预先选定，以实现在给定FET导电性类型下所需的功函数。在任何情况下，可以执行化学机械抛光(CMP)工艺以从ILD层250的顶面上方移除所有栅极材料。然后，替代金属栅极260的材料能被凹陷，使得每个替代金属栅极的顶面低于ILD层250的顶面，而介电质盖层能被沉积与平坦化以在每个替代金属栅极260上形成第二牺牲性栅极盖263(见图8A-8B)。该第二牺牲性栅极盖263能由与牺牲性栅极侧壁间隔件240相同的材料制成。举例而言，第二牺牲性栅极盖263和牺牲性栅极侧壁间隔件240能分别由氮化硅制成。因此，每个替代金属栅极260具有侧壁和横向定位且紧紧相邻于该些侧壁的牺牲性栅极侧壁间隔件240以及顶面和与顶面紧紧相邻的牺牲性栅极盖263。
对于每个FET，具有塞盖249的金属栓塞248也能形成于源极/漏极区域212(或如果适用的话，在凸起外延源极/漏极区域213上)，使得每个金属栓塞248被横向定位且紧紧相邻于至少一个牺牲性栅极侧壁间隔件240(见图9A-9B和10A-10C)。为了形成具有塞盖249的金属栓塞248，金属栓塞开口能在穿过ILD层250被形成(例如。光蚀刻图案化和蚀刻)到源极/漏极区域212(或如果适用的话，至凸起外延源极/漏极区域213，如图所示)。然后，金属栓塞248能被形成于金属栓塞开口中。也就是说，金属(例如，钨、钴、铝或任何其它合适的金属栓塞材料)可以沉积到金属栓塞开口中，而可以执行CMP工艺以在ILD层250的顶面上方移除金属(见图9A-9B)。此外，可以执行蚀刻工艺以使金属栓塞凹陷(例如，在ILD层250中形成在每个金属栓塞248上方对准的凹槽)。应当注意的是，可以执行这个蚀刻工艺，使得金属栓塞248的顶面相等于、低于、或高于相邻替代金属栅极的顶面。然后，另一个介电质盖层能被沉积和被平坦化，以便在每个金属栓塞248上方的凹槽内形成塞盖249。塞盖249能具体地由与第二牺牲性栅极盖263和牺牲性栅极侧壁间隔件240不同的材料制成。举例而言，塞盖249能由与ILD层250相同的介电质材料(例如，氧化硅)制成。
随后，如上所述，第二牺牲性栅极盖263和牺牲性栅极侧壁间隔件240能由从每个栅极260选择性蚀刻掉的相同介电质材料(例如，氮化硅)制成(104，见图11)。对第二牺牲性栅极盖263和牺牲性栅极侧壁间隔件240的蚀刻在栅极260周围产生空穴265。空穴265将具有下部部分2651和上部部分2652。下部部分2651将曝露栅极260的侧壁和栅极260相对侧上的相邻金属栓塞248。上部部分2652将位于下部部分2651和栅极260的上方，而因此将会曝露在相邻金属栓塞248上的塞盖249的侧壁。应当注意的是，从每个栅极260所蚀刻掉的第二牺牲性栅极盖263和牺牲性栅极侧壁间隔件240的流程104能被定时，使得其在曝露半导体本体210的顶面之前停止(以及如果适用的话，凸起外延源极/漏极区域213)。因此，如图所示，牺牲性栅极侧壁间隔件240的区段241能保持在与栅极260紧紧相邻的半导体本体210的顶面上。
在空穴被形成在围绕在每个栅极260以后，第一介电质层270能被沉积于该ILD层250、塞盖249之上，并进入每个空穴265(106，见图12)。第一介电质层270能被沉积以在每个空穴的下部部分2651中产生气隙271，使得第一介电质层270与每个空穴265的上部部分2652对齐。举例而言，原子层沉积(ALD)工艺能被调整，使得所得到的该第一介电质层270为半共形的，因为它对齐每个空穴的上部部分2652，但仅部分地对齐下部部分2651，在空穴的下部部分2651被对齐或被填补前，在栅极260与相邻金属栓塞248之间的狭小空间的顶部夹断。结果，气隙271(也称为空隙)在栅极260的侧壁和相邻金属栓塞248之间的空穴265的下部部分2651内形成。在已提供的例子中沉积工艺本身被定制以确保该已沉积的第一介电质层夹断，从而在空穴265的下部部分中形成所需的气隙271。
然而，应当理解的是，在第一介电质层270的沉积期间，其它流程能可代替地被用于确保气隙271在空穴265的下部部分2651中形成。举例而言，虽然未示出，T形替代金属栅极能在最初被形成以在T形栅极的宽顶部和相邻金属栓塞之间提供非常狭小的空间。于是，当第一介电质层被沉积，会发生夹断，导致下部部分2651中形成气隙271。在这种情况下，将执行额外蚀刻流程以移除T形栅极的宽顶部，而第一介电质层将重新沉积以便对齐空穴265的上部部分2652。
在任何情况下，第一介电质层270能具体地为与用于塞盖249的不同的介电质。举例而言，第一介电质层270能由碳氧化硅制成。
接下来，第二介电质层275能被沉积在第一介电质层270上，以填补每个空穴265的上部部分2652(108，见图13)。或者，第二介电质层275能由与之前使用于牺牲性栅极侧壁间隔件240的相同介电质材料制成。举例而言，第二介电质层275能由氮化硅制成。在任何情况下，第二介电质层275能由不同于第一介电质层270和塞盖249的介电质材料制成。也就是说，第一介电质层270、第二介电质层275和塞盖249能由三种不同的介电质层材料制成(例如分别为碳氧化硅、氮化硅、以及氧化硅)。在第二介电质层275被沉积之后，第二介电质层275和第一介电质层270能从塞盖249和ILD层250上方被移除(例如，使用化学机械抛光(CMP)工艺)(110)。
然后，另一个ILD层290可以形成(例如，沉积)在ILD层250与塞盖249的实质共平面顶面上，并与其紧紧相邻，以及进一步在每个空穴265上横向地延伸，以便在对齐空穴的上部部分的第一介电质层270的上方，并与其紧紧相邻。而第二介电质层275，其在第一介电质层270上，并填补空穴的上部部分(112，见图14)。ILD层290能由相同于ILD层250和塞盖249的介电质材料制成(例如，氧化硅)。
随后，可以形成中段工艺(MOL)接点，其垂直地延伸穿过ILD层290而向下至每个FET的金属栓塞248与栅极260(114)。用于形成这种MOL接点的流程步骤在以下详细描述，并在图15-22中绘出。应该注意的是，由于空间限制和临界尺寸，通常给定FET的栅极的栅极接点和相同FET的金属栓塞的源极/漏极接点将不会沿着半导体本体的长度完全对准(即图中所示的沿着横截面Z-Z’)。因此，为了说明的用意及避免混杂，图中仅示出两个接点开口和对应接点的形成包括，第一FET201的栅极的栅极接点开口和栅极接点，以及第二finFET202的其中一个金属栓塞的源极/漏极接点开口和源极/漏极接点。然而，应当理解的是，每个finFET 201-202的其它MOL接点也将同时形成于所示的横截面Z-Z’的外侧。
为了在流程114形成MOL接点，第一掩模层281(例如，第一光学聚合层(OPL))能被形成于ILD层290之上(115)。第一掩模层281能与源极/漏极接点开口291进行光蚀刻图案化，其垂直延伸穿过第一掩模层281至ILD层290并且在塞盖249上方对齐(116，见图15)。接下来，源极/漏极接点开口291能延伸穿过ILD层290与塞盖249至下面的金属栓塞248(117，见图16)。由于ILD层290和塞盖249的介电质材料相同(例如，氧化硅)以及由于这介电质材料与第一介电质层270和第二介电质层275不同(例如分别为碳氧化硅和氮化硅)，其对齐/填补每个栅极260上的空穴，延伸源极/漏极接点开口291的工艺能是对第一介电质层270和第二介电质层275材料有选择性的非等向性蚀刻工艺。举例而言，这种非等向性蚀刻流程能是常规氧化硅非等向性蚀刻，其选择性蚀刻在碳氧化硅第一介电质层270和氮化硅第二介电质层275上方的氧化硅ILD层290和氧化硅塞盖249(即以比碳氧化硅或氮化硅更快的速度蚀刻氧化硅)，以不(或仅最低性)蚀刻该第一和该第二介电质层270、275的方式，曝露通过ILD氧化物和氧化塞盖249的金属栓塞248的顶部，从而确保栅极260保持未曝露。因此，由于在系统中曝露的不同材料之间的现有蚀刻选择性，这种蚀刻将会以自我对准的方式进行，使得这种工艺比起诸如光蚀刻重迭控制等工艺变化性更强健。
一旦源极/漏极接点开口291被延伸到金属栓塞248，第一掩模层281能被选择性移除(118)，而第二掩模层282(例如，第二OPL)能被形成于ILD层290上(119，见图17)。这第二掩模层282能与根据该方法形成的每个FET的每个栅极的至少一个栅极接点开口293进行光蚀刻图案化(120，见图18)。具体而言，栅极接点开口293能垂直延伸穿过第二掩模层282至ILD层290，并且能在栅极260上被对准。
然后能执行多个选择性蚀刻工艺以延伸栅极接点开口293至下面的栅极260。具体而言，栅极接点开口293能延伸穿过ILD层290，并停在下面的第二介电质层275上方(121，见图19)。由于ILD层290的介电质材料(例如，氧化硅)不同于栅极260上方的第一介电质层270和第二介电质层275的介电质材料(例如分别为碳氧化硅和氮化硅)，所以延伸栅极接点开口293至下面的第二介电质层275的流程可以是对第一介电质层270和第二介电质层275的材料有选择性的非等向性蚀刻工艺。例如，这蚀刻工艺可以是用于蚀刻源极/漏极接点开口291的相同的常规氧化硅非等向性蚀刻工艺，如上所述。最理想的是，当第二介电质层275的顶面被曝露时，流程121的蚀刻将会停止。然而，由于塞盖249和ILD层290由相同材料制成，所以在与第一介电质层270的上角紧紧相邻的塞盖249中可能形成凹陷。因此，塞盖249的高度和流程121中蚀刻的时间应该预先确定，以确保有足够的幅度让金属栓塞248不被曝露。
每个栅极接点开口293能进一步延伸穿过第二介电质层275的已曝露部分，在下面的第一介电质层270的水平部分上停止(122，见图20)。由于第二介电质层275的介电质材料(例如，氮化硅)不同于第一介电质层270和塞盖249的介电质材料(例如分别为碳氧化硅和氧化硅)，延伸栅极接点开口293至下面的第一介电质层270的水平部分的工艺可以是对第一介电质层270和塞盖249的材料有选择性的非等向性蚀刻工艺。举例而言，这非等向性蚀刻工艺能是常规氮化硅非等向性蚀刻，其选择性蚀刻在碳氧化硅第一介电质层270和氧化硅塞盖249上方的氮化硅第二介电质层275(即以比碳氧化硅或氧化硅更快的速度蚀刻氮化硅)，以移除第二介电质层275。
每个栅极接点开口293能进一步延伸穿过第一介电质层270的水平部分的已曝露部分，在下面的栅极260上停止(123，见图21)。由于第一介电质层270的介电质材料(例如，碳氧化硅)不同于塞盖249的介电质材料(例如，氧化硅)，延伸栅极接点开口293至下面的栅极260的工艺能是对塞盖249的材料有选择性的非等向性蚀刻工艺。举例而言，这非等向性蚀刻工艺能是常规碳氧化硅非等向性蚀刻，其选择性蚀刻在氧化硅塞盖249和栅极260的材料上方的碳氧化硅第一介电质层270(即以比氧化硅或栅极材料更快的速度蚀刻碳氧化硅)，以不(或仅最低性)蚀刻塞盖249的方式从栅极260顶部移除第一介电质层270，从而曝露栅极260而不曝露任何相邻的金属栓塞248。
另外，由于用于将栅极接点开口293延伸至下面栅极260的蚀刻工艺本质上为非等向性的，它将从每个栅极的顶面上移除第一介电质层270的水平部分的已曝露部分，但将完整地留下第一介电质层270的垂直部分，该垂直部分横向定位于与塞盖249相邻并且位于气隙271上方。结果，对于每个栅极，将产生具有下气隙段277和上实心段278的介电质间隔件276(即间隔件)。介电质间隔件276的下气隙段277将包含气隙277，并将横向定位于栅极260的侧壁和栅极260相对侧的相邻金属栓塞248之间。介电质间隔件276的上实心段278将实质上是实心的，将位于下气隙段277上方并将横向定位于与相邻金属栓塞248上的塞盖249的侧壁紧紧相邻。因此，由于在系统中曝露的不同材料之间的现有蚀刻选择性，所以与用于形成源极/漏极接点开口蚀刻工艺一样，用于延伸栅极接点开口293至下面的栅极260的多选择性蚀刻工艺将以自我对准方式执行，使得这种工艺比起诸如光蚀刻重迭控制等工艺变化性更强健。
然后可以选择性移除第二掩模层282(124)而金属能沉积以填补源极/漏极和栅极接点开口291和293，从而分别形成源极/漏极和栅极接点294和295(125，见图22)。在流程122沉积的金属能例如是铜、钨、铝、钴、或任何适于MOL接点形成的其它金属材料。用于沉积各种金属材料以填补接点开口的技术在所属技术领域中众所周知，因此这些细节会从说明书中省略以让读者能够集中在所揭示方法的显著态样上。
应当注意的是，作为用于ILD层290和塞盖249(例如，氧化硅)、用于第二介电质层275(例如，氮化硅)以及用于第一介电质层270(即碳氧化硅)的三种不同介电质材料的结果，能执行上述的选择性蚀刻工艺118，使得源极/漏极接点开口291与金属栓塞248自我对准。也就是说，即使源极/漏极接点开口291宽于金属栓塞和/或偏位，每个源极/漏极接点开口291将落在金属栓塞248上，而稍微有或没有曝露相邻栅极260的风险，以与栅极重迭。因此，所揭示的方法避免了源极/漏极接点294与相邻栅极260的短路。
类似地，由于用于ILD层290和塞盖249(例如，氧化硅)、用于第二介电质层275(例如，氮化硅)以及用于第一介电质层270(例如，碳氧化硅)的三种不同的介电质材料，能执行上述的选择性蚀刻工艺121-123，使得每个栅极接点开口293被自我对准至栅极260。也就是说，即使在栅极接点开口293宽于栅极和/或偏移的情况下，每个栅极接点开口293将稍微有或没有曝露相邻金属栓塞248的风险而降落在栅极260上，以便重迭相邻金属栓塞。因此，栅极接点开口293以及形成在那栅极接点开口293的栅极接点295能具有被介电质间隔件276的上实心段278横向包围的狭小部分，以及在狭小部分上方和在介电质间隔件276的上实心段278横向延伸的更宽部分(例如，延伸到塞盖249上)。因此，本揭示的方法避免了将栅极接点295与相邻金属栓塞248短路。所以，视需要地，栅极接点开口293以及(更具体而言，)栅极接点开口中的栅极接点295能被形成于FET的主动区域上方(例如，如图21和22所示在沟道区域211的正上方)或其附近以最小化装置尺寸而不会有短路到相邻金属栓塞的风险。
参照图22，也在这里揭示了根据上述方法形成的集成电路(IC)结构，以具有一个或多个具有气隙栅极侧壁间隔件的晶体管，以及视需要的在主动区域(例如，CBoA)上或其附近的栅极接点。为了说明的用意，本文揭示的IC结构会在下文中被描述，并在附图中示出关于两个非平面FET(即，第一finFET 201和第二finFET 202)，其共享单个半导体本体(例如，半导体鳍片)，并且具有相同类型的导电性。然而，应当理解的是，所示的FET的数量和类型不止在限制性。举例而言，视需要地，这种IC结构可以包括多鳍片鳍式FET、平面FET、不同类型导电性的FET等。
在任何情况下，本文所揭示的每个IC结构200能并入至少一个晶体管(例如，见第一晶体管201和第二晶体管202)。
每个晶体管201、202能具有半导体本体210(例如，半导体鳍片，如硅鳍片)，并且在该半导体本体210内，沟道区域211横向定位于源极/漏极区域212之间。该沟道区域211能例如掺杂有第一掺杂剂，以便在相对低导电性的水平上具有第一类型导电性。该源极/漏极区域212能例如掺杂有第二掺杂剂，以便在相对高导电性的水平上具有第二类型导电性。视需要地，外延半导体材料(例如，外延硅或任何其它合适的外延半导体材料)能在源极/漏极区域212上生长，从而形成凸起外延源极/漏极区域213(如图所示)。该外延半导体材料能被原位掺杂或随后被注入，使得凸起外延源极/漏极区域213在相对高导电性水平上具有第二类型导电性。视需要地，半导体本体210能被凹陷在源极/漏极区域212处(例如，半导体本体210能具有已凹陷源极/漏极区域212)且外延源极/漏极区域213能位在该已凹陷源极/漏极区域上(未示出)。
每个晶体管201、202还能具有栅极260，其在沟道区域211上相邻于半导体本体210。栅极260能为替代金属栅极。举例而言，该栅极260能包括共形高K栅极介电质层261以及在该栅极介电质层261上的一个或多个金属层262。那些所属技术领域具有技术者将会意识到用于替代金属栅极的介电质和金属层的材料与厚度能被预选以在给定FET导电性类型的情况下达成想要的功函数。或者，该栅极260能为具有例如二氧化硅栅极介电质层和多晶硅掺杂栅极导电层的常规的栅极先制(gate-first)栅极。
每个晶体管201、202还能具有在该源极/漏极区域212上的金属栓塞248(或，如果可以适用的话，在凸起外延源极/漏极区域213)以及在金属栓塞248上方并与其紧紧相邻的塞盖249。该金属栓塞248能由例如钨、钴、铝或任何其它合适的金属栓塞材料制成。该塞盖能为由例如氧化硅所制成的介电质塞盖。
每个晶体管201、202还能具有中段工艺(MOL)接点。具体而言，每个晶体管201、202能包括源极/漏极接点294，其垂直延伸穿过层间介电质(ILD)层290(例如，氧化硅ILD层)进一步向下到金属栓塞248以及栅极接点295，其垂直延伸穿过该ILD层290进一步向下到该栅极260。应当注意的是，由于空间限制和临界尺寸，通常给定FET的栅极接点295到栅极260以及相同FET的源极/漏极接点294到金属栓塞248将不会沿着半导体本体210的长度完全地被对准(即，沿着图22所示的横截面Z-Z’)。因此，为了说明的用意，图22中仅示出了两个MOL接点：第一晶体管201的栅极接点295到栅极260以及第二晶体管202的源极/漏极接点294到其中一个金属栓塞248。然而，应当理解的是，该IC结构200还将包括所示横截面Z-Z’之外的每个晶体管201-202的其它MOL接点。
每个晶体管201、202还能具有介电质间隔件276，其具有下气隙段277和上实心段278。该下气隙段277和上实心段能分别由相同的介电质材料制成，其介电质材料不同于塞盖249的。举例而言，该下气隙段277和该上实心段能分别由碳氧化硅制成。该下气隙段277能包含在该介电质材料内(例如，碳氧化硅内)的气隙271，并且可以被横向定位且紧紧相邻于栅极260的侧壁和栅极260的相对侧的相邻金属栓塞248之间。该上实心段278能位于该下气隙段277上方并且横向定位且紧紧相邻于栅极接点295与金属栓塞248的相邻塞盖249之间。视需要地，该介电质间隔件276能具有在半导体本体210和该下气隙段277之间的附加区段241。这个介电质间隔件276的附加区段241能由不同于上方区段和不同于该塞盖249的介电质材料制成。举例而言，介电质间隔件276的该附加区段241能由氮化硅制成，并且尤其能在制成期间从栅极260蚀刻掉的氮化硅牺牲性栅极侧壁间隔件240的残留部分，如上方有关于该方法所详细讨论过的。
因此，在IC结构200中，介电质间隔件276的上实心段278和下气隙段277、视需要的介电质间隔件276的附加区段241、以及塞盖249与ILD层290能由三种不同的介电质材料制成(例如，分别为碳氧化硅、氮化硅及氧化硅)。
应当注意的是，由于在工艺期间使用不同的介电质材料(参见以上关于该方法的详细讨论)，即使用于那源极/漏极接点的源极/漏极接点开口被图案化为比金属栓塞更宽和/或金属栓塞的偏移，每个源极/漏极接点294将会降落在金属栓塞248上，而介电质间隔件276的上实心段278将会防止源极/漏极接点294至相邻栅极260的短路，以便重迭该栅极。类似地，由于在工艺期间使用不同的介电质材料(参见以上关于该方法的详细讨论)，即使在那栅极接点的栅极接点开口被图案化为比该栅极更宽和/或偏移，每个栅极接点295将会降落在栅极上，而该介电质间隔件276的上实心段278和塞盖249将会防止该栅极接点295到相邻金属栓塞248的短路，以便重迭相邻金属栓塞。因此，如图所示，该栅极接点295能具有狭小部分，其被该介电质间隔件276的上实心段278横向包围，以及更宽部分，其在狭小部分上方，其在该介电质间隔件276的上实心段278上横向地延伸(例如，到该塞盖429上)而不会短路到该下方的金属栓塞248。因此，该栅极接点295能选择性地降落在该FET主动区域的上方(例如，如图22所示的在该沟道区域211的正上方)或与其靠近，以最小化装置尺寸而不会有短路到相邻金属栓塞的风险。
在上述方法和结构中，该晶体管201、202能为N型或P型场效应晶体管。对于N型FET，该沟道区域的第一类型导电性能为P型导电性而该源极/漏极区域的第二类型导电性能为N型导电性；而对于P型FET，该沟道区域的第一类型导电性能为N型导电性而该源极/漏极区域的该第二类型导电性能为P型导电性。那些所属领域中具有技术者将会意识到不同掺杂剂能用来达成不同导电性类型，而该掺杂剂能根据所使用的不同的半导体材料而改变。举例而言，一种具有N型导电性的硅基半导体材料通常掺杂有N型掺杂剂(例如，第5族掺杂剂，如砷(As)、磷(P)或锑(Sb))，而一种具有P型导电性的硅基半导体材料通常掺杂有P型掺杂剂(例如，第3族掺杂剂，如硼(B)或铟(In))。或者，一种具有P型导电性的氮化镓(GaN)基半导体材料通常掺杂有镁(Mg)，而具有N型导电性的氮化镓(GaN)基半导体材料通常掺杂有硅(Si)。那些所属技术领域中具有技术者也将会意识到不同的导电性水平将取决于掺杂剂的相对浓度程度。
上文所描述的方法是使用于集成电路芯片的制造。所得到的集成电路芯片能由制造者以原始晶片形式(意即，作为具有多个未封装芯片的单一晶片)、作为裸晶粒、或以封装形式而销售。在后者的例子中，芯片是安装在单一芯片封装中(诸如塑胶载板，具有固定至主机板或其它较高位阶的载板的导线)或在多重芯片封装中(诸如具有表面互连线或埋入式互连线的任一个或两者的陶瓷载板)。在任何例子中，芯片是与其它芯片、离散电路元件及/或其它讯号处理装置整合成为下列任一者的一部分：(a)中间产品，诸如主机板或(b)终端产品。终端产品可以是包含集成电路芯片的任何产品，范围从玩具及其它低端应用至具有显示器、键盘或其它输入装置、以及中央处理器的先进的计算机产品。
应该理解的是，本文所使用的术语为说明本揭示方法和结构的用途，而不旨在限制。举例而言，如本文中所用的，单数形式“一”、“一种”、“一个”、以及“该”也旨在包括复数形式，除非上下文另有所指。另外，如本文中所用的，术语“包含”和/或“包括”注明所述特征、整数、步骤、操作、元素和/或构件的存在，但不排除存在或附加一个或多个其它特征、整数、步骤、操作、元素、构件和/或其组合。此外，如本文中所用的，诸如“右”、“左”、“垂直的”、“水平的”、“顶部”、“底部”、“上部”、“下部”、“下面”、“底下”、“下伏的”、“上方”、“重迭”、“平行”、“垂直”等术语旨在描述如它们在图中被定向和示出的相对位置(除非另有说明)。举例而言，元件的低层或下部部分将会被定为比该相同元件的高层或更高部分更靠近于该衬底的实质平面底面；水平表面将会实质平行于该衬底的平面底面以及垂直表面将会实质垂直于该衬底的平面底面等。如本文所使用的，诸如“碰触”、“在”、“直接接触”、“靠合”、“直接相邻于”、“紧紧相邻于”等术语旨在表示至少一个元件物理接触另一个元件(没有其它元件分离所述元件)。此外，如本文所使用的，片语“横向定位且相邻于”和“横向定位且紧紧相邻于”是指一个元件被定为于另一个元件的侧面(即，位于另一个元件的一侧)，而不是定位于该其它元件的上方或下方，那些元件在附图中被定向和示出。在以下所附的申请专利范围对应的结构、材料、动作以及相同的所有手段或步骤加上功能元件旨在包括任何结构、材料、或执行与其它特别保护的被保护元件组合功能的动作。
已提出本说明内容的各种具体实施例的说明是为了图解说明而非旨在穷尽或限定所揭示的具体实施例。本领域技术人员明白在不脱离所揭示具体实施例的精神及范畴下仍有许多修改及变体。选择使用于本文的术语以最佳地解释该具体实施例的原理，实际应用或优于出现于市上的技术的技术改善，或致能其他本领域技术人员了解揭示于本文的具体实施例。

Claims (13)

1.一种形成集成电路结构的方法，该方法包含：
在沟道区域形成与半导体本体相邻的栅极，该沟道区域横向定位于源极/漏极区域之间，而该栅极具有牺牲性栅极盖与牺牲性栅极侧壁间隔件；
在该源极/漏极区域上形成具有塞盖的金属栓塞，该金属栓塞横向定位且紧紧相邻于该牺牲性栅极侧壁间隔件；
蚀刻该牺牲性栅极盖与该牺牲性栅极侧壁间隔件以创造具有下部部分及上部部分的空穴，该空穴的该下部部分曝露该栅极的侧壁和该金属栓塞，而该空穴的该上部部分位于该空穴的该下部部分上方及曝露该栅极的顶面；
沉积第一介电质层进入该空穴，使得多个气隙建立在该空穴的该下部部分中且在该栅极的该侧壁与该金属栓塞之间以及使得该第一介电质层衬在该空穴的该上部部分，该第一介电质层的水平部分在该栅极的该顶面上方且与该栅极的该顶面紧紧相邻，而该第一介电质层的垂直部分在该多个气隙上方且横向定位与该塞盖相邻；以及
在沉积该第一介电质层进入该空穴之后，沉积第二介电质层于该第一介电质层的该水平部分上且在该第一介电质层的该垂直部分之间以填补该空穴的该上部部分。
2.如权利要求1所述的方法，该牺牲性栅极盖和该牺牲性栅极侧壁间隔件的蚀刻在曝露该半导体本体的顶面之前停止。
3.如权利要求1所述的方法，该栅极包含替代金属栅极，而该牺牲性栅极盖与该牺牲性栅极侧壁间隔件包含氮化硅。
4.如权利要求1所述的方法，还包含：
该第一介电质层、该第二介电质层以及该塞盖包含三种不同的介电质材料。
5.如权利要求4所述的方法，该第一介电质层包含碳氧化硅，该第二介电质层包含氮化硅，以及该塞盖包含氧化硅。
6.如权利要求4所述的方法，还包含：
从该塞盖上方移除该第一介电质层和该第二介电质层；
在该塞盖上方形成层间介电质层，与其紧紧相邻，并在该空穴上方进一步横向延伸；以及
形成栅极接点，包含：
形成栅极接点开口，其在该栅极上方对准并延伸穿过该层间介电质层至该第二介电质层；
延伸该栅极接点开口穿过该第二介电质层到该第一介电质层；
延伸该栅极接点开口穿过该第一介电质层到该栅极，穿过该第一介电质的该栅极接点开口的延伸包含执行选择性非等向性蚀刻工艺，其从该栅极的顶面移除该第一介电质层的水平部分，并在该气隙上方完整地留下该第一介电质层的垂直区段，以创造一种包含下气隙段和在该下气隙段上方的上实心段的介电质间隔件；以及
以金属填补该栅极接点开口以形成该栅极接点。
7.如权利要求6所述的方法，该栅极接点的形成包含形成该栅极接点落在与主动区域相邻的该栅极上。
8.一种形成集成电路结构的方法，该方法包含：
在沟道区域形成相邻于半导体本体的栅极，每个沟道区域横向定位于源极/漏极区域之间，而每个栅极具有牺牲性栅极盖和牺牲性栅极侧壁间隔件；
在该源极/漏极区域上形成金属栓塞，每个金属栓塞被横向定位且紧紧相邻于至少一个牺牲性栅极侧壁间隔件；
蚀刻该金属栓塞以在该金属栓塞上方形成凹槽；
在该凹槽中形成塞盖；
从每个该栅极选择性蚀刻掉该牺牲性栅极盖和该牺牲性栅极侧壁间隔件以创造空穴，每个空穴具有下部部分和上部部分，每个空穴的该下部部分曝露该栅极的侧壁和相邻的金属栓塞，而每个空穴的该上部部分位于每个空穴的该下部部分上方及曝露该栅极的顶面；
沉积第一介电质层进入该空穴，使得在每个空穴中，多个气隙建立在该下部部分中且在该栅极的该侧壁与该金属栓塞之间，并且使得该第一介电质层衬在每个空穴的该上部部分，该第一介电质层的水平部分在该栅极的该顶面上方且与该栅极的该顶面紧紧相邻，而该第一介电质层的垂直部分在该多个气隙上方且横向定位与该塞盖相邻；
在沉积该第一介电质层进入该空穴之后，沉积第二介电质层在该第一介电质层的该水平部分上且在该第一介电质层的该垂直部分之间的该空穴内以填补该空穴的该上部部分，该塞盖、该第一介电质层和该第二介电质层包含三种不同的介电质材料；
从该塞盖上方移除该第一介电质层和该第二介电质层；
在该塞盖上方形成层间介电质层，与其紧紧相邻，并进一步横向延伸于该空穴上方；以及
形成接点通过该层间介电质层至至少一个栅极以及至少一个金属栓塞。
9.如权利要求8所述的方法，该牺牲性栅极盖和该牺牲性栅极侧壁间隔件的选择性蚀刻在曝露该半导体本体的顶面前停止。
10.如权利要求8所述的方法，该栅极包含替代金属栅极，以及该牺牲性栅极盖与该牺牲性栅极侧壁间隔件包含氮化硅。
11.如权利要求8所述的方法，该第一介电质层包含碳氧化硅，该第二介电质层包含氮化硅，以及该塞盖包含氧化硅。
12.如权利要求8所述的方法，该接点的形成包含：
形成在金属栓塞上的塞盖上方对准的源极/漏极接点开口；
延伸该源极/漏极接点开口至该金属栓塞；
在该层间介电质层上形成掩模层，该掩模层填补该源极/漏极接点开口，并与栅极上方所对准的栅极接点开口被图案化；
延伸该栅极接点开口穿过该层间介电质层至该第二介电质层；
延伸该栅极接点开口穿过该第二介电质层至该第一介电质层；
延伸该栅极接点开口穿过该第一介电质层至该栅极，该栅极接点开口的穿过该第一介电质层的延伸包含执行选择性非等向性蚀刻工艺，其从该栅极顶面移除该第一介电质层的水平区段，并在该气隙上方完整地留下该第一介电质层的垂直区段，以创造包含下气隙段和在该下气隙段上方的上实心段的介电质间隔件；以及
以金属填补该源极/漏极接点开口与该栅极接点开口以形成源极/漏极接点和栅极接点。
13.如权利要求12所述的方法，该栅极接点开口降落在与主动区域相邻的该栅极。
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