TWI663729B - 半導體結構及其製造方法 - Google Patents

半導體結構及其製造方法 Download PDF

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TWI663729B
TWI663729B TW105100179A TW105100179A TWI663729B TW I663729 B TWI663729 B TW I663729B TW 105100179 A TW105100179 A TW 105100179A TW 105100179 A TW105100179 A TW 105100179A TW I663729 B TWI663729 B TW I663729B
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dielectric layer
layer
shaped structure
item
substrate
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TW105100179A
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TW201725726A (zh
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林建廷
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聯華電子股份有限公司
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Priority to TW105100179A priority Critical patent/TWI663729B/zh
Priority to CN201610059555.2A priority patent/CN106941118A/zh
Priority to US15/011,996 priority patent/US10021298B2/en
Priority to US15/390,666 priority patent/US10425580B2/en
Publication of TW201725726A publication Critical patent/TW201725726A/zh
Priority to US16/001,367 priority patent/US10178309B2/en
Priority to US16/447,016 priority patent/US10623638B2/en
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Publication of TWI663729B publication Critical patent/TWI663729B/zh
Priority to US16/821,215 priority patent/US11032472B2/en

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Abstract

在此提供一種半導體結構及其製造方法。此種半導體結構包括一基板、一閘極結構、一第一介電層、以及二氣隙。閘極結構設置在基板上。閘極結構具有相對的二側壁。閘極結構包括一U形結構和一金屬閘極電極。U形結構定義朝向上方的一開口。U形結構包括一功函數層。金屬閘極電極設置在U形結構所定義的開口中。U形結構的一上表面的水平高度低於金屬閘極電極的一上表面的水平高度。第一介電層設置在基板上並鄰接於閘極結構。該二氣隙分別形成在第一介電層和閘極結構相對的二側壁的其中一者之間。

Description

半導體結構及其製造方法
本發明是關於半導體結構及其製造方法。本發明特別是關於包括金屬閘極結構的半導體結構及其製造方法。
在半導體結構中，任何導電-介電-導電結構都可能展現出電容。不希望其產生的電容，例如形成在閘極結構和源極/汲極區之間的電容、或形成在閘極結構和槽形接觸結構(slot contact)之間的電容等等，可能不利地影響半導體裝置的操作。隨著半導體結構的縮小，這個問題變得更加緊要。
本發明是關於降低不希望其產生的電容的解決方案。
根據一些實施例，提供一種半導體結構。此種半導體結構包括一基板、一閘極結構、一第一介電層、以及二氣隙(air gap)。閘極結構設置在基板上。閘極結構具有相對的二側壁。閘極結構包括一U形結構和一金屬閘極電極。U形結構定義朝向上方的一開口。U形結構包括一功函數層(work function layer)。金屬閘極電極設置在U形結構所定義的開口中。U形結構的一上表 面的水平高度低於金屬閘極電極的一上表面的水平高度。第一介電層設置在基板上並鄰接於閘極結構。二氣隙分別形成在第一介電層和閘極結構相對的二側壁的其中一者之間。
根據一些實施例，提供一種半導體結構的製造方法。此種方法包括下列步驟。首先，提供一基板。形成一犧牲閘極結構在基板上。犧牲閘極結構具有相對的二側壁。形成二犧牲間隔物分別在犧牲閘極結構相對的二側壁上。形成一第一介電層在基板上並鄰接於犧牲閘極結構。接著，移除犧牲閘極結構，形成一開口。形成一閘極結構在開口中。閘極結構具有相對的二側壁。閘極結構包括一U形結構和一金屬閘極電極。U形結構定義朝向上方的一開口。U形結構包括一功函數層。金屬閘極電極形成在U形結構所定義的開口中。U形結構的一上表面的水平高度低於金屬閘極電極的一上表面的水平高度。之後，移除該二犧牲間隔物，形成二氣隙分別位於第一介電層和閘極結構相對的二側壁的其中一者之間。
為了對本發明之上述及其他方面有更佳的瞭解，下文特舉較佳實施例，並配合所附圖式，作詳細說明如下：
102‧‧‧基板
104‧‧‧鰭
1041、1042‧‧‧源極/汲極區
106‧‧‧閘極結構
106s‧‧‧側壁
108‧‧‧U形結構
108o‧‧‧開口
108t‧‧‧上表面
110‧‧‧金屬閘極電極
110t‧‧‧上表面
112‧‧‧功函數層
114‧‧‧高介電常數介電層
116‧‧‧蝕刻停止層
118‧‧‧介面介電層
120‧‧‧接觸結構蝕刻停止層
122‧‧‧第一介電層
122t‧‧‧上表面
124‧‧‧氣隙
126‧‧‧第二介電層
128‧‧‧接觸結構
130‧‧‧第三介電層
132‧‧‧接觸結構
202‧‧‧基板
204‧‧‧鰭
206‧‧‧介面介電層
208‧‧‧犧牲閘極結構
2081‧‧‧矽層
2082‧‧‧硬遮罩層
208s‧‧‧側壁
210‧‧‧犧牲間隔物
212‧‧‧接觸結構蝕刻停止層
214‧‧‧第一介電層
214t‧‧‧上表面
216‧‧‧開口
2180‧‧‧層
2200‧‧‧層
2220‧‧‧層
2240‧‧‧材料
218‧‧‧高介電常數介電層
220‧‧‧蝕刻停止層
222‧‧‧功函數層
224‧‧‧金屬閘極電極
224t‧‧‧上表面
226‧‧‧閘極結構
226s‧‧‧側面
228‧‧‧U形結構
228o‧‧‧開口
228t‧‧‧上表面
230‧‧‧阻障層
232‧‧‧氣隙
234‧‧‧第二介電層
第1圖繪示根據實施例的半導體結構。
第2A~2I圖繪示半導體結構在根據實施例的製造流程中的不同階段。
以下將參照所附圖式，對於各種實施例進行詳細的描述。為了清楚起見，圖式中的元件可能並未反映出其真實的尺寸。此外，還可能省略一些元件。可以預期的是，一實施例中的元件和特徵可能被有利地納入至另一實施例中，而並未另外再作列舉。
請參照第1圖，其提供根據實施例的半導體結構。半導體結構包括一基板102、一閘極結構106、一第一介電層122、以及二氣隙124。閘極結構106設置在基板102上。閘極結構106具有相對的二側壁106s。第一介電層122設置在基板102上並鄰接於閘極結構106。二氣隙124分別形成在第一介電層122和閘極結構106相對的二側壁106s的其中一者之間。
以下提供半導體結構進一步的細節。在一些實施例中，閘極結構106是直接設置在基板102上。或者，如第1圖所示，半導體結構還可包括一鰭(fin)104。鰭104可如第1圖所示為一絕緣層上覆矽(silicon on insulator,SOI)基板或矽基板(Si substrate)的一部分、或以磊晶方式形成於任何材料的基板上，而閘極結構106是設置在鰭104上並橫越鰭104。更具體地說，鰭104可在一第一方向上延伸，而閘極結構106可在不同於第一方向的一第二方向上延伸。在第1圖中，第一方向是紙面上的水平方向，而第二方向是垂直於紙面的方向。鰭104中可包括二源極/汲極區1041和1042，分別設置在閘極結構106的二側。
根據一些實施例，半導體結構還可包括一介面介電層(interfacial dielectric layer)118。介面介電層118係設置在基板102上，而閘極結構106是設置在介面介電層118上。因此，能 夠減輕基板102和閘極結構106之間的潛在介面問題。
閘極結構106可為一金屬閘極結構。在這樣的情況下，閘極結構106包括一U形結構108和一金屬閘極電極110。U形結構108定義朝向上方的一開口108o。U形結構108包括一功函數層112。根據一些實施例，U形結構108還可包括一高介電常數介電層(high-k dielectric layer)114，其中功函數層112是設置在高介電常數介電層114上。根據一些實施例，U形結構108還可選擇性地包括一蝕刻停止層(etch stop layer)116，其中蝕刻停止層116是設置在功函數層112和高介電常數介電層114之間。根據一些實施例，U形結構108還可包括一阻障層(未示於第1圖)，其中阻障層是設置在功函數層112上。這些層共同構成U形結構108。金屬閘極電極110設置在U形結構108所定義的開口108o中。U形結構108的一上表面108t的水平高度低於金屬閘極電極110的一上表面110t的水平高度。此外，在一些實施例中，如第1圖所示，氣隙124並未超過U形結構108的上表面108t的水平高度。在一些實施例中，如第1圖所示，U形結構108的上表面108t的水平高度和金屬閘極電極110的上表面110t的水平高度低於第一介電層122的一上表面122t的水平高度。
半導體結構還可包括一接觸結構蝕刻停止層(contact etch stop layer)120。接觸結構蝕刻停止層120設置在基板102上(或者在某些情況下是設置在鰭104上)並位於閘極結構106二側，而第一介電層122是設置在接觸結構蝕刻停止層120上。
半導體結構還可包括一第二介電層126。第二介電 層126密封氣隙124。根據一些實施例，第二介電層126可例如藉由電漿輔助化學氣相沉積(plasma-enhanced chemical vapor deposition,PECVD)由氮化矽形成。
半導體結構還可包括其他半導體裝置中的典型元件。舉例來說，如第1圖所示，半導體結構還可包括複數接觸結構128如槽形接觸結構、一第三介電層130、和複數接觸結構132。接觸結構128通過第一介電層122地設置在閘極結構106的二側。第三介電層130設置在第一介電層122上。接觸結構132通過第三介電層130地設置，並連接至槽形接觸結構128和閘極結構106。
在根據上述實施例的半導體結構中，典型地設置在閘極結構的側壁上的間隔物(spacer)被氣隙所取代。由於氣隙的介電常數低於間隔物的介電常數，因此能夠降低電容，特別是形成在閘極結構和源極/汲極區之間的電容、或形成在閘極結構和槽形接觸結構之間的電容等等。如此一來，便能夠改善裝置的表現。
以下提供根據實施例的半導體結構的製造方法。請參照第2A圖，首先提供一基板202。基板202可為一矽基板、一含矽基板、或一絕緣層覆矽(silicon-on-insulator,SOI)基板等等。根據一些實施例，可形成一鰭204在基板202上，如第2A圖所示。鰭204可由矽形成。根據一些實施例，可形成一介面介電層206在基板202上，例如在鰭204上，如第2A圖所示。介面介電層206可由二氧化矽形成。形成一犧牲閘極結構208在基板202上，例如在鰭204和介面介電層206上。犧牲閘極結構208橫越鰭204。犧牲閘極結構208具有相對的二側壁208s。在一些實施 例中，犧牲閘極結構208包括一矽層2081和選擇性的一硬遮罩層2082，但實施例並不受限於此。
請參照第2B圖，形成二犧牲間隔物210分別在犧牲閘極結構208相對的二側壁208s上。犧牲間隔物210可由氮化矽、或氧碳氮化矽(SiOCN)等等形成。雖然未示於圖式，在一些實施例中，源極/汲極區藉由使用犧牲閘極結構208和犧牲間隔物210作為遮罩的自對準植入製程形成在鰭204中。
請參照第2C圖，可選擇性地形成一接觸結構蝕刻停止層212在基板202上並覆蓋犧牲閘極結構208。接著，形成一第一介電層214在接觸結構蝕刻停止層212上。第一介電層214的材料較佳地係不同於接觸結構蝕刻停止層212的材料。接著，可進行一平坦化製程，例如一化學機械平坦化(chemical mechanical planarization,CMP)製程，直到移除硬遮罩層2082並曝露出矽層2081為止。如此一來，便形成了形成在基板202上並鄰接於犧牲閘極結構208的接觸結構蝕刻停止層212和第一介電層214。
之後，移除犧牲閘極結構208，形成一開口216，如第2D圖所示。在接下來的步驟中，將形成一閘極結構226在開口216中。
請參照第2E圖，以共形的方式，依序形成由用於形成一高介電常數介電層的材料形成的一層2180、由用於形成一蝕刻停止層的材料形成的一層2200、和由用於形成一功函數層的材料形成的一層2220在第一介電層214上和開口216中，其中 層2180和層2200為選擇性地形成。接著，形成用於形成一金屬閘極電極的一材料2240在層2200上和填充至開口216中。用於形成高介電常數介電層的材料可為HfO2、HfSiO4、HfSiON、Al2O3、La2O3、Ta2O5、Y2O3、ZrO2、SrTiO3、ZrSiO4、HfZrO4、SBT(SrBi2Ta2O9)、PZT(PbZrxTi1-xO3)、或BST(BaxSr1-xTiO3)等等。用於形成蝕刻停止層的材料可為TaN等等。用於形成功函數層的材料可為TiN等等(用於p型半導體裝置)、或可為TiAl或TiAlN等等(用於n型半導體裝置)。用於形成金屬閘極電極的材料可為鎢、鋁或銅等等。
請參照第2F圖，進行一移除製程，以形成閘極結構226在開口216中。閘極結構226具有相對的二側壁226s。閘極結構226包括一U形結構228和一金屬閘極電極224。U形結構228定義朝向上方的一開口228o。U形結構228至少包括功函數層222。根據一些實施例，U形結構228還可包括高介電常數介電層218，其中功函數層222是形成在高介電常數介電層218上。根據一些實施例，U形結構228還可包括蝕刻停止層220，其中蝕刻停止層220是形成在功函數層222和高介電常數介電層218之間。根據一些實施例，如第2G圖(第2F圖的替代形式)所示，U形結構228還可包括一阻障層230，其中阻障層230是形成在功函數層222上。阻障層230可由TiN等等形成。金屬閘極電極224形成在U形結構228所定義的開口2280中。U形結構228的一上表面228t的水平高度低於金屬閘極電極224的一上表面224t的水平高度。這有利於進一步地降低不希望其產生的電容。
舉例來說，可進行一平坦化製程，例如一CMP製 程，直到再次曝露出第一介電層214。在一些實施例中，可再進行一乾蝕刻製程和一溼蝕刻製程，以移除部分U形結構228和金屬閘極電極224的材料，使得U形結構228的上表面228t的水平高度和金屬閘極電極224的上表面224t的水平高度低於第一介電層214的一上表面214t的水平高度。這有利於進一步地降低不希望其產生的電容。
請參照第2H圖，移除犧牲間隔物210，形成二氣隙232分別位於第一介電層214和閘極結構226相對的二側壁226s的其中一者之間。犧牲間隔物210的移除可藉由一乾蝕刻製程和一溼蝕刻製程來進行。藉由移除犧牲間隔物210和形成氣隙232，能夠降低半導體結構中不希望其產生的電容。如此一來，便能夠改善裝置的表現。
請參照第2I圖，還可形成一第二介電層234在第一介電層214上，使得第二介電層234密封氣隙232.。第二介電層234可藉由PECVD由氮化矽形成。在一些實施例中，如第2I圖所示，第二介電層234的材料可能填充至氣隙232中，氣隙232因此縮小並變成水滴狀。形成在原本的氣隙232的側壁上的第二介電層234的材料可能是大約數埃，而形成在原本的氣隙232的底部上的第二介電層234的材料可能是大約數十埃。因此，氣隙232並未超過U形結構228的上表面228t的水平高度。之後，可進行一移除製程，例如一CMP製程，以移除不需要的第二介電層234的部分。然而，留下的第二介電層234的部分應足以密封氣隙232。
之後，可以再進行其他半導體裝置的製造流程中的 典型步驟，例如用於形成如第1圖所示的槽形接觸結構、第三介電層、和接觸結構的步驟。
綜上所述，雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。

Claims (20)

  1. 一種半導體結構，包括：一基板；一閘極結構，設置在該基板上，該閘極結構具有相對的二側壁，該閘極結構包括：一U形結構，定義朝向上方的一開口，該U形結構包括一功函數層；和一金屬閘極電極，設置在該U形結構所定義的該開口中，其中該U形結構的一上表面的水平高度低於該金屬閘極電極的一上表面的水平高度；一第一介電層，設置在該基板上並鄰接於該閘極結構；以及二氣隙，分別形成在該第一介電層和該閘極結構相對的該二側壁的其中一者之間，其中該二氣隙於該基板的一上表面的一法線方向上不與該U形結構重疊。
  2. 如申請專利範圍第1項所述之半導體結構，其中該二氣隙並未超過該U形結構的該上表面的水平高度。
  3. 如申請專利範圍第1項所述之半導體結構，其中該U形結構的該上表面的水平高度和該金屬閘極電極的該上表面的水平高度低於該第一介電層的一上表面的水平高度。
  4. 如申請專利範圍第1項所述之半導體結構，更包括：一第二介電層，密封該二氣隙。
  5. 如申請專利範圍第4項所述之半導體結構，其中該第二介電層是藉由電漿輔助化學氣相沉積由氮化矽形成。
  6. 如申請專利範圍第1項所述之半導體結構，更包括：一介面介電層，設置在該基板上，其中該閘極結構是設置在該介面介電層上。
  7. 如申請專利範圍第1項所述之半導體結構，其中該U形結構更包括一高介電常數介電層，其中該功函數層是設置在該高介電常數介電層上。
  8. 如申請專利範圍第7項所述之半導體結構，其中該U形結構更包括一蝕刻停止層，其中該蝕刻停止層是設置在該功函數層和該高介電常數介電層之間。
  9. 如申請專利範圍第8項所述之半導體結構，其中該U形結構更包括一阻障層，其中該阻障層是設置在該功函數層上。
  10. 如申請專利範圍第1項所述之半導體結構，更包括：一鰭，設置在該基板上，其中該閘極結構是設置在該鰭上並橫越該鰭。
  11. 一種半導體結構的製造方法，包括：提供一基板；形成一犧牲閘極結構在該基板上，該犧牲閘極結構具有相對的二側壁；形成二犧牲間隔物分別在該犧牲閘極結構相對的該二側壁上；形成一第一介電層在該基板上並鄰接於該犧牲閘極結構；移除該犧牲閘極結構，形成一開口；形成一閘極結構在該開口中，該閘極結構具有相對的二側壁，該閘極結構包括：一U形結構，定義朝向上方的一開口，該U形結構包括一功函數層；和一金屬閘極電極，形成在該U形結構所定義的該開口中，其中該U形結構的一上表面的水平高度低於該金屬閘極電極的一上表面的水平高度；移除該二犧牲間隔物，形成二氣隙分別位於該第一介電層和該閘極結構相對的該二側壁的其中一者之間，其中該二氣隙於該基板的一上表面的一法線方向上不與該U形結構重疊。
  12. 如申請專利範圍第11項所述之半導體結構的製造方法，其中該二氣隙並未超過該U形結構的該上表面的水平高度。
  13. 如申請專利範圍第11項所述之半導體結構的製造方法，其中形成該閘極結構的步驟包括移除部分該U形結構和該金屬閘極電極的材料，使得該U形結構的該上表面的水平高度和該金屬閘極電極的該上表面的水平高度低於該第一介電層的一上表面的水平高度。
  14. 如申請專利範圍第11項所述之半導體結構的製造方法，更包括：形成一第二介電層在該第一介電層上，使得該第二介電層密封該二氣隙。
  15. 如申請專利範圍第14項所述之半導體結構的製造方法，其中該第二介電層是藉由電漿輔助化學氣相沉積由氮化矽形成。
  16. 如申請專利範圍第11項所述之半導體結構的製造方法，更包括：形成一介面介電層在該基板上，其中該犧牲閘極結構是形成在該介面介電層上。
  17. 如申請專利範圍第11項所述之半導體結構的製造方法，其中該U形結構更包括一高介電常數介電層，其中該功函數層是形成在該高介電常數介電層上。
  18. 如申請專利範圍第17項所述之半導體結構的製造方法，其中該U形結構更包括一蝕刻停止層，其中該蝕刻停止層是形成在該功函數層和該高介電常數介電層之間。
  19. 如申請專利範圍第18項所述之半導體結構的製造方法，其中該U形結構更包括一阻障層，其中該阻障層是形成在該功函數層上。
  20. 如申請專利範圍第11項所述之半導體結構的製造方法，更包括：形成一鰭在該基板上，其中該犧牲閘極結構是形成在該鰭上並橫越該鰭。
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