JP5208011B2 - メモリ回路装置 - Google Patents

メモリ回路装置 Download PDF

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Publication number
JP5208011B2
JP5208011B2 JP2009031380A JP2009031380A JP5208011B2 JP 5208011 B2 JP5208011 B2 JP 5208011B2 JP 2009031380 A JP2009031380 A JP 2009031380A JP 2009031380 A JP2009031380 A JP 2009031380A JP 5208011 B2 JP5208011 B2 JP 5208011B2
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JP
Japan
Prior art keywords
memory
memory cell
column
writing
circuit device
Prior art date
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Expired - Fee Related
Application number
JP2009031380A
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English (en)
Japanese (ja)
Other versions
JP2010186525A (ja
JP2010186525A5 (enExample
Inventor
和宏 津村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP2009031380A priority Critical patent/JP5208011B2/ja
Priority to TW099102455A priority patent/TWI498910B/zh
Priority to US12/701,144 priority patent/US8259516B2/en
Priority to KR1020100012949A priority patent/KR101657309B1/ko
Priority to CN201010115304.4A priority patent/CN101807428B/zh
Publication of JP2010186525A publication Critical patent/JP2010186525A/ja
Publication of JP2010186525A5 publication Critical patent/JP2010186525A5/ja
Application granted granted Critical
Publication of JP5208011B2 publication Critical patent/JP5208011B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/143—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using laser-fusible links
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G11C17/165—Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Landscapes

  • Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Read Only Memory (AREA)
  • Static Random-Access Memory (AREA)
  • Non-Volatile Memory (AREA)
JP2009031380A 2009-02-13 2009-02-13 メモリ回路装置 Expired - Fee Related JP5208011B2 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2009031380A JP5208011B2 (ja) 2009-02-13 2009-02-13 メモリ回路装置
TW099102455A TWI498910B (zh) 2009-02-13 2010-01-28 記憶體電路裝置
US12/701,144 US8259516B2 (en) 2009-02-13 2010-02-05 Memory circuit including row and column selection for writing information
KR1020100012949A KR101657309B1 (ko) 2009-02-13 2010-02-11 메모리 회로
CN201010115304.4A CN101807428B (zh) 2009-02-13 2010-02-11 存储器电路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009031380A JP5208011B2 (ja) 2009-02-13 2009-02-13 メモリ回路装置

Publications (3)

Publication Number Publication Date
JP2010186525A JP2010186525A (ja) 2010-08-26
JP2010186525A5 JP2010186525A5 (enExample) 2012-01-26
JP5208011B2 true JP5208011B2 (ja) 2013-06-12

Family

ID=42559793

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009031380A Expired - Fee Related JP5208011B2 (ja) 2009-02-13 2009-02-13 メモリ回路装置

Country Status (5)

Country Link
US (1) US8259516B2 (enExample)
JP (1) JP5208011B2 (enExample)
KR (1) KR101657309B1 (enExample)
CN (1) CN101807428B (enExample)
TW (1) TWI498910B (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105244060B (zh) * 2015-09-25 2019-01-01 北京兆易创新科技股份有限公司 一种基于芯片的测试处理方法及装置
JP6390683B2 (ja) * 2016-09-28 2018-09-19 ミツミ電機株式会社 半導体集積回路
JP6932552B2 (ja) 2017-05-31 2021-09-08 Hoya株式会社 マスクブランク、転写用マスクの製造方法及び半導体デバイスの製造方法
CN110956993A (zh) * 2019-12-12 2020-04-03 中国科学院微电子研究所 基于电阻分压读取的阻变型存储单元
CN116030871B (zh) * 2023-03-23 2023-06-23 长鑫存储技术有限公司 一种修调电路和存储器

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63263828A (ja) * 1987-04-21 1988-10-31 Mitsubishi Electric Corp 半導体集積回路
JPH0249297A (ja) * 1988-08-10 1990-02-19 Sharp Corp 記憶装置
JPH0637254A (ja) 1992-07-20 1994-02-10 Fujitsu Ltd 半導体集積回路における基準電圧発生回路
JP3308608B2 (ja) * 1992-10-13 2002-07-29 株式会社日立製作所 信号処理装置および磁気記録再生装置
JP3615009B2 (ja) * 1997-02-12 2005-01-26 株式会社東芝 半導体記憶装置
JPH11306782A (ja) * 1998-04-24 1999-11-05 Sharp Corp 半導体記憶装置
JP2003110029A (ja) * 2001-06-27 2003-04-11 Fuji Electric Co Ltd 半導体装置、そのトリミング方法およびデータ記憶回路
JP2005100538A (ja) * 2003-09-25 2005-04-14 Toshiba Corp 不揮発性半導体記憶装置及びこれを用いた電子装置
JP4698583B2 (ja) * 2004-05-12 2011-06-08 スパンション エルエルシー 半導体装置及びその制御方法
JP2006164408A (ja) * 2004-12-08 2006-06-22 Toshiba Corp 不揮発性半導体記憶装置及びそのデータ消去方法。
JP4825436B2 (ja) * 2005-03-29 2011-11-30 ルネサスエレクトロニクス株式会社 半導体記憶装置及び半導体装置
US7457178B2 (en) * 2006-01-12 2008-11-25 Sandisk Corporation Trimming of analog voltages in flash memory devices
KR100684909B1 (ko) * 2006-01-24 2007-02-22 삼성전자주식회사 읽기 에러를 방지할 수 있는 플래시 메모리 장치
JP5028967B2 (ja) * 2006-11-15 2012-09-19 富士通セミコンダクター株式会社 半導体記憶装置および半導体記憶装置の制御方法
JP4852004B2 (ja) * 2007-07-26 2012-01-11 セイコーインスツル株式会社 トリミング方法
KR100933852B1 (ko) * 2007-12-28 2009-12-24 주식회사 하이닉스반도체 불휘발성 메모리 소자 및 그 동작 방법

Also Published As

Publication number Publication date
KR101657309B1 (ko) 2016-09-13
US8259516B2 (en) 2012-09-04
US20100208532A1 (en) 2010-08-19
JP2010186525A (ja) 2010-08-26
KR20100092899A (ko) 2010-08-23
TWI498910B (zh) 2015-09-01
CN101807428B (zh) 2014-04-23
TW201115584A (en) 2011-05-01
CN101807428A (zh) 2010-08-18

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