JP5151438B2 - 半導体装置およびその製造方法、ならびに半導体装置用基板およびその製造方法 - Google Patents
半導体装置およびその製造方法、ならびに半導体装置用基板およびその製造方法 Download PDFInfo
- Publication number
- JP5151438B2 JP5151438B2 JP2007318817A JP2007318817A JP5151438B2 JP 5151438 B2 JP5151438 B2 JP 5151438B2 JP 2007318817 A JP2007318817 A JP 2007318817A JP 2007318817 A JP2007318817 A JP 2007318817A JP 5151438 B2 JP5151438 B2 JP 5151438B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- terminal
- semiconductor device
- die pad
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
ここで、図1は、本発明による半導体装置の一実施の形態を示す概略断面図であり、図2は、端子部の拡大図である。また図3は、ダイパッドの拡大図であり、図4は、本発明による半導体装置用基板の一実施の形態を示す概略断面図である。また図5は、本発明による半導体装置用基板の製造方法の一実施の形態を示す工程図であり、図6は、基板上に端子部(ダイパッド)を形成する工程を示す図である。また図7は、本発明による半導体装置の製造方法の一実施の形態を示す工程図である。
図1において、半導体装置10はLGAタイプの樹脂封止型半導体装置であり、各々が内部端子面13bと外部端子面13aとを有する複数の端子部13と、この端子部13の配列の略中央に設けられたダイパッド12とを備えている。各端子部13の外部端子面13aおよびダイパッド12の外面12aは、同一平面上に並んでいる。
図4において、半導体装置用基板20は、金属基板21と、この金属基板21上に設けられ、各々が内部端子面13bと外部端子面13aとを有する複数の端子部13と、金属基板21上に設けられ、内面12bと外面12aとを有するダイパッド12とを備えている。また金属基板21の所定位置に開口22が形成されている。なお各端子部13の外部端子面13aおよびダイパッド12の外面12aは、同一平面上に並んでいる。
11 封止樹脂部
12 ダイパッド
12c ニッケル(Ni)層
12d 金層
12e 銀層
12f 貴金属めっき層
12R 粗面
13 端子部
13c ニッケル(Ni)層
13d 金層
13e 銀層
13f 貴金属めっき層
13R 粗面
15 半導体素子
16 電気絶縁性材料
17 ワイヤ(接続部)
20 半導体装置用基板
21 金属基板
22 開口
Claims (4)
- 各々が内部端子面と外部端子面とを有する複数の端子部と、
ダイパッドと、
ダイパッド上に搭載され、各端子部の内部端子面と接続部により電気的に接続された半導体素子と、
各端子部の外部端子面を外方へ露出させるようにダイパッド、端子部、半導体素子、および接続部を封止する封止樹脂部とを備え、
各端子部の外部端子面およびダイパッドの外面は同一平面上に並び、
各端子部は、上面が粗面となるニッケル層と、ニッケル層上に設けられたボンディング用貴金属めっき層とを有し、
該貴金属めっき層の合計厚みは、該貴金属めっき層の表面がニッケル層の粗面を維持する程度の厚みであって、0.5μm以下の厚みとなり、
該貴金属めっき層は、ニッケル層上に設けられた金層と、金層上に設けられるとともに最表面側に位置する銀層とからなることを特徴とする半導体装置。 - 少なくともダイパッドの内面に撥水処理加工がなされていることを特徴とする請求項1記載の半導体装置。
- 金属基板と、
該金属基板上に設けられ、各々が内部端子面と外部端子面とを有する複数の端子部と、 該金属基板上に設けられ、内面と外面とを有するダイパッドとを備え、
各端子部の外部端子面およびダイパッドの外面は同一平面上に並び、
各端子部は、上面が粗面となるニッケル層と、ニッケル層上に設けられたボンディング用貴金属めっき層とを有し、
該貴金属めっき層の合計厚みは、該貴金属めっき層の表面がニッケル層の粗面を維持する程度の厚みであって、0.5μm以下の厚みとなり、
該貴金属めっき層は、ニッケル層上に設けられた金層と、金層上に設けられるとともに最表面側に位置する銀層とからなることを特徴とする半導体装置用基板。 - 少なくともダイパッドの内面に撥水処理加工がなされていることを特徴とする請求項3記載の半導体装置用基板。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007318817A JP5151438B2 (ja) | 2007-12-10 | 2007-12-10 | 半導体装置およびその製造方法、ならびに半導体装置用基板およびその製造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007318817A JP5151438B2 (ja) | 2007-12-10 | 2007-12-10 | 半導体装置およびその製造方法、ならびに半導体装置用基板およびその製造方法 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012264264A Division JP5418928B2 (ja) | 2012-12-03 | 2012-12-03 | 半導体装置およびその製造方法、ならびに半導体装置用基板およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009141274A JP2009141274A (ja) | 2009-06-25 |
JP5151438B2 true JP5151438B2 (ja) | 2013-02-27 |
Family
ID=40871562
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007318817A Active JP5151438B2 (ja) | 2007-12-10 | 2007-12-10 | 半導体装置およびその製造方法、ならびに半導体装置用基板およびその製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP5151438B2 (ja) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10763196B1 (en) | 2019-03-22 | 2020-09-01 | Ohkuchi Materials Co., Ltd. | Lead frame |
US10777492B1 (en) | 2019-03-25 | 2020-09-15 | Ohkuchi Materials Co., Ltd. | Substrate for mounting semiconductor element |
KR20200115101A (ko) * | 2019-03-28 | 2020-10-07 | 오쿠치 마테리얼스 가부시키가이샤 | 반도체 소자 탑재용 부품, 리드 프레임 및 반도체 소자 탑재용 기판 |
US10811346B2 (en) | 2019-03-22 | 2020-10-20 | Ohkuchi Materials Co., Ltd. | Lead frame |
US10903150B2 (en) | 2019-03-22 | 2021-01-26 | Ohkuchi Materials Co., Ltd. | Lead frame |
US11404286B2 (en) | 2019-03-22 | 2022-08-02 | Ohkuchi Materials Co., Ltd. | Lead frame |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5565668B2 (ja) * | 2010-01-25 | 2014-08-06 | 大日本印刷株式会社 | 半導体素子載置部材と配線導体との組合体、半導体素子載置基板およびその製造方法、ならびに半導体素子パッケージおよびその製造方法 |
US9263374B2 (en) | 2010-09-28 | 2016-02-16 | Dai Nippon Printing Co., Ltd. | Semiconductor device and manufacturing method therefor |
JP5699331B2 (ja) * | 2011-03-29 | 2015-04-08 | 大日本印刷株式会社 | 半導体装置および半導体装置の製造方法 |
DE102011008163A1 (de) * | 2011-01-10 | 2012-07-12 | Bayer Material Science Ag | Beschichtung für metallische Zellelement-Werkstoffe einer Elektrolysezelle |
JP6099370B2 (ja) * | 2012-11-21 | 2017-03-22 | Shマテリアル株式会社 | 半導体素子搭載用基板及びその製造方法 |
JP2014123592A (ja) * | 2012-12-20 | 2014-07-03 | Ibiden Co Ltd | プリント配線板の製造方法及びプリント配線板 |
JP6443979B2 (ja) * | 2015-01-30 | 2018-12-26 | 大口マテリアル株式会社 | リードフレーム及びその製造方法 |
JP2015092635A (ja) * | 2015-02-05 | 2015-05-14 | 大日本印刷株式会社 | 半導体装置および半導体装置の製造方法 |
JP6299004B2 (ja) * | 2015-04-30 | 2018-03-28 | Shマテリアル株式会社 | 半導体素子搭載用基板及び半導体装置、並びにそれらの製造方法 |
JP6557814B2 (ja) * | 2015-12-15 | 2019-08-14 | 大口マテリアル株式会社 | 半導体素子搭載用基板及びその製造方法、並びに半導体装置の製造方法 |
US9653385B1 (en) * | 2016-05-26 | 2017-05-16 | Sdi Corporation | Lead frame |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63114242A (ja) * | 1986-10-31 | 1988-05-19 | Toshiba Corp | 半導体装置 |
JPH05102346A (ja) * | 1991-10-09 | 1993-04-23 | Nec Corp | 樹脂封止半導体装置 |
JPH11111909A (ja) * | 1997-10-07 | 1999-04-23 | Seiichi Serizawa | 半導体装置用リードフレーム |
JP2000178799A (ja) * | 1998-12-15 | 2000-06-27 | Dainippon Printing Co Ltd | 多層めっき工程の管理方法 |
JP3869849B2 (ja) * | 2000-04-25 | 2007-01-17 | 九州日立マクセル株式会社 | 半導体装置の製造方法 |
JP3626075B2 (ja) * | 2000-06-20 | 2005-03-02 | 九州日立マクセル株式会社 | 半導体装置の製造方法 |
JP2002289739A (ja) * | 2001-03-23 | 2002-10-04 | Dainippon Printing Co Ltd | 樹脂封止型半導体装置および半導体装置用回路部材とその製造方法 |
JP2003037215A (ja) * | 2001-07-26 | 2003-02-07 | Mitsui Mining & Smelting Co Ltd | 電子部品実装用基板及び電子部品実装用基板の製造方法 |
JP2003303919A (ja) * | 2002-04-10 | 2003-10-24 | Hitachi Ltd | 半導体装置及びその製造方法 |
JP4027147B2 (ja) * | 2002-04-19 | 2007-12-26 | 大日本印刷株式会社 | パッケージ基板の製造方法 |
-
2007
- 2007-12-10 JP JP2007318817A patent/JP5151438B2/ja active Active
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10763196B1 (en) | 2019-03-22 | 2020-09-01 | Ohkuchi Materials Co., Ltd. | Lead frame |
KR20200112661A (ko) * | 2019-03-22 | 2020-10-05 | 오쿠치 마테리얼스 가부시키가이샤 | 반도체 소자 탑재용 기판 |
US10811346B2 (en) | 2019-03-22 | 2020-10-20 | Ohkuchi Materials Co., Ltd. | Lead frame |
US10903150B2 (en) | 2019-03-22 | 2021-01-26 | Ohkuchi Materials Co., Ltd. | Lead frame |
US11404286B2 (en) | 2019-03-22 | 2022-08-02 | Ohkuchi Materials Co., Ltd. | Lead frame |
US10777492B1 (en) | 2019-03-25 | 2020-09-15 | Ohkuchi Materials Co., Ltd. | Substrate for mounting semiconductor element |
KR20200115101A (ko) * | 2019-03-28 | 2020-10-07 | 오쿠치 마테리얼스 가부시키가이샤 | 반도체 소자 탑재용 부품, 리드 프레임 및 반도체 소자 탑재용 기판 |
US10847451B2 (en) | 2019-03-28 | 2020-11-24 | Ohkuchi Materials Co., Ltd. | Device for mounting semiconductor element, lead frame, and substrate for mounting semiconductor element |
Also Published As
Publication number | Publication date |
---|---|
JP2009141274A (ja) | 2009-06-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5151438B2 (ja) | 半導体装置およびその製造方法、ならびに半導体装置用基板およびその製造方法 | |
US6933594B2 (en) | Leadless plastic chip carrier with etch back pad singulation | |
US6995460B1 (en) | Leadless plastic chip carrier with etch back pad singulation | |
KR101026586B1 (ko) | 반도체 장치의 개선된 습기 신뢰성 및 개선된 납땜가능성을 위한 리드프레임을 포함하는 반도체 장치 및 그제조 방법 | |
US6808962B2 (en) | Semiconductor device and method for fabricating the semiconductor device | |
JP2002289739A (ja) | 樹脂封止型半導体装置および半導体装置用回路部材とその製造方法 | |
JP4984253B2 (ja) | 半導体装置の製造方法および半導体装置用基板の製造方法 | |
TWI421910B (zh) | 半導體元件基板、其製造方法及半導體裝置 | |
TWI479626B (zh) | 導線架基板及其製造方法以及半導體裝置 | |
KR100551576B1 (ko) | 반도체 장치 및 그 제조방법 | |
JP2011077519A (ja) | リードフレーム及びその製造方法 | |
JP5948881B2 (ja) | 半導体装置用リードフレーム | |
JP4329678B2 (ja) | 半導体装置に用いるリードフレームの製造方法 | |
US7825501B2 (en) | High bond line thickness for semiconductor devices | |
JP5418928B2 (ja) | 半導体装置およびその製造方法、ならびに半導体装置用基板およびその製造方法 | |
JP2004207381A (ja) | 配線基板及びその製造方法並びに半導体装置 | |
JP2016165005A (ja) | 半導体装置およびその製造方法、ならびに半導体装置用基板およびその製造方法 | |
JP5500130B2 (ja) | 樹脂封止型半導体装置および半導体装置用回路部材 | |
JP2014053638A (ja) | 半導体装置およびその製造方法、ならびに半導体装置用基板およびその製造方法 | |
JP3992877B2 (ja) | 樹脂封止型半導体装置の製造方法 | |
JP5609911B2 (ja) | 樹脂封止型半導体装置および半導体装置用回路部材 | |
JP5482743B2 (ja) | 樹脂封止型半導体装置および半導体装置用回路部材 | |
JP5807815B2 (ja) | 半導体装置およびその製造方法、ならびに半導体装置用基板およびその製造方法 | |
JP5403435B2 (ja) | 半導体装置およびその製造方法、ならびに半導体装置用基板およびその製造方法 | |
KR20130059580A (ko) | 반도체 패키지 및 그의 제조방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20101027 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20110711 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110715 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110913 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120330 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120525 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20121106 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20121119 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20151214 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5151438 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |