JP5403435B2 - 半導体装置およびその製造方法、ならびに半導体装置用基板およびその製造方法 - Google Patents
半導体装置およびその製造方法、ならびに半導体装置用基板およびその製造方法 Download PDFInfo
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- JP5403435B2 JP5403435B2 JP2011197521A JP2011197521A JP5403435B2 JP 5403435 B2 JP5403435 B2 JP 5403435B2 JP 2011197521 A JP2011197521 A JP 2011197521A JP 2011197521 A JP2011197521 A JP 2011197521A JP 5403435 B2 JP5403435 B2 JP 5403435B2
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- Prior art keywords
- terminal
- substrate
- semiconductor device
- die pad
- protrusion
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
11 封止樹脂部
12 ダイパッド
12a 外面
12b 内面
12c 突起部
13 端子部
13a 外部端子面
13b 内部端子面
13c 突起部
15 半導体素子
16 電気絶縁性材料
17 ワイヤ(接続部)
18 永久レジスト層
20 半導体装置用基板
21 基板
22 開口
32 レジスト層
40、41 ドライフィルムレジストシート
42、44 剥離シート
Claims (4)
- 各々が内部端子面と外部端子面とを有する複数の端子部と、
ダイパッドと、
ダイパッド上に搭載され、各端子部の内部端子面と接続部により電気的に接続された半導体素子と、
各端子部の外部端子面を外方へ露出させるようにダイパッド、端子部、半導体素子、および接続部を封止する封止樹脂部とを備え、
各端子部の外部端子面およびダイパッドの外面は同一平面上に並び、
各端子部の内部端子面側に、外方に突出する突起部が形成され、
ダイパッドの内面側に、外方に突出する突起部が形成され、
ダイパッドの突起部より下方部分と、端子部の突起部より下方部分との間、および隣接する端子部の突起部より下方部間に、永久レジスト層が形成され、
端子部の厚さは、25μm以下であることを特徴とする半導体装置。 - 永久レジスト層はポリイミド系樹脂からなり、封止樹脂部はエポキシ系樹脂からなることを特徴とする請求項1に記載の半導体装置。
- 基板と、
基板上に設けられ、各々が内部端子面と外部端子面とを有する複数の端子部と、
基板上に設けられ、内面と外面とを有するダイパッドとを備え、
各端子部の外部端子面およびダイパッドの外面は同一平面上に並び、
各端子部の内部端子面側に、外方に突出する突起部が形成され、
ダイパッドの内面側に、外方に突出する突起部が形成され、
ダイパッドの突起部より下方部分と端子部の突起部より下方部分との間、および隣接する端子部の突起部より下方部間に、永久レジスト層が形成され、
端子部の厚さは、25μm以下であることを特徴とする半導体装置用基板。 - 永久レジスト層はポリイミド系樹脂からなることを特徴とする請求項3に記載の半導体装置用基板。
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JP2011197521A JP5403435B2 (ja) | 2011-09-09 | 2011-09-09 | 半導体装置およびその製造方法、ならびに半導体装置用基板およびその製造方法 |
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JP2011197521A JP5403435B2 (ja) | 2011-09-09 | 2011-09-09 | 半導体装置およびその製造方法、ならびに半導体装置用基板およびその製造方法 |
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JP2007332564A Division JP4984253B2 (ja) | 2007-12-25 | 2007-12-25 | 半導体装置の製造方法および半導体装置用基板の製造方法 |
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JP2013228276A Division JP5807815B2 (ja) | 2013-11-01 | 2013-11-01 | 半導体装置およびその製造方法、ならびに半導体装置用基板およびその製造方法 |
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JP5403435B2 true JP5403435B2 (ja) | 2014-01-29 |
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JP2002289739A (ja) * | 2001-03-23 | 2002-10-04 | Dainippon Printing Co Ltd | 樹脂封止型半導体装置および半導体装置用回路部材とその製造方法 |
JP2005244033A (ja) * | 2004-02-27 | 2005-09-08 | Torex Semiconductor Ltd | 電極パッケージ及び半導体装置 |
JP5001542B2 (ja) * | 2005-03-17 | 2012-08-15 | 日立電線株式会社 | 電子装置用基板およびその製造方法、ならびに電子装置の製造方法 |
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