JP3869849B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP3869849B2 JP3869849B2 JP2006072498A JP2006072498A JP3869849B2 JP 3869849 B2 JP3869849 B2 JP 3869849B2 JP 2006072498 A JP2006072498 A JP 2006072498A JP 2006072498 A JP2006072498 A JP 2006072498A JP 3869849 B2 JP3869849 B2 JP 3869849B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
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- H01L2224/05554—Shape in top view being square
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H—ELECTRICITY
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
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- H01—ELECTRIC ELEMENTS
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Description
8)この第8の製造工程は、図1,2に示すように、切り出された個々の半導体装置の樹脂封止体2の底面の金属層8a,8bに金薄膜層8cをフラッシュ法または電解メッキあるいは無電解メッキは等によって蒸着する。
2a 電極パッド
4 ワイヤ
7 樹脂パッケージ
7a,7b 溝
8,8a,8b 金属層
8c 金属層
9 金属基板
10,10a,10b レジスト膜
11 樹脂封止体
12 金薄膜層
13,14 金属層
S,S1 ,S2切断線
E 半導体素子が搭載される領域
Claims (1)
- 可撓性平板状の金属基板に、パターニングされた金属層を形成した電着フレームを形成する工程と、前記電着フレームのパターニングされた前記金属層に複数の半導体素子を隣接して搭載する工程と、前記パターニングされた金属層に搭載される各半導体素子間に形成された外部導出用の金属層に、前記隣接する各半導体素子の電極パッドをワイヤで所定間隔を設けて電気的に共通接続するワイヤボンディング工程と、前記電着フレームに搭載されて配線がなされた半導体素子を樹脂封止する樹脂封止工程と、前記金属基板を剥離して樹脂封止体を得る剥離工程と、前記半導体素子が複数封止された樹脂封止体を、パターニングされた金属層の切断マークの間により切断部位が設定され、切断部位を切断することによって個々の半導体装置に切断する切り出し工程とを含む半導体装置の製造方法であって、
前記金属層は、金属基板の一面にレジスト膜をパターンニングして、金属層を形成する金属基板面を露呈させて、薄膜層を電着して形成した後に薄膜金属層が形成されたものであり、
また、半導体素子が搭載される金属層と外部導出用の金属層の形成領域の外周において、前記金属層の切断マーク間毎に切断部位を設定したことを特徴とする半導体装置の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006072498A JP3869849B2 (ja) | 2000-04-25 | 2006-03-16 | 半導体装置の製造方法 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000124102 | 2000-04-25 | ||
JP2006072498A JP3869849B2 (ja) | 2000-04-25 | 2006-03-16 | 半導体装置の製造方法 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2001078791A Division JP2002016181A (ja) | 2000-04-25 | 2001-03-19 | 半導体装置、その製造方法、及び電着フレーム |
Publications (3)
Publication Number | Publication Date |
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JP2006196922A JP2006196922A (ja) | 2006-07-27 |
JP2006196922A5 JP2006196922A5 (ja) | 2006-09-21 |
JP3869849B2 true JP3869849B2 (ja) | 2007-01-17 |
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Application Number | Title | Priority Date | Filing Date |
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JP2006072498A Expired - Lifetime JP3869849B2 (ja) | 2000-04-25 | 2006-03-16 | 半導体装置の製造方法 |
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Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5098452B2 (ja) * | 2007-06-11 | 2012-12-12 | 住友金属鉱山株式会社 | 半導体装置の製造方法 |
JP5151438B2 (ja) * | 2007-12-10 | 2013-02-27 | 大日本印刷株式会社 | 半導体装置およびその製造方法、ならびに半導体装置用基板およびその製造方法 |
KR20140058698A (ko) | 2009-06-24 | 2014-05-15 | 아오이 전자 주식회사 | 반도체 장치 및 반도체 장치의 제조 방법 |
EP2337068A1 (en) | 2009-12-18 | 2011-06-22 | Nxp B.V. | Pre-soldered leadless package |
JP5779748B2 (ja) | 2010-11-02 | 2015-09-16 | リコー電子デバイス株式会社 | 半導体パッケージ及び電子部品実装体 |
TWI533380B (zh) * | 2011-05-03 | 2016-05-11 | 旭德科技股份有限公司 | 封裝結構及其製作方法 |
JP2012084938A (ja) * | 2012-02-03 | 2012-04-26 | Sumitomo Metal Mining Co Ltd | 半導体装置製造用基板 |
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2006
- 2006-03-16 JP JP2006072498A patent/JP3869849B2/ja not_active Expired - Lifetime
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JP2006196922A (ja) | 2006-07-27 |
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