JP5122106B2 - 炭素含有膜エッチング方法及びこれを利用した半導体素子の製造方法 - Google Patents
炭素含有膜エッチング方法及びこれを利用した半導体素子の製造方法 Download PDFInfo
- Publication number
- JP5122106B2 JP5122106B2 JP2006272137A JP2006272137A JP5122106B2 JP 5122106 B2 JP5122106 B2 JP 5122106B2 JP 2006272137 A JP2006272137 A JP 2006272137A JP 2006272137 A JP2006272137 A JP 2006272137A JP 5122106 B2 JP5122106 B2 JP 5122106B2
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- Japan
- Prior art keywords
- carbon
- containing film
- gas
- etching
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02115—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material being carbon, e.g. alpha-C, diamond or hydrogen doped carbon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02362—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment formation of intermediate layers, e.g. capping layers or diffusion barriers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
- Electrodes Of Semiconductors (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2005-0096164 | 2005-10-12 | ||
| KR1020050096164A KR100780944B1 (ko) | 2005-10-12 | 2005-10-12 | 탄소함유막 식각 방법 및 이를 이용한 반도체 소자의 제조방법 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2007110112A JP2007110112A (ja) | 2007-04-26 |
| JP2007110112A5 JP2007110112A5 (enExample) | 2009-11-19 |
| JP5122106B2 true JP5122106B2 (ja) | 2013-01-16 |
Family
ID=37911496
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2006272137A Active JP5122106B2 (ja) | 2005-10-12 | 2006-10-03 | 炭素含有膜エッチング方法及びこれを利用した半導体素子の製造方法 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US7494934B2 (enExample) |
| JP (1) | JP5122106B2 (enExample) |
| KR (1) | KR100780944B1 (enExample) |
| CN (1) | CN100570830C (enExample) |
Families Citing this family (30)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7517804B2 (en) * | 2006-08-31 | 2009-04-14 | Micron Technologies, Inc. | Selective etch chemistries for forming high aspect ratio features and associated structures |
| US20100327413A1 (en) * | 2007-05-03 | 2010-12-30 | Lam Research Corporation | Hardmask open and etch profile control with hardmask open |
| KR100950553B1 (ko) * | 2007-08-31 | 2010-03-30 | 주식회사 하이닉스반도체 | 반도체 소자의 콘택 형성 방법 |
| JP5226296B2 (ja) * | 2007-12-27 | 2013-07-03 | 東京エレクトロン株式会社 | プラズマエッチング方法、プラズマエッチング装置、制御プログラム及びコンピュータ記憶媒体 |
| US8133819B2 (en) | 2008-02-21 | 2012-03-13 | Applied Materials, Inc. | Plasma etching carbonaceous layers with sulfur-based etchants |
| JP5064319B2 (ja) * | 2008-07-04 | 2012-10-31 | 東京エレクトロン株式会社 | プラズマエッチング方法、制御プログラム及びコンピュータ記憶媒体 |
| JP2010041028A (ja) | 2008-07-11 | 2010-02-18 | Tokyo Electron Ltd | 基板処理方法 |
| JP2010283213A (ja) * | 2009-06-05 | 2010-12-16 | Tokyo Electron Ltd | 基板処理方法 |
| EP2525416A2 (en) * | 2011-05-17 | 2012-11-21 | Intevac, Inc. | Method for rear point contact fabrication for solar cells |
| US8916054B2 (en) * | 2011-10-26 | 2014-12-23 | International Business Machines Corporation | High fidelity patterning employing a fluorohydrocarbon-containing polymer |
| JP5932599B2 (ja) * | 2011-10-31 | 2016-06-08 | 株式会社日立ハイテクノロジーズ | プラズマエッチング方法 |
| TWI497586B (zh) * | 2011-10-31 | 2015-08-21 | Hitachi High Tech Corp | Plasma etching method |
| KR20130107628A (ko) | 2012-03-22 | 2013-10-02 | 삼성디스플레이 주식회사 | 트렌치 형성 방법, 금속 배선 형성 방법, 및 박막 트랜지스터 표시판의 제조 방법 |
| CN103377991B (zh) * | 2012-04-18 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | 沟槽的形成方法 |
| US9165783B2 (en) * | 2012-11-01 | 2015-10-20 | Applied Materials, Inc. | Method of patterning a low-k dielectric film |
| CN104425222B (zh) * | 2013-08-28 | 2018-09-07 | 中芯国际集成电路制造(上海)有限公司 | 图形化方法 |
| CN104425221B (zh) * | 2013-08-28 | 2017-12-01 | 中芯国际集成电路制造(上海)有限公司 | 图形化方法 |
| KR102362065B1 (ko) | 2015-05-27 | 2022-02-14 | 삼성전자주식회사 | 반도체 소자의 제조 방법 |
| JP6748354B2 (ja) * | 2015-09-18 | 2020-09-02 | セントラル硝子株式会社 | ドライエッチング方法及びドライエッチング剤 |
| JP6907217B2 (ja) * | 2016-01-20 | 2021-07-21 | アプライド マテリアルズ インコーポレイテッドApplied Materials,Incorporated | 横方向ハードマスク凹部縮小のためのハイブリッドカーボンハードマスク |
| KR102329531B1 (ko) * | 2016-03-28 | 2021-11-23 | 주식회사 히타치하이테크 | 플라스마 처리 방법 및 플라스마 처리 장치 |
| KR102582762B1 (ko) * | 2017-05-11 | 2023-09-25 | 주성엔지니어링(주) | 기판 처리 방법 및 그를 이용한 유기 발광 소자 제조 방법 |
| KR102372892B1 (ko) * | 2017-08-10 | 2022-03-10 | 삼성전자주식회사 | 집적회로 소자의 제조 방법 |
| US10978302B2 (en) | 2017-11-29 | 2021-04-13 | Lam Research Corporation | Method of improving deposition induced CD imbalance using spatially selective ashing of carbon based film |
| JP7366918B2 (ja) | 2018-03-16 | 2023-10-23 | ラム リサーチ コーポレーション | 誘電体における高アスペクト比フィーチャのプラズマエッチング化学物質 |
| CN108538712B (zh) * | 2018-04-25 | 2020-08-25 | 武汉新芯集成电路制造有限公司 | 接触孔的制造方法 |
| CN111446204B (zh) * | 2019-01-17 | 2024-02-06 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
| KR20220030249A (ko) | 2019-06-24 | 2022-03-10 | 램 리써치 코포레이션 | 선택적 탄소 증착 |
| JP7321059B2 (ja) * | 2019-11-06 | 2023-08-04 | 東京エレクトロン株式会社 | プラズマ処理方法及びプラズマ処理装置 |
| JP7721455B2 (ja) * | 2022-01-31 | 2025-08-12 | 東京エレクトロン株式会社 | プラズマ処理方法及びプラズマ処理システム |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR960000375B1 (ko) * | 1991-01-22 | 1996-01-05 | 가부시끼가이샤 도시바 | 반도체장치의 제조방법 |
| JPH0590224A (ja) * | 1991-01-22 | 1993-04-09 | Toshiba Corp | 半導体装置の製造方法 |
| JP3282292B2 (ja) * | 1993-06-07 | 2002-05-13 | ソニー株式会社 | ドライエッチング方法 |
| US5545579A (en) * | 1995-04-04 | 1996-08-13 | Taiwan Semiconductor Manufacturing Company | Method of fabricating a sub-quarter micrometer channel field effect transistor having elevated source/drain areas and lightly doped drains |
| JP3400918B2 (ja) * | 1996-11-14 | 2003-04-28 | 東京エレクトロン株式会社 | 半導体装置の製造方法 |
| KR20010042419A (ko) * | 1998-04-02 | 2001-05-25 | 조셉 제이. 스위니 | 낮은 k 유전체를 에칭하는 방법 |
| US6703265B2 (en) * | 2000-08-02 | 2004-03-09 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of manufacturing the same |
| JP3526438B2 (ja) * | 2000-09-07 | 2004-05-17 | 株式会社日立製作所 | 試料のエッチング処理方法 |
| JP2002093778A (ja) * | 2000-09-11 | 2002-03-29 | Toshiba Corp | 有機膜のエッチング方法およびこれを用いた半導体装置の製造方法 |
| US6835663B2 (en) * | 2002-06-28 | 2004-12-28 | Infineon Technologies Ag | Hardmask of amorphous carbon-hydrogen (a-C:H) layers with tunable etch resistivity |
| US20040079726A1 (en) * | 2002-07-03 | 2004-04-29 | Advanced Micro Devices, Inc. | Method of using an amorphous carbon layer for improved reticle fabrication |
| KR20040003652A (ko) * | 2002-07-03 | 2004-01-13 | 주식회사 하이닉스반도체 | 반도체 소자의 게이트 형성 방법 |
| JP2004031892A (ja) | 2002-12-27 | 2004-01-29 | Fujitsu Ltd | アモルファスカーボンを用いた半導体装置の製造方法 |
| KR100510558B1 (ko) * | 2003-12-13 | 2005-08-26 | 삼성전자주식회사 | 패턴 형성 방법 |
| US7115524B2 (en) * | 2004-05-17 | 2006-10-03 | Micron Technology, Inc. | Methods of processing a semiconductor substrate |
-
2005
- 2005-10-12 KR KR1020050096164A patent/KR100780944B1/ko not_active Expired - Fee Related
-
2006
- 2006-08-29 US US11/512,026 patent/US7494934B2/en active Active
- 2006-10-03 JP JP2006272137A patent/JP5122106B2/ja active Active
- 2006-10-11 CN CNB2006101321471A patent/CN100570830C/zh active Active
Also Published As
| Publication number | Publication date |
|---|---|
| JP2007110112A (ja) | 2007-04-26 |
| US20070082483A1 (en) | 2007-04-12 |
| KR20070040633A (ko) | 2007-04-17 |
| CN1956154A (zh) | 2007-05-02 |
| US7494934B2 (en) | 2009-02-24 |
| KR100780944B1 (ko) | 2007-12-03 |
| CN100570830C (zh) | 2009-12-16 |
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